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Digital Electronics
Introduce the J/K flip-flop and provide an excitation table and a sample timing analysis.
Review flip-flop clock parameters. Introduce the transparent D-latch. Discuss flip-flop asynchronous inputs.
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Inputs
. .
. .
Outputs
Clock
D
D Q
CLK
Q
0 1
Q
1 0
0 1
CLK
Q
: Rising Edge of Clock
Q=D=1
Q=D=1
No Change
Q=D=0
Q=D=0
No Change
D
CLK
J
J CLK K Q
K 0 1 0 1
CLK
Q
Q0
No Change Clear Set Toggle
0 1 1
0 1
Q0
NO CHANGE
SET
NO CHANGE
Q J K CLK
Clock Edges
Positive Edge Transition
1 0
CLK
Q
0 1
Q
1 0
0 1
CLK
Q
: Rising Edge of Clock
CLK
Q
0 1
Q
1 0
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0 1
CLK
Q
: Falling Edge of Clock
K 0 1 0 1
CLK
Q
Q0
0 0 1 1
0 1
Q0
K 0 1 0 1
CLK
Q
Q0
0 0 1 1
0 1
Q0
10
Flip-Flop Timing
Data Input (D,J, or K) 1 0
tS
Setup Time
Positive Edge Clock 1
0
tH
Hold Time
Setup Time (tS): The time interval before the active transition of the clock signal during which the data input (D, J, or K) must be maintained. Hold Time (tH): The time interval after the active transition of the clock signal during which the data input (D, J, or K) must be maintained.
11
Asynchronous Inputs
Asynchronous inputs (Preset & Clear) are used to override the clock/data inputs and force the outputs to a predefined state. The Preset (PR) input forces the output to:
D PR Q
Q 1 & Q 0
The Clear (CLR) input forces the output to:
CLK CLR
Q 0 & Q 1
PR
PRESET
CLR
CLEAR
CLK
CLOCK
D
DATA
Q
0 1 1 0 1
Q
1 0 0 1 1 Asynchronous Preset Asynchronous Clear ILLEGAL CONDITION
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1 1 0 1 0
1 1 1 0 0
X X X
0 1 X X X
Q=D=0
Clocked
Q=D=0
Clocked
Q=D=1
Clocked
Q=D=1
Clocked
Q=D=0
Clocked
Q
Q=1
Preset
Q=1
Preset
PR CLR D CLK
Q=0
Clear
13
Transparent D-Latch
EN
D Q
D X 0 1
Q
Q0
Q
Q0
0 1
0 1
1 0
EN
EN: Enable
14
Q D
EN
15
16
74LS74: D Flip-Flop
18
19
74LS75: D Latch
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