Institute Name – Veermata Jijabai Technological Institute,

Mumbai.
Class – Second year B. Tech in Electrical Engineering.
Course Name – Analog Digital Circuits .
Subject – ADC Lab Experiments.

Experiment 5 : Study of D and JK-Flip

Flops.

Students Name and college ID – (Group No. – 8)

Registration Student Names

ID

201030031 Ashutosh Dubey

201030068 Krushna Padawale

201030009 Adithyakrishna Viswanathan

201030037 Shaileshkumar Dahekar

201030019 Vijay Modhave

 Experiment 5 : Study of D and JK-Flip Flops

AIM :-

1. Study the operation and working principle of JK and D flip-flops.

2. Study the procedure for conducting the experiment in the lab.

Objectives:
To construct JK and D flip-flops and verity their truth tables.

Apparatus:
1. IC 7473
2. IC 7474
3. IC Trainer kit
4. Connecting patch chords
5. Connecting wires
6. Led (output)
7. Bread board

Theory:
In digital circuits, a FIipFIop is a term referring to an electronic circuit (a bi
stable multi-vibrator ) that has two stable states and thereby is
capable of serving as one bit of memory.
A flip-flop is usually controlled by one or two control signals and /or a
gate or clock signal. The output often includes the complement as well as
the normal output.

What is a JK Flip-Flop?
The JK Flip-Flop is a sequential device with 3 inputs (J, K, CLK (clock
signal)) and 2 outputs (Q and Q’). J and K are control inputs. These control
inputs are named “J” and “K” in honor of their inventor Jack Kilby.
What Does D-Type Flip-Flop Mean?
A D-type flip-flop is a clocked flip-flop which has two stable states. A D-type
flip-flop operates with a delay in input by one clock cycle. Thus, by
cascading many D-type flip-flops delay circuits can be created, which are
used in many applications such as in digital television systems.
A D-type flip-flop is also known as a D flip-flop or delay flip-flop.

JK-FIip-FIop:

The JK flip-flop augments the behaviour of the SR flip-flop (J = Set, K =

Reset) by interpreting the S = R = 1 condition as a “flip“ or toggle command.
Specifically, the combination J = 1, K = 0 is a command to set the flip-
flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and
the combination J = K = 1 is a command to toggle the flip-flop, i.e., change
its output to the logical complement of its current value.

The PRESET and CLEAR inputs of a JK Flip-Flop :

There are two very important additional inputs in the JK Flip-Flop. PRESET
input is used to directly put a “1” in the Q output on the JK Flip-Flop. CLEAR
input is used to directly put a “0” in the Q output on the JK Flip-Flop.
The PRESET and CLEAR inputs of the JK Flip-Flop are
asynchronous, which means that they will have an immediate
effect on the Q and Q’ outputs regardless of the state of the
clock and / or the J and K inputs.

It is important NOT to simultaneously activate the CLEAR and

PRESET inputs.

The Flip-Flop may or may not have a small bubble in the

PRESET or CLEAR inputs which indicate that they are active
low. The complete diagram of the JK flip-flop is as shown in the
diagram above.

D-FIip-FIop:

The Q output always takes on the state of the D input at the moment of a
rising clock edge. (or falling edge if the clock input is active low) It is
called the D flip-flop for this reason, since the output takes the
value of the D input or Data input, and Delays it by one clock count. The D
flip-flop can be interpreted as a primitive memory cell, zero-order hold, or
delay line.

D Flip-flop :

D Flip-flops are used as a part of memory storage elements and data

processors as well. D flip-flop can be built using NAND gate or with NOR
gate. Due to its versatility they are available as IC packages. The major
applications of D flip-flop are to introduce delay in timing circuit, as a
buffer, sampling data at specific intervals. D flip-flop is simpler in terms of
wiring connection compared to JK flip-flop. Here we are using NAND gates
for demonstrating the D flip flop.

Whenever the clock signal is LOW, the input is never going to affect the
output state. The clock has to be high for the inputs to get active. Thus, D
flip-flop is a controlled Bi-stable latch where the clock signal is the control
signal. Again, this gets divided into positive edge triggered D flip flop and
negative edge triggered D flip-flop. Thus, the output has two stable states
based on the inputs which have been discussed below.
INTRO: D FLIP FLOP WITH PRESET AND CLEAR

- The flip flop is a basic building block of sequential logic circuits.

- It is a circuit that has two stable states and can store one bit of state
information.

- The output changes state by signals applied to one or more control inputs.

- The basic D Flip Flop has a D (data) input and a clock input and outputs
Q and Q (the inverse of Q).

- Optionally it may also include the PR (Preset) and CLR (Clear) control
inputs.

The preset and clear input are active-low, because there are an inverting
bubble at that input lead on the block symbol, just like the negative edge-
trigger clock inputs.

When the preset input is activated, the flip-flop will be reset (Q=0, not-Q=1)
regardless of any of the synchronous inputs or the clock. When the clear
input is activated, the flip-flop will be set (Q=1, not-Q=0), regardless of any
of the synchronous inputs or the clock. So, what happens if both preset and
clear inputs are not activated ( both of them 0 ) ? Surprise, surprise: we get
an invalid state on the output, where Q and not-Q go to the same state.

when both preset and clear inputs are activated then the flip flop will work
normally.
We will Verify in our IC lab to design and simulate the D flip flop with
preset and clear.

The link of the Lab performance video :-

https://drive.google.com/file/d/14IckoGaf38gwTD3wQccvYWGvO9Dms
z5g/view?usp=drivesdk

Characteristic Tables :-

A characteristic table defines the logical properties of a flip-flop by

describing its operation in tabular form. The characteristic tables of three
types of flip-flops are presented In Table 5.1 . They define the next state
(i.e., the state that results from a clock transition)
Characteristic Equations :

The logical properties of a flip-flop, as described in the characteristic table,

can be Expressed algebraically with a characteristic equation. For the D
flip-flop, we have the Characteristic equation

Q(t + 1) = D

Which states that the next state of the output will be equal to the value of
input D in the Present state. The characteristic equation for the JK flip-flop
can be derived from the Characteristic table or from the circuit of Fig. 5.12 .
We obtain

Q(t + 1) = JQ + KQ
Circuit diagrams:

JK FIip-FIop:

Fig.6.3 JK Flip Flop using IC 7476(Power connection, ground connection,

the above are two JK Flip-Flops in a single IC)

Truth table:

Inputs Outputs
Preset Clear Clock J K Q
0 0 x x x 1 1
0 1 x x x 1 0
1 0 x x x 0 1
1 1 0 0 0
1 1 1 0 1 0
1 1 0 1 0 1
1 1 1 1 Toogle state
1 1 0 x x Q
Symbol:

D-FIip-FIop using JK FIip-FIop:

Inputs Output
s
Prese Clear Clock D Q
t
L H X X H L
H L X X L H
L L X X H H
H H H H L
H H L L H
H H L X Q0

Fig.6.4 D-Flip-Flop using JK Flip-Flop & its Truth table :

With pre-set and clear :-

Symbol:

Procedure:
1. Construct the RS flip flop as shown in figures 6.1 & 6.2.
2. Feed the logic signals from the logic input switches observe the
logic outputs on the logic Level LED indicators.
3. Verify the corresponding truth tables.
4. Construct JK - flip flop (fig 6.3) and repeat step 2 and 3.
5. Construct D - Flip flop (fig 6.4) and repeat step 2 and 3.
6. Construct T - Flip flop (fig 6.5) and repeat step 2 and 3.
Circuit diagram :
Result:

For JK flip-flops :-

For D Flip-Flop :-
For JK Flip-Flop :-
Conclusion :-
Thus we have studied D and JK flip flop And also verified it with its
Characteristic table And got the results as per desired output.

Inference:
Different types of Flip flops ( JK & D ) are Constructed using IC 7476 and
hence their truth tables are verified.

Outcomes:
After finishing this experiment students are able to construct RS, JK, D and
T flip-flops and verity their truth tables.

Viva Questions:
1. Difference between latch and flip-flop.
2. List the applications of flip-flops.
3. Explain the operation of JK flip-flop.
4. What is meant by level triggering and edge triggering in flip-flops.
5. Explain the difference between +ve edge and -ve edge triggering.
6. Which type of edge triggering is used in IC 7474 J-K Flip-flop?
7. Explain the preset and clear inputs of a flip-flop and why are these
Called asynchronous Inputs.
8. Where do the D-FF’s are used and why it is called a delay flip flop.
9. Explain the race around problem in JK-FF and how it is eliminated in
master slave JK- FF.