Opamp Design

Lecture 230 Design of Two-Stage Op Amps (3/27/10) Page 230-1
CMOS Analog Circuit Design P.E. Allen - 2010

LECTURE 230 DESIGN OF TWO-STAGE OP AMPS
LECTURE OUTLINE
Outline
Steps in Designing an Op Amp
Design Procedure for a Two-Stage Op Amp
Design Example of a Two-Stage Op Amp
Right Half Plane Zero
PSRR of the Two-Stage Op Amp
Summary
CMOS Analog Circuit Design, 2
nd
Edition Reference
Pages 269-293
STEPS IN DESIGNING A CMOS OP AMP
Steps
1.) Choosing or creating the basic structure of the op amp.
This step is results in a schematic showing the transistors and their interconnections.
This diagram does not change throughout the remainder of the design unless the
specifications cannot be met, then a new or modified structure must be developed.
2.) Selection of the dc currents and transistor sizes.
Most of the effort of design is in this category.
Simulators are used to aid the designer in this phase.
3.) Physical implementation of the design.
Layout of the transistors
Floorplanning the connections, pin-outs, power supply buses and grounds
Extraction of the physical parasitics and re-simulation
Verification that the layout is a physical representation of the circuit.
4.) Fabrication
5.) Measurement
Verification of the specifications
Modification of the design as necessary
Design Inputs
Boundary conditions:
1. Process specification (V
T
, K', C
ox
, etc.)
2. Supply voltage and range
3. Supply current and range
4. Operating temperature and range
Requirements:
1. Gain
2. Gain bandwidth
3. Settling time
4. Slew rate
5. Common-mode input range, ICMR
6. Common-mode rejection ratio, CMRR
7. Power-supply rejection ratio, PSRR
8. Output-voltage swing
9. Output resistance
10. Offset
11. Noise
12. Layout area
Outputs of Op Amp Design
The basic outputs of design are:
1.) The topology
2.) The dc currents
3.) The W and L values of transistors
4.) The values of components
060625-06
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
CL
+
-
Cc
W/L ratios
Topology
DC Currents
L
W
Op amp circuit
or systems
specifications
Design of
CMOS
Op Amps
Component
values
C R
50A
Some Practical Thoughts on Op Amp Design
1.) Decide upon a suitable topology.
Experience is a great help
The topology should be the one capable of meeting most of the specifications
Try to avoid inventing a new topology but start with an existing topology
2.) Determine the type of compensation needed to meet the specifications.
Consider the load and stability requirements
Use some form of Miller compensation or a self-compensated approach
3.) Design dc currents and device sizes for proper dc, ac, and transient performance.
This begins with hand calculations based upon approximate design equations.
Compensation components are also sized in this step of the procedure.
After each device is sized by hand, a circuit simulator is used to fine tune the
design
Two basic steps of design:
1.) First-cut - this step is to use hand calculations to propose a design that has
potential of satisfying the specifications. Design robustness is developed in this step.
2.) Optimization - this step uses the computer to refine and optimize the design.
A DESIGN PROCEDURE FOR THE TWO-STAGE CMOS OP AMP
Unbuffered, Two-Stage CMOS Op Amp
-
+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+
-
C
c
C
L
Fig. 6.3-1
Notation:
S
i
=
W
i
L
i
= W/L of the ith transistor
DC Balance Conditions for the Two-Stage Op Amp
For best performance, keep all transistors in
saturation.
M4 is the only transistor that cannot be forced
into saturation by internal connections or
external voltages.
Therefore, we develop conditions to force M4 to
be in saturation.
1.) First assume that V
SG4
= V
SG6
. This will
cause proper mirroring in the M3-M4 mirror.
Also, the gate and drain of M4 are at the same
potential so that M4 is guaranteed to be in
saturation.
2.) If V
SG4
= V
SG6
, then I
6
=
S
6
S
4
I
4
3.) However, I
7
=
S
7
S
5
I
5
=
S
7
S
5
(2I
4
)
4.) For balance, I
6
must equal I
7

S
6
S
4
=
2S
7
S
5
called the balance conditions
5.) So if the balance conditions are satisfied, then V
DG4
= 0 and M4 is saturated.
-
+
v
in
M1 M2
M3 M4
M5
M6
M7
v
o
V
DD
V
SS
V
Bias
+
-
C
c
C
L
-
+
V
SG6
-
+
V
SG4
I
4
I
5
I
7
I
6
Fig. 6.3-1A
Summary of the Design Relationships for the Two-Stage Op Amp
Slew rate SR =
I
5
C
c
(Assuming I
7
>>I
5
and C
L
> C
c
)
First-stage gain A
v1
=
g
m1
g
ds2
+g
ds4
=
2g
m1
I
5
(l
2
+l
4
)
Second-stage gain A
v2
=
g
m6
g
ds6
+g
ds7
=
g
m6
I
6
(l
6
+l
7
)
Gain-bandwidth GB =
g
m1
C
c
Output pole p
2
=
-g
m6
C
L
RHP zero z
1
=
g
m6
C
c
60 phase margin requires that g
m6
= 2.2g
m2
(C
L
/C
c
) if all other roots are 10GB.
Positive ICMR V
in(max)
= V
DD
-
I
5
b
3
- |V
T03
|
(max)
+ V
T1(min)
)
Negative ICMR V
in(min)
= V
SS
+
I
5
b
1
+ V
T1(max)
+ V
DS5
(sat)
Op Amp Specifications
The following design procedure assumes that specifications for the following parameters
are given.
1. Gain at dc, A
v
(0)
2. Gain-bandwidth, GB
3. Phase margin (or settling time)
4. Input common-mode range, ICMR
5. Load Capacitance, C
L
6. Slew-rate, SR
7. Output voltage swing
8. Power dissipation, P
diss
-
+
v
in
M1
M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+
-
C
c
C
L
V
SG4
+
-
Max. ICMR
and/or p
3
V
SG6
+
-
V
out
(max)
I
6
g
m6
or
Proper Mirroring
V
SG4
=V
SG6
C
c
0.2C
L
(PM = 60)
GB =
g
m1
C
c
Min. ICMR I
5 I
5
= SRC
c
V
out
(min)
Fig. 160-02
Unbuffered Op Amp Design Procedure
This design procedure assumes that the gain at dc (A
v
), unity gain bandwidth (GB), input
common mode range (V
in
(min) and V
in
(max)), load capacitance (C
L
), slew rate (SR),
settling time (T
s
), output voltage swing (V
out
(max) and V
out
(min)), and power dissipation
(P
diss
) are given. Choose the smallest device length which will keep the channel
modulation parameter constant and give good matching for current mirrors.
1. From the desired phase margin, choose the minimum value for C
c
, i.e. for a 60 phase
margin we use the following relationship. This assumes that z 10GB.
C
c
> 0.22C
L
2. Determine the minimum value for the tail current (I
5
) from
I
5
= SR
.
C
c
3. Design for S
3
from the maximum input voltage specification.
S
3
=
I
5
K'
3
[V
DD
V
in
(max)|V
T03
|(max)+V
T1
(min)]
2
4. Verify that the pole of M3 due to C
gs3
and C
gs4
(= 0.67W
3
L
3
C
ox
) will not be dominant
by assuming it to be greater than 10 GB
g
m3
2C
gs3
> 10GB.
Unbuffered Op Amp Design Procedure - Continued
5. Design for S
1
(S
2
) to achieve the desired GB.
g
m1
= GB
.
C
c
S
2
=
g
m1
2
K'
1
I
5
6. Design for S
5
from the minimum input voltage. First calculate V
DS5
(sat) then find S
5
.
V
DS5
(sat) = V
in
(min) - V
SS
-
I
5
1
-V
T1
(max) 100 mV S
5
=
2I
5
K'
5
[V
DS5
(sat)]
2
7. Find S
6
by letting the second pole (p
2
) be equal to 2.2 times GB and assuming that
V
SG4
= V
SG6
.
g
m6
= 2.2g
m2
(C
L
/C
c
) and
g
m6
g
m4
=
2K
P
'S
6
I
6
2K
P
'S
4
I
4
=
S
6
S
4
I
6
I
4
=
S
6
S
4
S
6
=
g
m6
g
m4
S
4
8. Calculate I
6
from
I
6
=
g
m6
2
2K'
6
S
6
Check to make sure that S
6
satisfies the V
out
(max) requirement and adjust as necessary.
9. Design S
7
to achieve the desired current ratios between I
5
and I
6
.
S
7
= (I
6
/I
5
)S
5
(Check the minimum output voltage requirements)
Unbuffered Op Amp Design Procedure - Continued
10. Check gain and power dissipation specifications.
A
v
=
2g
m2
g
m6
I
5
(l
2
+l
4
)I
6
(l
6
+l
7
)
P
diss
= (I
5
+ I
6
)(V
DD
+ |V
SS
|)
11. If the gain specification is not met, then the currents, I
5
and I
6
, can be decreased or
the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked
to insure that they are satisfied. If the power dissipation is too high, then one can only
reduce the currents I
5
and I
6
. Reduction of currents will probably necessitate increase of
some of the W/L ratios in order to satisfy input and output swings.
12. Simulate the circuit to check to see that all specifications are met.
DESIGN EXAMPLE OF A TWO-STAGE OP AMP
Example 230-1 - Design of a Two-Stage Op Amp
If K
N
=120A/V
2
, K
P
= 25A/V
2
, V
TN
= |V
TP
| = 0.5V,
N
= 0.06V
-1
, and
P
=
0.08V
-1
, design a two-stage, CMOS op amp that meets the following specifications.
Assume the channel length is to be 0.5m and the load capacitor is C
L
= 10pF.
A
v
> 3000V/V V
DD
=2.5V GB = 5MHz SR > 10V/s
60 phase margin 0.5V<V
out
range < 2V ICMR = 1.25V to 2V P
diss
2mW
Solution
1.) The first step is to calculate the minimum value of the compensation capacitor C
c
,
C
c
> (2.2/10)(10 pF) = 2.2 pF
2.) Choose C
c
as 3pF. Using the slew-rate specification and C
c
calculate I
5
.
I
5
= (3x10
-12
)(10x10
6
) = 30 A
3.) Next calculate (W/L)
3
using ICMR requirements (use worst case thresholds 0.15V).
(W/L)
3
=
30x10
-6
(25x10
-6
)[2.5-2-.65+0.35]
2
= 30 (W/L)
3
=(W/L)
4
=30
Example 230-1 - Continued
4.) Now we can check the value of the mirror pole, p
3
, to make sure that it is in fact
greater than 10GB. Assume the C
ox
= 6fF/m
2
. The mirror pole can be found as
p
3

-g
m3
2C
gs3
=
- 2K
p
S
3
I
3
2(0.667)W
3
L
3
C
ox
= -1.25x10
9
(rads/sec)
or 199 MHz. Thus, p
3
, is not of concern in this design because p
3
>> 10GB.
5.) The next step in the design is to calculate g
m1
to get
g
m1
= (5x10
6
)(2)(3x10
-12
) = 94.25S
Therefore, (W/L)
1
is
(W/L)
1
= (W/L)
2
=
g
m1
2
2K
N
I
1
=
(94.25)
2
212015
= 2.47 3.0 (W/L)
1
=(W/L)
2
=3
6.) Next calculate V
DS5
,
V
DS5
= 1.25 -
30x10
-6
120x10
-6
3
- .65 = 0.31V
Using V
DS5
calculate (W/L)
5
from the saturation relationship.
(W/L)
5
=
2(30x10
-6
)
(120x10
-6
)(0.31)
2
= 5.16 6 (W/L)
5
=6
7.) For 60 phase margin, we know that
g
m6
~ 10g
m1
~ 942.5S
Assuming that g
m6
= 942.5S and knowing that g
m4
= 150S, we calculate (W/L)
6
as
(W/L)
6
= 30
942.5x10
-6
(150x10
-6
)
= 188.5 - 190 (W/L)
6
=190
8.) Calculate I
6
using the small-signal g
m
expression:
I
6
=
(942.5x10
-6
)
2
(2)(25x10
-6
)(188.5)
= 94.2A - 95A
Calculating (W/L)
6
based on V
out
(max), gives a value of 15. Since 190 exceeds the
specification and gives better phase margin, we choose (W/L)
6
= 190 and I
6
= 95A.
With I
6
= 95A the power dissipation is P
diss
= 2.5V(30A+95A) = 0.3125mW
9.) Finally, calculate (W/L)
7
(W/L)
7
= 6
\
|
|
[
)
j
j
95x10
-6
30x10
-6
= 19 - 20 - (W/L)
7
=20
Let us check the V
out
(min) specification although the W/L of M7 is so large that this is
probably not necessary. The value of V
out
(min) is
V
out
(min) = V
DS7
(sat) = (295)/(12020) = 0.281V
which is less than required. At this point, the first-cut design is complete.
10.) Now check to see that the gain specification has been met
A
v
=
(94.25x10
-6
)(942.5x10
-6
)
15x10
-6
(.06+.08)95x10
-6
(.06+.08)
= 3,180V/V
which barely exceeds the specifications. Since we are at 2xL
min
, it wont do any good to
increase the channel lengths. Decreasing the currents or increasing W
6
/L
6
will help.
The figure below shows the results of the first-cut design. The W/L ratios shown do
not account for the lateral diffusion discussed above. The next phase requires simulation.
RIGHT-HALF PLANE ZERO
Controlling the Right-Half Plane Zero
Why is the RHP zero a problem?
Because it boosts the magnitude but lags the phase - the worst possible combination for
stability.
060626-03
j
j
1
j
2
j
3
3
180 >
1
>
2
>
3
z
1
Loop
Gain
0dB
log
10
log
10
360
180
RHP Zero Boost
RHP Zero Lag
Loop
Phase
Shift
Solution of the problem:
The compensation comes from the feedback path through C
c
, but the RHP zero
comes from the feedforward path through C
c
so eliminate the feedforward path!
Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor
Model:
The transfer
function is given
by the following
equation,
V
o
(s)
V
in
(s)
=
(g
mI
)(g
mII
)(R
I
)(R
II
)
1+s[R
I
C
I
+R
II
C
II
+R
I
C
c
+g
mII
R
I
R
II
C
c
]+s
2
[R
I
R
II
C
II
(C
I
+C
c
)]
Using the technique as before to approximate p
1
and p
2
results in the following
p
1

-1
R
I
C
I
+R
II
C
II
+R
I
C
c
+g
mII
R
I
R
II
C
c

-1
g
mII
R
I
R
II
C
c
and
p
2

-g
mII
C
c
C
II
(C
I
+C
c
)
Comments:
Poles are approximately what they were before with the zero removed.
For 45 phase margin, |p
2
| must be greater than GB
For 60 phase margin, |p
2
| must be greater than 1.73GB
Fig. 430-0
Inverting
High-Gain
Stage
C
c
v
OUT g
mI
v
in
R
I
g
mII
V
I
R
II
C
II
V
I
C
c
+
-
V
o
C
I
+
-
V
in
V
out
+1
Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero
Assume that the unity-gain buffer has an output resistance of R
o
.
Model:
Inverting
High-Gain
Stage
+1
C
c
v
OUT g
mI
v
in
R
I
g
mII
V
I
R
II
C
II
V
I
C
c
+
-
V
out
C
I
+
-
V
in R
o
R
o
V
out
Fig. 430-03
R
o
It can be shown that if the output resistance of the buffer amplifier, R
o
, is not neglected
that another pole occurs at,
p
4

-1
R
o
[C
I
C
c
/(C
I
+C
c
)]
and a LHP zero at
z
2

-1
R
o
C
c
Closer examination shows that if a resistor, called a nulling resistor, is placed in series
with C
c
that the RHP zero can be eliminated or moved to the LHP.
Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)
Inverting
High-Gain
Stage
C
c
v
OUT
R
z
g
mI
v
in
R
I
g
mII
V
I
R
II
C
II
C
c
+
-
V
out C
I
+
-
V
in
R
z
Fig. 430-04
V
I
Nodal equations:
g
mI
V
in
+
V
I
R
I
+ sC
I
V
I
+
sC
c
1+sC
c
R
z
(V
I
- V
out
) = 0
g
mII
V
I
+
V
o
R
II
+ sC
II
V
out
+
sC
c
1+sC
c
R
z
(V
out
- V
I
) = 0
Solution:
V
out
(s)
V
in
(s)
=
a{1-s[(C
c
/g
mII
)-R
z
C
c
]}
1+bs+cs
2
+ds
3
where

W,J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of CA., Santa Barbara.
a = g
mI
g
mII
R
I
R
II
b = (C
II
+ C
c
)R
II
+ (C
I
+ C
c
)R
I
+ g
mII
R
I
R
II
C
c
+ R
z
C
c
c = [R
I
R
II
(C
I
C
II
+ C
c
C
I
+ C
c
C
II
) + R
z
C
c
(R
I
C
I
+ R
II
C
II
)]
d = R
I
R
II
R
z
C
I
C
II
C
c
Use of Nulling Resistor to Eliminate the RHP - Continued
If R
z
is assumed to be less than R
I
or R
II
and the poles widely spaced, then the roots of
the above transfer function can be approximated as
p
1

-1
(1+g
mII
R
II
)R
I
C
c

-1
g
mII
R
II
R
I
C
c
p
2

-g
mII
C
c
C
I
C
II
+C
c
C
I
+C
c
C
II

-g
mII
C
II
p
4
=
-1
R
z
C
I
and
z
1
=
1
C
c
(1/g
mII
-R
z
)
Note that the zero can be placed anywhere on the real axis.
A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p
2
We desire that z
1
= p
2
in terms of the previous notation.
Therefore,
1
C
c
(1/g
mII
-R
z
)
=
-g
mII
C
II
The value of R
z
can be found as
R
z
=
C
c
+C
II
C
c
(1/g
mII
)
With p
2
canceled, the remaining roots are p
1
and p
4
(the pole due to R
z
) . For unity-gain
stability, all that is required is that
|p
4
| > A
v
(0)|p
1
| =
A
v
(0)
g
mII
R
II
R
I
C
c
=
g
mI
C
c

and (1/R
z
C
I
) > (g
mI
/C
c
) = GB
Substituting R
z
into the above inequality and assuming C
II
>> C
c
results in
C
c
>
g
mI
g
mII
C
I
C
II
This procedure gives excellent stability for a fixed value of C
II
( C
L
).
Unfortunately, as C
L
changes, p
2
changes and the zero must be readjusted to cancel p
2
.
j
Fig. 430-06
-p
4
-p
2
-p
1
z
1
Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op Amp
Circuit:
We saw earlier that the roots were:
p
1
= -
g
m2
A
v
C
c
= -
g
m1
A
v
C
c
p
2
= -
g
m6
C
L
p
4
= -
1
R
z
C
I
z
1
=
-1
R
z
C
c
-C
c
/g
m6
where A
v
= g
m1
g
m6
R
I
R
II
.
(Note that p
4
is the pole resulting from the nulling resistor compensation technique.)
V
DD
V
SS
I
Bias
C
L
C
c
C
M
v
out
V
B
V
A
M1 M2
M3 M4
M5
M6
M7
M9
M10
M11
M12
v
in
+
v
in
-
M8
Fig. 160-03
V
C
Design of the Nulling Resistor (M8)
For the zero to be on top of the second pole (p
2
), the following relationship must hold
R
z
=
1
g
m6

\
|
|
[
)
j
j
C
L
+C
c
C
c
=
\
|
|
[
)
j
j
C
c
+C
L
C
c

1
2K
P
S
6
I
6

The resistor, R
z
, is realized by the transistor M8 which is operating in the active region
because the dc current through it is zero. Therefore, R
z
, can be written as
R
z
=
ov
DS8
oi
D8

|
V
DS8
=0
=
1
K
P
S
8
(V
SG8
-|V
TP
|)
The bias circuit is designed so that voltage V
A
is equal to V
B
.
. |V
GS10
| ~ |V
T
| = |V
GS8
| ~ |V
T
|= V
SG11
= V
SG6
=
\
|
|
[
)
j
j
W
11
L
11
=
\
|
|
[
)
j
j
I
10
I
6

\
|
|
[
)
j
j
W
6
L
6
In the saturation region
|V
GS10
| ~ |V
T
| =
2(I
10
)
K'
P
(W
10
/L
10
)
= |V
GS8
| ~ |V
T
|
. R
z
=
1
K
P
S
8

K
P
S
10
2I
10
=
1
S
8

S
10
2K
P
I
10
Equating the two expressions for R
z
gives
\
|
|
[
)
j
j
W
8
L
8
=
\
|
|
[
)
j
j
C
c
C
L
+C
c

S
10
S
6
I
6
I
10
Example 230-2 - RHP Zero Compensation
Use results of Ex. 230-1 and design compensation circuitry so that the RHP zero is
moved from the RHP to the LHP and placed on top of the output pole p
2
. Use device
data given in Ex. 230-1.
Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias current
I
10
. The first step in this design is to establish the bias components. In order to set V
A
equal to V
B
, then V
SG11
must equal V
SG6
. Therefore,
S
11
= (I
11
/I
6
)S
6
Choose I
11
= I
10
= I
9
= 15A which gives S
11
= (15A/95A)190 = 30.
The aspect ratio of M10 is essentially a free
parameter, and will be set equal to 1. There must be
sufficient supply voltage to support the sum of V
SG11
,
V
SG10
, and V
DS9
. The ratio of I
10
/I
5
determines the
(W/L) of M9. This ratio is
(W/L)
9
= (I
10
/I
5
)(W/L)
5
= (15/30)(6) = 3
Now (W/L)
8
is determined to be
(W/L)
8
=
3pF
3pF+10pF

119095A
15A
= 8
It is worthwhile to check that the RHP zero has been moved on top of p
2
. To do this, first
calculate the value of R
z
. V
SG8
must first be determined. It is equal to V
SG10
, which is
V
SG10
=
2I
10
K
P
S
10
+ |V
TP
| =
215
251
+ 0.5 = 1.595V
Next determine R
z
.
R
z
=
1
K
P
S
8
(V
SG10
-|V
TP
|)
=
10
6
258(1.595-.7)
= 4.564k
The location of z
1
is calculated as
z
1
=
-1
(4.564x10
3
)(3x10
-12
)-
3x10
-12
950x10
-6
= -94.91x10
6
rads/sec
The output pole, p
2
, is
p
2
= -
950x10
-6
10x10
-12
= -95x10
6
rads/sec
Thus, we see that for all practical purposes, the output pole is canceled by the zero
that has been moved from the RHP to the LHP.
The results of this design are summarized below where L = 0.5m.
W
8
= 4m W
9
/L
9
= 1.5m W
10
= 0.5m and W
11
= 15 m
An Alternate Form of Nulling Resistor
To cancel p
2
,
z
1
= p
2
R
z
=
C
c
+C
L
g
m6A
C
C
=
1
g
m6B

Which gives
g
m6B
= g
m6A
C
c
C
c
+C
L

In the previous example,
g
m6A
= 950S, C
c
= 3pF
and C
L
= 10pF.
Choose I
6B
= 10A to get
g
m6B
=
g
m6A
C
c
C
c
+C
L

2K
P
W
6B
I
6B
L
6B
=
C
c
C
c
+C
L

2K
P
W
6A
I
D6
L
6A

or
W
6B
L
6B
=
3
13
2

I
6A
I
6B

W
6A
L
6A
=
3
13
2

95
10
(190) = 96.12 W
6B
= 48m
-
+
v
in
M1 M2
M3 M4
M5
M6
M7
v
ou
V
DD
V
SS
V
Bias
+
-
C
c
C
L
M11 M10
M6B
M8 M9
Fig. 6.3-4A
Increasing the Magnitude of the Output Pole
The magnitude of the output pole , p

2
, can be increased by introducing gain in the Miller
capacitor feedback path. For example,
V
DD
V
SS
V
Bias
C
c
M6
M7
M8
M9 M10
M12 M11
v
OUT
I
in
R
1
R
2
C
2
r
ds8
gm8Vs8
C
c
V
out V
1
+
-
+
-
+
-
Vs8
I
in
R
1
R
2
C
2
g
m8
V
s8
V
out V
1
+
-
+
-
+
-
V
s8
1
gm8
C
c
g
m6
V
1
g
m6
V
1
C
gd6
C
gd6
Fig. 6.2-15B
The resistors R
1
and R
2
are defined as
R
1
=
1
g
ds2
+g
ds4
+g
ds9
and R
2
=
1
g
ds6
+g
ds7

where transistors M2 and M4 are the output transistors of the first stage.
Nodal equations:
I
in
= G
1
V
1
-g
m8
V
s8
= G
1
V
1
-
\
|
|
[
)
j
j
g
m8
sC
c
g
m8
+sC
c
V
out
and 0 = g
m6
V
1
+
|
|
|
|
|
|
|
|
G
2
+sC
2
+
g
m8
sC
c
g
m8
+sC
c
V
out

B.K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
Increasing the Magnitude of the Output Pole - Continued
Solving for the transfer function V
out
/I
in
gives,
V
out
I
in
=
\
|
|
[
)
j
j
-g
m6
G
1
G
2

|
|
|
|
|
|
|
|
|
|
\
|
|
[
)
j
j
1+
sC
c
g
m8
1+s
|
|
|
|
|
|
|
|
C
c
g
m8
+
C
2
G
2
+
C
c
G
2
+
g
m6
C
c
G
1
G
2
+s
2
\
|
|
[
)
j
j
C
c
C
2
g
m8
G
2

Using the approximate method of solving for the roots of the denominator gives
p
1
=
-1
C
c
g
m8
+
C
c
G
2
+
C
2
G
2
+
g
m6
C
c
G
1
G
2
-
-6
g
m6
r
ds
2
C
c

and p
2
-
-
g
m6
r
ds
2
C
c
6
C
c
C
2
g
m8
G
2
=
g
m8
r
ds
2
G
2
6

\
|
|
[
)
j
j
g
m6
C
2
=
\
|
|
[
)
j
j
g
m8
r
ds
3
|p
2
|
where all the various channel resistance have been assumed to equal r
ds
and p
2
is the
output pole for normal Miller compensation.
Result:
Dominant pole is approximately the same and the output pole is increased by - g
m
r
ds
.
Increasing the Magnitude of the Output Pole - Continued
In addition there is a LHP zero at -g
m8
/sC
c
and a RHP zero due to C
gd6
(shown dashed
in the previous model) at g
m6
/Cgd6.
Roots are:
j
g
m6
C
gd6
-g
m8
C
c
-g
m6
g
m8
r
ds
3C
2
-1
g
m6
r
ds
C
c
Fig. 6.2-16A
Concept:
R
out
= r
ds7
||
3
g
m6
g
m8
r
ds8

3
g
m6
g
m8
r
ds8

Therefore, the output pole is
approximately,
|p
2
|
g
m6
g
m8
r
ds8
3C
II

V
DD
C
c
r
ds7
v
out
M6
C
II
GBC
c
1
0
V
DD
v
out
M6
C
II
M8
g
m8
r
ds8
Fig. Fig. 430-08
r
ds7
3
POWER SUPPLY REJECTION RATIO OF THE TWO-STAGE OP AMP
What is PSRR?
PSRR =
A
v
(V
dd
=0)
A
dd
(V
in
=0)

How do you calculate PSRR?
You could calculate A
v
and A
dd
and divide,
however
+
-
V
DD
V
SS
V
dd
V
out
V
2
V
1
V
2
V
1
A
v
(V
1
-V
2
)
A
dd
V
dd
V
ss
V
out
Fig. 180-02
V
out
= A
dd
V
dd
+ A
v
(V
1
-V
2
) = A
dd
V
dd
- A
v
V
out
V
out
(1+A
v
) = A
dd
V
dd
V
out
V
dd
=
A
dd
1+A
v

A
dd
A
v
=
1
PSRR
+
(Good for frequencies up to GB)
+
-
V
DD
V
SS
V
dd
V
2
V
1
V
ss
V
out
V
in
Fig.180-01
Approximate Model for PSRR
+
M1 M2
M3 M4
M5
M6
M7
V
out
V
DD
V
SS
V
Bias
C
c
C
II
V
dd
C
I
Fig. 180-05
C
c
V
dd R
out
V
out
Other sources
of PSRR
+

besides C
c
1
R
out
C
c
V
out
V
dd
0dB
1.) The M7 current sink causes V
SG6
to act like a battery.
2.) Therefore, V
dd
couples from the source to gate of M6.
3.) The path to the output is through any capacitance from gate to drain of M6.
Conclusion:
The Miller capacitor C
c
couples the positive power supply ripple directly to the output.
Must reduce or eliminate C
c
.
Approximate Model for PSRR
-
What is Z
out
?
Z
out
=
V
t
I
t
I
t
= g
mII
V
1
= g
mII
g
mI
V
t
G
I
+sC
I
+sC
c

Thus, Z
out
=
G
I
+s(C
I
+C
c
)
g
mI
g
MII

V
out
V
ss
=
1+
r
ds7
Z
out
1
=
s(C
c
+C
I
)+G
I
+g
mI
g
mII
r
ds7
s(C
c
+C
I
)+G
I
Pole at
-G
I
C
c
+C
I

The negative PSRR is much better than the positive PSRR.
M1 M2
M3 M4
M5
M6
M7
V
out
V
DD
V
SS
V
Bias
C
c
C
II
V
ss
C
I
Fig. 180-11
V
Bias
connected to V
SS
r
ds7
v
out
Z
out
V
ss
r
ds7
Path through C
gd7
is negligible
Fig.180-12
V
t
r
ds6
||r
ds7
V
out
C
I
C
c
+
-
V
1
+
-
g
mI
V
out
g
mII
V
1
R
I
C
II
+C
gd7
I
t
SUMMARY
The output of the design of an op amp is
- Schematic
- DC currents
- W/L ratios
- Component values
Design procedures provide an organized approach to creating the dc currents, W/L
ratios, and the component values
The right-half plane zero causes the Miller compensation to deteriorate
Methods for eliminating the influence of the RHP zero are:
- Nulling resistor
- Increasing the magnitude of the output pole
The PSRR of the two-stage op amp is poor because of the Miller capacitance, however,
methods exist to eliminate this problem
The two-stage op amp is a very general and flexible op amp

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Lecture 230 Design of Two-Stage Op Amps (3/27/10) Page 230-1

CMOS Analog Circuit Design P.E. Allen - 2010

The magnitude of the output pole , p

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