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  • Power Aware Testing by Proper Don't Care Filling

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    The document discusses power aware testing of VLSI chips. It notes that VLSI chips contain many transistors and feature sizes smaller than 100nm increase the likelihood of defects. During testing, switching activity and parallel testing can lead to excessive power dissipation compared to normal operation. The document also states that testing is one of the most expensive parts of the design cycle and that power must now be considered as a critical parameter for developing low power system tests.

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    Power Aware Testing by Proper Don’t Care Filling

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    The document discusses power aware testing of VLSI chips. It notes that VLSI chips contain many transistors and feature sizes smaller than 100nm increase the likelihood of defects. During testing, switching activity and parallel testing can lead to excessive power dissipation compared to normal operation. The document also states that testing is one of the most expensive parts of the design cycle and that power must now be considered as a critical parameter for developing low power system tests.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
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    22 views5 pages

    Power Aware Testing by Proper Don't Care Filling

    Uploaded by

    sambhunit
    The document discusses power aware testing of VLSI chips. It notes that VLSI chips contain many transistors and feature sizes smaller than 100nm increase the likelihood of defects. During testing, switching activity and parallel testing can lead to excessive power dissipation compared to normal operation. The document also states that testing is one of the most expensive parts of the design cycle and that power must now be considered as a critical parameter for developing low power system tests.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 5

    Power Aware Testing by Proper Dont Care Filling of Test Patterns

    DEPT. OF ECE

    NIT AGARTALA

    INTRODUCTION
    VLSI devices with many millions of transistors are commonly used in todays computers and electronic appliances. The reduction in feature size increases the probability that a manufacturing defect in the IC will result in a faulty chip. A very small defect can easily result in a faulty transistor or interconnecting wire when the feature size is less than 100 nm.

    TESTING DURING VLSI LIFE CYCLE

    WHY TEST POWER IS HIGHER?


    In test mode, switching activity of all nodes is often several times higher than during normal operation. Often parallel testing is used in SoCs to reduce test application time, which might result in excessive energy and power dissipation. DFT circuitry designed to reduce test complexity is often idle during normal operation, but might be intensively used in test mode.

    TEST CHALLENGES
    Escalating transistor counts, increasing chips complexity, while maintaining its size. Testing is one of the most expensive and problematic aspects in a circuit design cycle.

    Traditionally test engineers evaluated test techniques according to area, fault coverage, test application time etc.
    The new class of low power systems make power management a critical parameter that cannot be ignored in test development.

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