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Wafer Sort

Wafer sort is a 100% testing of each die on a wafer at the end of wafer fabrication to verify chip functionality, sort good chips, provide fab yield information, and achieve high test coverage. The wafer sort procedure uses automated test equipment to test every die on the wafer through electrical probe needles contacting bond pads. Common wafer sort tests include DC tests to check continuity and shorts/opens, output checks, and functional tests to verify intended chip performance. Wafer sort yield measures the percentage of acceptable dies passing the tests and low yield can mean more chips rejected at assembly.

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589 views12 pages

Wafer Sort

Wafer sort is a 100% testing of each die on a wafer at the end of wafer fabrication to verify chip functionality, sort good chips, provide fab yield information, and achieve high test coverage. The wafer sort procedure uses automated test equipment to test every die on the wafer through electrical probe needles contacting bond pads. Common wafer sort tests include DC tests to check continuity and shorts/opens, output checks, and functional tests to verify intended chip performance. Wafer sort yield measures the percentage of acceptable dies passing the tests and low yield can mean more chips rejected at assembly.

Uploaded by

iloveCG
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd

Wafer Sort

Wafer Sort
At the end of wafer fab, wafers undergo 100% wafer sort testing of each die. Also known as electrical sort, wafer probe, or probe.

Wafer sort makes an important contribution to wafer fab.

Objectives of wafer sort:


1. Chip functionality verify the operation of all chip functions 2. Chip sorting sort good chips based on their operating speed performance 3. Fab yield response provide important fab yield information 4. Test coverage achieve high test coverage of the internal device nodes at the lowest cost.

Performing Wafer Sort


Procedure is similar to in-line parametric test Every die on the wafer is tested Automated test equipment (ATE) is used Located in an adjacent facility to the fab with less stringent cleanroom class A correlation wafer is used to verify tester setup

Wafers are indexed from the cassette to the prober Mounting on a vacuum chuck with Zpositioning Mechanical probe needles contact the bond pads to create electrical continuity Type of tests, number of tests, and their order are defined by the test program in computer

Wafer Sort Tests


These are sometimes referred to as AC tests because a system clock and high-frequency input signal are used to verify the chip performance.

Three tests typically done during wafer sort


DC tests (continuity, shorts/opens, and leakage) Output checks Functional tests

DC tests (continuity, shorts/opens, and leakage)


Continuity test to verify that the probe needles are making good electrical contact with the bonding pads.
Short/opens test conducted by applying a forward bias voltage and measuring the voltage drop

Output checks - to verify acceptable chip performance, wafer sort tests the output signals Functional tests - verify that the chip performs as intended by the product data specification

Yield
Wafer sort yield the percentage of acceptable die that pass the wafer sort test. - low yield means that a large number of chips will be rejected at assembly and packaging.

Fabrication and design factors that affect wafer sort yield:


Larger wafer diameter Increased die size Increase in number of process steps Shrinking feature sizes Process maturity Crystal defects

Common test troubleshooting problems:


1. Probe card problem at in-line parametric test 2. Damage test pads or bonding pads 3. Tester not functioning properly during test

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