Siddhi Vinayak College of Sc. $ hr.

Education(Alwar)

A
presentation on
45 Nanometer Technology

Presented by:

Bhawna kalra

Guided by:Vikas

Tiwar

H.O.D(E.C.E. Dept.)

Presentation flow
Need

Introduction
45 nm technology
Features
Products
Advantages
Future applications
Conclusion
Reference

Need of nm Technology
As VLSI technology has progressed to pack smaller, faster and
increasing number of transistors on a single chip .
Copper/Low-k interconnect technologies for sub-100 nm CMOS ICs
are impacting system performance through increased power
dissipation, signal delay, and cross-talk. .
With clock frequencies increasing into the GHz regime, the parasitic
resistance, capacitance and inductance associated with these wires
often lead to performance bottlenecks which have led the
semiconductor and the electronic design automation industries to
adopt several technological innovations.
Furthermore, prevalent high chip temperatures (aggravated by large
power dissipation of nanometer scale ICs) and increasing current
densities in wires make electromigration in copper a constant threat
to VLSI circuits.
To overcome all these problems nm technology is used.

Nanometer Technology
Nanometer is the art and science of
manipulating matter at the nano scale
(down to 1/1,00,000 the width of the
human hair ) to creat new and unique
materials and products.with
enormous potential to change societry..

Nanometer why?

Tiny Size
Incredible surface area per unit mass
Light weight.
Strong.

Intel SRAM Test Chips

130 nm
process
2.45 m cell
18 Mbits
103 mm
March 00

90 nm
Process
1 m cell
50Mbits
109 mm
February 02

65 nm
process

45 nm
process

0.57 m cell
70 Mbits
110 mm
April 04

0.346m
153 Mbits
119 mm
January 06

New SRAM Test Vehicles developed every 2 years to held

development of logic technologies

45 nm Technology
Intel is first to reach an important
milestone in the development of 45 nm
logic technology.
Fully functional 153 Mbit SRAM chips have
been made with > 1 billion transistor each.
The memory cell size on this SRAM is
0.346 m,almost half the size of 65 nm
cell.

45nm High-k + Metal Gate Transistors

65 nm Transistor
TEM

45 nm HK + MG
TEM

Hafnium-based high-k + metal gate transistors are the biggest

advancement in transistor technology

Benefits Compared to 65
nm
>25x lower gate oxide leakage
>30% lower switching power
~30% higher drive current
>5x lower source-drain leakage
HiK gate insulator introduced at 45nm CMOS node to reduce gate leakage

Metal Gate introduced at 45nm CMOS node to

eliminate poly depletion

Logic Processing trends

Logic Processing trends

Performance and functionality continue to

improve with increased transistor count.

The Road to HK+MG Processors

Transistor Density $ Performance

Graphs represents transistor performance $ Density

Transistor
Performance
Intel 45nm transistors
provide the higher drive
currents from 65nm

Transistor Density
Intel 45 nm transistors
provide the tightest gate
pitch from 65nm
technology

SRAM Cell Size Scaling

6 transistor SRAM area of 0.346 m
193 nm dry lithography used to patter critical layers

65 nm, 0.570 um2

45 nm, 0.346 um2

32 nm, 0.171 um2

Transistor density continues to double every 2 years

45 nm microprocessor Products
Single
core

Dua
l
Cor
e

Quad
core

a
6 core

>200 million 45 nm CPU shipped

to date

8
core

Changes in Scaling
THEN
Scaling drove
performance
Performance
constrained
Active power
dominates
Independent designprocess

130 nm

90 nm

NOW
Materials drive
performance
Power constrained
Standby power
dominates
Collaborative design
process

65 nm

45 nm

Advantages
Benefits Compared to 65 nm
>25x lower gate oxide leakage
>30% lower switching power
~30% higher drive current
>5x lower source-drain leakage

Overall advantages
Tiny Size
Incredible surface area per unit mass
Light weight.
Strong

Applications of 45 nm
Energy applications
Industrial applications
Drugs $ Cancer detection and
treatment.
Potential applications of carbon
nanotubes
Electronics
Environmental Applications $ green

CONCLUSION
45 nm logic technology is being
demonstrated on fully functional 153 Mbits
SRAM chips with > 1 billion transistors.
These SRAM test chips exercise all of the
transistor $ interconnect features to be used on
45 nm microprocessors.
This 45 nm technology provides significant
density ,performance $ power improvements
over todays 65 nm technology.

Reference
S. R. Nassif, Within-chip variability analysis, in IEDM Tech. Dig., 1998,
pp. 283286.
E. J. Dudewicz and S. N. Mishra, Modern Mathematical Statistics.
Hoboken, NJ: Wiley, 1988.
BSIM4.60 Users Manual. [Online]. Available: http://www-device.eecs.
berkeley.edu/bsim3/~bism4.html.
H. P. Tuinhout, Impact of parametric mismatch and fluctuations on performance and
yield of deep-submicron CMOS technologies, in Proc.
ESSDERC, Firenze, Italy, 2002, pp. 95101.
H. R. Huff et al., IEEE IWGI Tech. Digest, 2001, p. 2.
C. Hobbs et al., IEEE VLSI Tech. Digest, 2003, p. 9.
J. Yuan, et al, A 45nm low cost low power platform by using
integrated dual-stress-liner technology, VLSI technology
symposium, 2006, pp. 100-101.
U. Gogineni, et al, Effect of substrate contact shape and
placement on RF characteristics of 45 nm low-power CMOS
devices, Radio Frequency Integrated Circuits Symposium,
2009, pp. 163-166.

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