Topics

Coarse-grained FPGAs. Reconfigurable systems. Reconfigurable ASICs.

FPGA-Based System Design: Chapter 7

Copyright 2004 Prentice Hall PTR

FPGA granularity

Typical LEs implement a small amount of logic.

Waste a lot of space/power on connecting logic elements. Specialized adder logic tries to solve this problem for a special case.

Can build FPGAs with larger elements.

FPGA-Based System Design: Chapter 7

Copyright 2004 Prentice Hall PTR

Granularity issues
How big is the logic element? How flexible should it be? What interconnection network is needed? How do you program it?

FPGA-Based System Design: Chapter 7

Copyright 2004 Prentice Hall PTR

Reconfigurable systems

Reconfigure logic on-the-fly:

application characteristics may change over time.

Issues:
Reconfiguration time. Reconfiguration memory cost. Power consumption. Synthesis for reconfiguration.
Copyright 2004 Prentice Hall PTR

FPGA-Based System Design: Chapter 7

PipeRench

Reconfigurable pipeline:
Each stage of the pipeline can be reconfigured quickly and independently.

Allows virtual pipeline that is longer than physical pipeline.

FPGA-Based System Design: Chapter 7

Copyright 2004 Prentice Hall PTR

PipeRench pipeline operation

FPGA-Based System Design: Chapter 7

Copyright 2004 Prentice Hall PTR

RaPiD architecture

Coarse-grained computational architecture:

Soft control can be reconfigured on every cycle. Hard control can be reconfigured only in configuration mode.

Interconnect network allows computational elements to be arranged in pipelines.

FPGA-Based System Design: Chapter 7

Copyright 2004 Prentice Hall PTR

RaPiD pipeline

FPGA-Based System Design: Chapter 7

Copyright 2004 Prentice Hall PTR

Reconfigurable ASICs

Problems with ASICs:

Mask cost. Manufacturing time.

Solution---mix ASIC and FPGA:

Reconfigurable logic on bottom. Custom wiring on top.

FPGA-Based System Design: Chapter 7

Copyright 2004 Prentice Hall PTR