EFFICIENT FPGA IMPLEMENTATION OF PWM CORE

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INTRODUCTION
Two undeniable trends pervade today's semiconductor design industry: -shrinking process geometries -the increasing adoption of system-on-a-chip (IP) blocks As semiconductors increase in density, growing trend toward moving complete systems from the board level to the chip level.
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 Shrinking design cycle times are putting pressure on system designers to use existing chips and differentiate their products at the system level. Virtually impossible for a single design team to create completely new intellectual property (IP) with each chip. Greater focus on design reuse, where IP from earlier designs is utilized and reused in later designs.

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 IP, EDA and Library vendors design various sophisticated IP cores to fulfill applicationspecific needs. Each IP core needs silicon technology support to ensure that the IP core is reusable and verified. The integrated-circuit industry is entering a system-on-chip era in which IP cores will be the key to enhancing design productivity and meeting the product road map.

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 The following sections describe the implementation of a Pulse Width Modulation (PWM) core on a Xilinx 4003E FPGA using CAD tool WorkView Office from Synopsis. The core is designed to operate at a clock frequency of 4Mhz. The PWM core developed can be used in many diverse and complex applications like robotics, motor and motion control, microprocessorcontrolled data acquisition system etc.

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FUNCTIONAL DESCRIPTION
A PWM circuit works by making a pulsating DC square wave with a variable on-to-off ratio. The average on time may be varied from 0 to 100 percent. The widths of the pulses are proportional to the input signal. When the signal is small, a series of narrow pulses is generated. When the signal is large, a series of wide pulses is generated.
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 In many of the applications, the single bit digital output is subject to a low-pass filter that results in an analog output level.

The output level is the analog equivalent of the digital PWMs duty-cycle.

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Functional Block Diagram

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 Basic principle: a register to store the value which is loaded on to the Up/Down Counter whenever the counter reaches its terminal count. The terminal counter is used to generate the pulse width modulation.

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 A data register: to store the value for the counter. Value determines the pulse width. The Up/Down Counter: loaded with a new value from the data register when the counter reaches its terminal count. Toggle Flip-flop generates the PWM output

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 When data value is first loaded, counter counts down from data value to 0. Terminal count and PWM signals are Low. When counter goes through 0 transition, terminal count is generated. Triggers Toggle Flip-flop to drive PWM signal High. Data value is re-loaded and counting proceeds up to maximum value. Terminal count generated again when counter reaches its maximum value. Drives PWM signal to toggle from High to Low. Data value is re-loaded and cycle repeats.
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 Direction of counter controlled by PWM signal: counter is set to count down when PWM is Low, and count up when PWM is High. Terminal count controls data value loaded to counter from data register. Data is loaded when terminal count is High. Duty cycle of the PWM signal is controlled by data value loaded to the up/down counter. Higher the data value, higher the duty cycle.

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Sample PWM Output Waveform

Mark Period Data Value*Tclock

Frame Period 2n*Tclock

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 Duty Cycle = Mark Period/Frame Period = Data Value/2n Mark Period = Data value*Tclock Frame Period=Tclock*2n For a 16-bit PWM core, n=16 and an on-board 4Mhz clock gives the value of the Tclock=250nsec. Mark Period = ( Data Value *250nsec ) Frame Period = 250nsec*216 Duty cycle = (Data value/216 )

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Data Values for different Duty Cycles

Data value
1110011000000000 1100000000000000 1000000000000000 0100000000000000 0001100100000000
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Duty Cycles(%)
90 75 50 25 10
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IMPLEMENTATION OF THE PWM CORE

The functional description of the PWM core was synthesized using VHDL model and simulated using Fusion, the WorkView Office simulator The simulation results are displayed in the form of waveforms using Vwaves display tool.
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Simulation Waveforms for 50% DutyCycle

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 The VHDL model was implemented on XC4003E and optimized for area. The data value is loaded by the user using switches connected to the input pins of the XC4003E. The optimized implementation was found to consume 33 flip-flops on the CLBs, i.e., 16% of the total available flip-flops. Implementation results also indicate a maximum working frequency of 17.517 Mhz. The PWM output is taken out on one of the output pins of the XC4003E and can be observed on an oscilloscope.
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CONCLUSION
A resource efficient implementation of a PWM core on FPGAs has been studied. The choice of the device depends upon the complexity of the system to be designed. Finding cores with the appropriate functionality, quality level and support can be quite challenging. So, the core can also be made available as part of an SOC platform and used in those applications where PWM is essential. The designed PWM core can be used in many applications like motor and motion control, microprocessor-controlled data acquisition system so that a complete SOC can be designed
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