VHDL - Slides

Bi 1
Vn M t phn cng (Hardware Modeling)
Hardware Modeling - 1 - 2
VHDL l g?
Mt t vit tt cho mt t vit tt khc, VHDL l t vit tt ca VHSIC Hardware Description Language
Cn VHSIC l t vit tt ca Very High Speed Integrated Circuit
Tip theo, chng ta bt u tm hiu v xut x v mc ch ca ngn ng ny
VHDL - Mc ch v s hnh thnh
VHDL, trc ht v ch yu l mt cng c m hnh ho phn cng (hardware modeling)
m phng (simulation) v tng hp (synthesis) mch
Chun IEEE 1076 rt hon chnh cho vic m hnh ho thit b, nhng n mi ch nh ngha cc tham s khi qut cho vic tng hp thit b
Kt qu: mt m hnh phn cng cho khng hn ph hp vi mt thit k mc cng logic c thng qua cc cng c v cc cng ngh ch (target) khc nhau
Chun ho VHDL
T chc IEEE chnh thc ph chun chp nhn ngn ng VHDL nh l mt chun ca h vo nm 1987, chun IEEE 1076
Ging nh cc chun kc ca IEEE, chun IEEE 1076 c sa i theo chu k ti thiu l 5 nm
Sa i u tin c thc hin nm 1993, v VHDL-93 hin nay c coi l phin bn chnh thc ca ngn ng ny, hin nay bt u xut hin VHDL 200X
Tuy nhin, hu ht cc cng c (tool) u h tr phin bn u tin (VHDL-87) Cc b phn ca VHDL 200X c h tr bi mt s tool
VHDL-2X VHDL-93
VHDL-87
Language Subsets
IEEE 1076 (synthesis)
IEEE 1076 (modeling)
Khng phi tt c cc cu trc VHDL u c th tng hp c. V d, wait for 10 ns l mt cu trc m hnh ho thng dng, nhng n khng tng ng vi v cng khng th to ra mt phn t mc cng logic
Cc mc tru tng trong m t phn cng

t chi tit hn, thit k v m phng nhanh hn
Behavioral
RTL
AND_OR2
DFF
Chi tit hn, ph thuc cng ngh, thit k v m phng chm hn
Logic
Layout
CLB_ R5C5
CLB_ R5C6
S chng cho trong VHDL

Sum <= A + B after 3 ns ;
Behavioral
Hardware Model
Sum <= A + B ;
RTL
Synthesizable Code
component Xlx_add2 port ( A: in bit ; B: in bit ; Sum: out bit ); end component ;
Logic
FPGA Vendor Library
Layout
Place & Route Utility
Trnh t thit k Top-Down
VHDL h tr hng tip cn top-down trong thit k
Nguyn tc phn on
Khi tin hnh phn on mt thit k trong VHDL, cn lu tm cn nhc mt s cc im chnh sau
Tn hiu ra c cht (Register) ti bin gii cc module
Ph hp vi cu trc m ngun dng RTL Quan trng i vi cc rng buc v thi gian, Important for timing constraints, ti u ho cu trc mch Hu ht cc cng c u khng ti u thng qua bin gii hierarchy
Gim n ti thiu s clock trn mi block
Duy tr cc tn hiu then cht trong phm vi mi block
Kch thc ca tng block nh c th kim tra nhanh chng
Mu th nhanh, n gin cho mi sub-module
Cu trc Top - Down

A[3:0]
entity Add_4
SUM [3:0]
B[3:0]
C_in C_out
A B C_in
entity Full_Add
Sum
C_out
Macro
A B
entity Half_Add
Sum Carry
Leaf Cell
Kim tra thit k
Khi s dng VHDL, c th thc hin cc bc kim tra thit k, bt u t Behavioral Simulation
Behavioral Simulation (Testbench driven)
VHDL modules
VITAL
Synthesis
Gate-Level Functional (Netlist-driven )
VHDL Initiative Toward ASIC Libraries
Place & Route
Gate-Level Timing (Back-annotated netlist )
SDF (Standard Delay Format) & Structural VHDL File
Cc bc kim tra thit k

(1) M phng Behavioral
Thc hin m ngun m t hnh vi, dng testbench
(2) M phng RTL

Thc hin file m ngun RTL, dng testbench
(3) M phng chc nng trong VHDL

Thc hin file .vhd m t cu trc, dng testbench
VHDL modules Synthesis
(4) M phng chc nng thit b mc cng

M phng netlist pre-P&R EDN dng cng c mc cng
(5) M phng theo quan h thi gian trong VHDL

Thc hin file cu trc .vhd v file SDF; dng testbench
Place & Route
(6) M phng quan h thi gian mc cng
M phng netlist post P&R EDN netlist, s dng cc delays
Kim tra thit k?

Test-Bench

Chip level Board level Std parts model Model bus operation Discrete event-driven Flexibility over strictly netlist-driven
Behavioral Module
MCU
FPGA
Memory
PLD
Kt lun
VHDL l mt ngn ng dng m hnh ho phn cng ca thit b Tng hp logic l mt tp con ca ton b ngn ng Cc vn v cng c v cng ngh c nh hng n vic tng hp logic ca mt thit k Cc m phng HDL c th bao gm cc d liu nh thi (back-annotated timing data)
Bi 2
Ngn ng VHDL
Design Units trong VHDL

Entity Architecture Configuration Package Package Body Library
Chng trnh VHDL bao gm cc design units.

Mt s design units c lp vi cc design unit khc.
Cc loi Design Unit
Trong VHDL c hai loi design unit, l:
Primary
Khng ph thuc vo cc design unit khc Ph thuc vo primary design unit
Secondary
Mi khi c thay i trong primary design unit, cn phi kim tra li secondary design unit. Nu khng, chng trnh s c li. Cc secondary unit khng th tn ti c lp -- tc l, phi ph thuc primary unit
Entity
Entity m t external interface ca thc th c thit k, cng cc thuc tnh lin quan vi interface
entity Half_Add is
Sum Carry
port (A, B : in std_logic ;

Carry, Sum : out std_logic) ; B end Half_Add ;
Ch thch: VHDL93 cho php dng optional reserved word entity ngay sau reserved word end, v d, end entity Half_Add ;
Architecture
Architecture m t hot ng bn trong ca thc th (entity) gn vi n (primary unit)
Mt architecture th hin mt chc nng ca thc th gn vi n, c th c nhiu architecture cho mt thc th
architecture My_Arch of Half_Add is begin Sum <= A xor B ;
Carry <= A and B ;

end My_Arch ;
Note: VHDL93 cho php s dng reserved word architecture sau reserved word end
Multiple Architecture
C th c nhiu architecture cng tn ti m t hot ng ca mt thc th
Chng c th biu din cc giai on khc nhau ca qu trnh thit k hoc cc cch tip cn khc nhau cho cng mt chc nng (optimization for speed verus area, etc.)
entity Cnt64 is ... end Cnt64 ; architecture BEH of Cnt64 is ... end BEH ; architecture RTL of Cnt64 is ... end RTL ; architecture XLX of Cnt64 is ... end XLX ;
entity Half_Add is ... end Half_Add ; architecture BEH of Half_Add is ... end BEH ; architecture RTL of Half_Add is ... end RTL ; architecture XLX of Half_Add is ... end XLX ;
Package
Mt package declaration c dng khai bo cc d liu dng cho ton b thit k, bao gm:
Constants, data types, subtypes, subprogram v function declarations, v.v
package My_Pack is
constant. . . ... function. . . ... component . . . ... subtype. . . end package My_pack ; library IEEE; use IEEE.std_logic_1164.all ; ... use work.My_Pack.all ;
entity . . .
Package Body
Mt package body l mt dependent unit ca mt package, n cha cc thng tin chi tit v cc i tng trong package
Subprograms, deferred constants

package body My_Pack is
package My_Pack is
constant. . . declaration ... function bv_to_integer ( ... details component . . . ... subtype. . .
end My_Pack ;
function bv_to_integer (BV: bit_v.. return integer is variable begin for index in BV'range loop ....
... end My_Pack ;
Library
V c bn, tt c cc i tng VHDL u c lu
trong cc th vin
Theo nh ngha, th vin l mt tp hp cc n v
thit k (design unit) c kim chng Work v std l hai th vin dng c cho mi design
unit
library IEEE ; package std_logic_1164 is.. package std_logic_unsigned is.. package std_logic_arith is..
Library
Libraries v Packages comprise the VHDL Design Management structure Theo mt ngha no , n tng t nh directories v
subdirectories
library IEEE ; package std_logic_1164 is.. package std_logic_unsigned is.. package std_logic_arith is..
Khi to cc Library
Tn ca library n thun l mt tham tr v mt logic
Chun VHDL khng quy nh cc yu cu cht ch v cu trc ca library, do vy chng khng d c chuyn giao gia cc tool
library My_Lib
package Fast_Counters is..

library My_Lib ; use My_Lib.Fast_Counters.all ; entity Mod1 is port ( . . .
package DSP_Filters is..
Khi to cc Library
Thng thng, cn phi to cc th vin trong mi tool c th thay v attach cc th vin c u
t tn cho library, v sau phn tch cc design unit c chn a vo n
library My_Lib
package Fast_Counters is..

library My_Lib ; use My_Lib.Fast_Counters.all ; entity Mod1 is port ( . . .
package DSP_Filters is..
Work Library
y l th mc con (sub-directory) mc nh c dng lu gi tt c cc n v thit k c bin dch (compiled design units), tr khi c cc ch nh khc. Mi mt cng c m phng hoc tng hp u s to ra mt cu trc nh th
Ch : hin th library l nhn tn ca design unit ch khng phi l tn ca source file
Work Library
Mt v d v ni dung ca work library
Design Unit entity entity entity package architecture architecture Identifier HALF_ADD DFF REG4 My_Counters. . . RTL STRUCTURAL
Secondary (dependent) design units tham tr ti primary unit tng ng vi n
V d v Hierarchy : DFF
entity DFF is port (D, Clock : in std_logic ; Reset : in std_logic ; Q : out std_logic) ; end entity DFF ; architecture RTL of DFF is begin process (Clock, Reset) begin If (Reset = 1 ) then Q <= 0 ; elsif (Clockevent and Clock = 1) then Q <= D ; end if ; end process ; end architecture RTL ;
Clock
Reset
V d v Hierarchy : REG-4
entity REG_4 is port (D_in : in std_logic_vector (3 downto 0); Clk, Rst : in std_logic; Q_out : out std_logic_vector (3 downto 0)); end REG_4; architecture Structural of REG_4 is component DFF port ( D, Clock : in std_logic ; Reset : in std_logic; Q : out std_logic ) ; end component ; begin U3 : DFF port map (D_in(3), Clk, Rst, Q_out(3)); U2 : DFF port map (D_in(2), Clk, Rst, Q_out(2)); U1 : DFF port map (D_in(1), Clk, Rst, Q_out(1)); U0 : DFF port map (D_in(0), Clk, Rst, Q_out(0)); end Structural;
REG_4 D_in(3)
DFF U3
Q_out(3)
D_in(2)
DFF U2
Q_out(2)
D_in(1)
DFF U1
Q_out(1)
D_in(0) Clk Rst
DFF U0
Q_out(0)
Lin kt Tn hiu
C hai phng php lin kt cc tn hiu vi cc cng tng ng ca chng
Lin kt theo v tr: Cc tn hiu mc cao c lit k theo ng trt t ca cc cng (port) mc thp trong component declaration U1: DFF port map (D_in, Clk, Rst, Q_out) ;
component DFF port (D, Clock : in std_logic ; Reset : in std_logic ; Q : out std_logic ) ; end component ;
Lin kt Tn hiu
C hai phng php lin kt cc tn hiu vi cc cng tng ng ca chng
Lin kt theo tn: Cc cng (ports) v tn hiu (signals) c lit k mt cch r rng, y , khng ph thuc trt t (strongly recommended) U1: DFF port map ( D =>D_in(1), Clock =>Clk, Reset =>Rst, Q =>Q_out(1)) ;
component DFF port (D, Clock : in std_logic ; Reset : in std_logic ; Q : out std_logic ) ; end component ;
Signal Declaration
Tt c cc tn hiu bn trong thc th cn phi c khai bo r rng

entity Top is port (I1, I2 : in std_logic; 01, 02 : out std_logic) ; end Top ;
architecture Structural of Top is component Sub_A port (A1, A2, A3 : in std_logic ; A4 : out std_logic_vector (3 downto 0)) ; end component ; component Sub_B port (B1: in std_logic_vector (3 downto 0 ) ; B2, B3, B4 : out std_logic) ; end component ;
Top
Sub_A I1 I2
A4 A1 A2 A3
Sub_B
Bus_1
B1 B3 B2 B4
signal Bus_1 : std_logic_vector (3 downto 0) ; signal Sig_1: std_logic ;
Sig_1
O1 O2
begin U0 : Sub_A port map (I1, I2, Sig_1, Bus_1) ; U1 : Sub_B port map (Bus_1, Sig_1, O1, O2) ; end Structural ;
C th ho phn t
entity REG_4 is port (D_in : in std_logic_vector (3 downto 0) ; Clk, Rst : in std_logic ; Q_out : out std_logic_vector (3 downto 0)) ; end REG_4 ; architecture Xilinx_Struct of REG_4 is component FDC port (D : in std_logic ; Clock, Reset : in std_logic ; Q : out std_logic) ; end component ; begin U3 : FDC port map (D=>D_in(3), Clock=>Clk, Reset=>Rst, Q=> Q_out(3)) ; U2 : FDC port map (D=>D_in(2), Clock=>Clk, Reset=>Rst, Q=> Q_out(2)) ; U1 : FDC port map (D=>D_in(1), Clock=>Clk, Reset=>Rst, Q=> Q_out(1)) ; U0 : FDC port map (D=>D_in(0), Clock=>Clk, Reset=>Rst, Q=> Q_out(0)) ; end Xilinx_Struct ; D_in(0) Clk Rst
Component instantiation from target library may be helpful for chip level optimization ( i.e., Xilinx Virtex )
D_in(3)
FDC U3
Q_out(3)
D_in(2)
FDC U2
Q_out(2)
D_in(1)
FDC U1
Q_out(1)
FDC U0
Q_out(0)
S dng Generics
Generics l cc tham s c th cp nht ng (thay i gi tr) trong tng cu lnh c th ho phn t ca thit k (component instantiation)
iu ny cho php khai bo cc tham s mt cch linh hot, mm do

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned_all; use IEEE.std_logic_arith.all;
entity My_Cntr is generic (Count_Width : integer := 8 ); port ( Data_In: in std_logic_vector (Count_Width -1 downto 0); Clk, Reset, Load, UpDn : in std_logic; Q_Out: out std_logic_vector (Count_Width -1 downto 0)); end entity My_Cntr;
architecture RTL of My_Cntr is end architecture RTL;
Lab
Marker
Cp nht gi tr ca Generics
S dng mt generic map cng vi port map, khi c mt phn t c c th ho u trong thit k
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned_all; use IEEE.std_logic_arith.all; entity MY_TOP_DESIGN is port ( DATA_BUS: in std_logic_vector (63 downto 0); CLOCK, RST, LD, CNTRL : in std_logic; DATA_Out: out std_logic_vector (63 downto 0)) ; end entity MY_TOP_DESIGN;
architecture STRUCTURAL of MY_TOP_DESIGN is
Nu khng c generic map, generic nhn gi tr mc nh ban u
component My_Cntr generic ( Count_Width : integer := 8 ); port ( Data_In: in std_logic_vector (Count_Width -1 downto 0); Clk, Reset, Load, UpDn : in std_logic; Q_Out: out std_logic_vector (Count_Width -1 downto 0)); end component ; begin U0: My_Cntr generic map (Count_Width => 64) port map (DATA_BUS, CLOCK, RST, LD, CNTRL, DATA_OUT ) ; end architecture RTL;
Bin dch VHDL
C th c bn giai on bin dch ng vi bn mc x l cho mt m hnh phn cng VHDL
Analysis (phn tch)
Design unit c kim tra li c php. Sau khi hon tt, n s c lu gi work directory Cu trc hierarchy ca thit k c dn tri bt u t mc cao nht. ng vi mi sub-module c th ch c mt copy duy nht c to ra Dng m t netlist ca thit k c to ra hoc theo format chun cng nghip hoc theo mt vendor-specific format M hnh c m phng theo cc bc thi gian gin on. N c iu khin bi cc s kin cc tn hiu ng b qu trnh
Elaboration (chnh sa)
Synthesis (tng hp)
Execution (ch m phng)
Quy trnh bin dch

entity DFF is port (D, Clk : in Reset: in Q: out
...
architecture..
Analyze
Execute
Elaborate
Synthesize
Trnh t Bin dch
Do mi quan h gia cc primary v secondary design unit cng nh kh nng c th c th ho cc module mc thp hn, nn qu trnh bin dch lun tun theo mt trt t nghgim ngt Cc entity phi c phn tch trc cc architecture tng ng vi chng Cc package cn phi c phn tch trc cc package body Mi mt module cn phi c phn tch trc khi n c tham tr bi cc module khc
y l trnh t bin dch Bottom-up
Comments
Comments (ch thch) c tc dng lm cho m ngun tr nn d hiu hn, iu ny cng tng t nh cc ngn ng khc - - Comments bt u bng hai du gch ngang - - Chng ch tip tc cho n ht dng - - Mt comment trn nhiu dng cn phi dng - - hai du gch ngang trn tt c cc dng
A_OUT <= 1 ; - - Comments c th vit t y
Kt lun
VHDL bao gm cc primary v secondary design unit Trt t bin dch chng trnh VHDL c thc hin theo mt quy lut cht ch Tt c cc design unit c kim chng c lu trong mt th vin gi l work library C th s dng Generics tng tnh linh hot ca m ngun (source code)
Bi 3
Signals v Data Types
Data Types
Data types l mt yu t quan trng trong VHDL (cng nh trong cc ngn ng khc)
Mi mt kiu d liu ch cho php nhn cc gi tr trong mt gii nht nh Mi i tng (signal, variable, constant, hoc port) cn phi c kiu d liu nht nh khi c khai bo (declared) Cc tn hiu lin kt vi nhau cn phi c cng kiu
VHDL l mt ngn ng nh kiu rt cht ch
Trong VHDL c nhiu kiu d liu cho php m t phn cng v kim tra li nhm m bo s tng thch tn hiu trong cc m hnh ln v phc tp
Cn tun th quy tc kim tra kiu trong cc m hnh c hnh vi (behavioral) v mc cng (gate-level)
Signals v Ports
Kiu d liu v rng bus cn phi ph hp trong cc lnh gn tn hiu (signal) v cng vo ra (port)
entity REG_4 is port (D_in1 : in std_logic_vector (3 downto 0); Cntrl : in std_logic_vector (1 downto 0); Clock, Reset : in std_logic; Q_out : out std_logic_vector (3 downto 0)); end entity REG_4; signal signal signal signal A : integer ; B : bit ; C : integer ; D : std_logic ;
A <= C; A <= C + 1; A <= B; D <= C; B <= D; Q_out <= Cntrl;
Cc loi data type trong VHDL
C 4 categories (loi) data types trong VHDL
Scalar
Single value object, defined indices, ordered Group objects, similar or different types Defines pointers to objects covered in Advanced VHDL course Sequence of objects of given type covered in Advanced VHDL course
Composite
Access

File

Scalar Data Types
Kiu ds liu v hng nhn cc gi tr n l. Trong VHDL, lp cc data type ny gm c:

Bit Boolean Integer Real Physical Character Std_logic and std_ulogic Enumerated
Bit v Boolean
Va m hnh ho phn cng, nhng n khng cho php m t cc gi tr high-impedance, unknown, dont care, v.v...
architecture BEHAVE of MUX is signal A,B,Sel, Z : bit ; begin if Sel = 1 then Z <= A ; else Z <= B ; end if . . .
type bit is (0, 1) ;
Thch hp cho vic m hnh ho mc khi nim l thuyt if Sel =1, if F >= G..
type boolean is (false, true) ;
both yield boolean result
Integer v Real
Chp nhn cc gi tr v cc i lng mt cch trc quan v linh hot
Cn phi quy nh gii gi tr cho cc kiu nguyn (integer), nu khng n s s dng gii gi tr mc nh vi s nguyn 32-bit signal B : integer range 15 downto 0 ;
type integer is range . . . signal A : integer range 0 to 7;
Cho php ngi thit k s dng cc gi tr floating point

Khai bo cc kiu real vi gii gi tr thc nht nh Cch dng gi tr kiu Real khng ging nh Integer type CAPACITY is range -25.0 to 25.0 ; type real is range . . . signal Sig_1 : CAPACITY := 3.0 ;
Physical
Kiu vt l (Physical type) c dng nh lng cc i lng vt l nh l khi lng, di, thi gian Kiu vt l c nh ngha theo n v c s ca n
Bt k n v dn xut no cng l bi ca n v c s
type time is range 1 to 1000000 units Time l kiu vt l duy nht c nh ngha trong VHDL. N rt cn thit cho fs; vic m phng thi gian tr v cc tham ps = 1000 fs; s khc c lin quan thi gian. ns = 1000 ps; constant Tpd : time := 3ns ; us = 1000 ns; ... ms = 1000 us; . . .
Z <= A after Tpd ;
Std_logic v Std_ulogic
Std_logic c pht trin t h thng MVL (MultiValue Logic) v c dng m hnh ho phn cng mt cch chi tit hn so vi kiu bit
H tr cc mc gi tr khc nhau ca tn hiu: don't-care conditions, unknown, three-state c nh ngha trong gi IEEE std_logic_1164 U, -- Uninitialized X, -- Forcing Unknown 0, -- Forcing Zero Recall: type bit is 1, -- Forcing One Z, -- High Impedance limited to (0, 1). W, -- Weak Unknown L, -- Weak Zero H, -- Weak One - -- Dont Care );
type std_ulogic is (
C hai kiu u cha cng mt tp cc gi tr nh nhau

So snh Std_logic v Std_ulogic
S khc nhau ch thc hin mch (implementation) Ch u trong ulogic c ngha l unresolved
Nu ngi thit k s dng hai hay nhiu tn hiu iu khin mt ca ra chung th anh ta phi dng mt hm resolution (c trong gi ieee_std_1164) quyt nh trn thc t tn hiu no c a ti ca ra Std_ulogic khng c kh nng , nhng n to ra mt cng c ni ti kim tra cc li wired-oring do s sut
signal A,B,C,Res_Out : std_logic ; signal Out_1 : std_ulogic ; Out_1 <= A ; Out_1 <= B ; Out_1 <= C ; Res_Out <= A; Res_Out <= B; Res_Out <= C;
A B C
A B C
Out_1
Res_Out
Signal Resolution
Mt ca ra c th khng th c nhiu tn hiu iu khin kiu wire-or
m hnh mt ca ra ba trng thi, ta s dng mt lnh gn tn hiu c iu kin v data-type l std_logic:

signal A,B,C,Res_Out : std_logic ;
Res_Out <= A when En0 = 1 else Z ; Res_Out <= B when En1 = 1 else Z ; Res_Out <= C when En2 = 1 else Z ;
En0
A
En1
B
En2
Res_Out
Enumerated (lit k)
Tng mc linh hot trong vic m hnh ho phn cng
Cc kiu lit k do ngi dng nh ngha s dng cc gi tr c th nhn bit mt cch d dng v thch hp vi hot ng ca m hnh Lm cho cc chng trnh d hiu hn nht l khi m t cc my trng thi (h logic dy) hoc cc h thng phc tp
type My_State is ( RST, LOAD, FETCH, STOR, SHIFT ) ;
...
signal STATE, NEXT_STATE : My_State ; ... case (STATE) is when LOAD => . . . if COND_A and COND_B then NEXT_STATE <= FETCH ; else NEXT_STATE <= STOR ;
Composite Data Types
Cc data type hn hp l s kt hp cc phn t di dng mt array hoc mt record
Bit_vector, Std_logic_vector v String l cc kiu hn hp c nh ngha trong VHDL
signal A_word : bit_vector (3 downto 0) := 0011 ;
Cu lnh ny to nn mt kiu bit_vector (array) t mt nhm 4 bit
Trong VHDL khng nh ngha u l LSB hoc MSB; do vy, khi bin dch gi tr ny khng c t ng hiu l 3 Ch : dng du trch kp (0011) cho cc i tng c kiu bit_vector, std_logic_vector hoc string, v dng du trch n (1) cho cc i tng c kiu bit, std_logic v character
Array
Array l nhm cc phn t n c cng kiu (type) ban u

type WORD is array (3 downto 0) of std_logic ; signal B_bus : WORD ;
B_bus
Nu B_bus c kiu WORD, gi tr c th 3 2 1 0 c ca cc index position phn t l? Cn nu B_bus c kiu signal B_bus : DATA ; DATA? type DATA is array (3 downto 0) of integer range 0 to 9 ;
Php gn cc Array
Khi gn gi tr mt array cho mt array khc, th: 1. Cc array cn phi c cng kiu gi tr 2. Cc array phi c cng di 3. Php gn c thc hin theo v tr, t tri sang phi
signal My_BusA, My_BusB: bit_vector (3 downto 0) ; signal My_BusC : bit_vector (0 to 3) ;
My_BusB <= My_BusA ; 3 2 1 0

My_BusA My_BusA
My_BusC <= My_BusA ; 3 2 1 0
My_BusB 3 2 1 0
My_BusC 0 1 2 3
Inadvertent bit-swap?
Cch vit lnh gn Array
n gin cc php gn array v lm cho chng trnh d c hn - ngi thit k c th s dng cc gi tr c s 16 (hexadecimal) hoc 8 (octal)
C th s dng du gch di cc gi tr bin cho d c

signal Data_Word : std_logic_vector (11 downto 0) ;
Data_Word <= XA6F; Data_Word <= 101001101111 ; Data_Word <= O5157; Data_Word <= B1010_0110_1111 ;
Records
type OPCODE is record PARITY : bit; ADDRESS : std_logic_vector ( 0 to 3 ); DATA_BYTE : std_logic_vector ( 7 downto 0 ); NUM_VALUE : integer range 0 to 6; STOP_BITS : bit_vector (1 downto 0); end record ; ... signal TX_PACKET, RX_PACKET : OPCODE; Record l nhm cc phn t n c kiu ban u c th khc nhau.
...
PARITY ADDRESS DATA_BYTE NUM_VALUE STOP_BITS
TX _ PAC K ET
String
signal Warning1: string (1 to 30) := Unexpected Outputs Detected ;
--declared within the architecture
String l array ca cc character
variable Warning2: string (1 to 30) := Unstable, Aborting Now ;

--declared within the process
constant Warning3: string (1 to 20) := Entering FSM State2 ;

--declared within the package or architecture
process ( A_sig , B_sig, C_sig ) process ( A_sig , B_sig, C_sig ) begin begin if (A_sig and B_sig ) /= 1 then if (A_sig and B_sig ) /= 1 then report Unexpected Outputs ; report Warning1; elsif ( A_sig and C_sig ) = 1 then elsif ( A_sig and C_sig ) = 1 then report I need a vacation ; report Warning2 & Problem Mod2; end if ; end if ; process ( A_sig , B_sig, C_sig ) end process ; end process ; begin assert (A_sig and B_sig ) /= 1 then report Warning1; severity note ; end if ; end process ;
Php gp cc Array
Php gp (Aggregate) l mt cng c tin li nhm cc kiu d liu (data type) c v hng v phc hp trong cc php gn
signal H_BYTE, L_BYTE: std_logic_vector ( 0 to 7); signal Q_Out : std_logic_vector (31 downto 0); signal A, B, C, D : std_logic; signal WORD : std_logic_vector (3 downto 0);
Only scalar data variables are allowed on the left-side aggregates. (A,B,C,D)<=WORD; WORD <= ( 2 => 1, 3 => D, others => 0 ) ; Q_Out <= ( others => 0 ) ; WORD <= ( A, B, C, D ) ; H_Byte <= ( 7|6|0 => 1, 2 to 5 => 0 ) ;
The total number of elements on both sides of any assignment must match, others can be used as a default assignment, regardless of the array size
Gp cc Record
Php gp (Aggregate) l mt cng c tin li nhm cc kiu d liu (data type) c v hng v phc hp trong cc php gn
type D_WORD is record UPPER : std_logic_vector (7 downto 0 ) ; LOWER : std_logic_vector (7 downto 0 ) ; end record ; signal DATA_WORD : D_WORD ; signal H_BYTE, L_BYTE: std_logic_vector (7 downto 0); signal TX_PACKET, RX_PACKET : OPCODE; --defined earlier DATA_WORD <= ( H_BYTE, L_BYTE) ; Only records can accept aggregate of arrays
TX_PACKET <= ( 1,0011,11101010,5,10 ) ; DATA_WORD <= ( LOWER => L_BYTE, UPPER=> H_BYTE) ; TX_PACKET. ADDRESS <= ( 0011 ) ; TX_PACKET. ADDRESS(2) <= 0 ; DATA_WORD <= ( LOWER | UPPER=> H_BYTE); DATA_WORD <= ( others => H_BYTE);
To lp cc Array 2-D
Khi cn m hnh ho cc cu trc b nh, ngi thit k phi to ra mt cu trc array 2 chiu (2-D structure)
y thc s l mt array ca cc array (hoc cc record)

7 6 5 4 3 2 1 0
type Mem_Array is array ( 0 to 3 ) of std_logic_vector ( 7 downto 0); signal My_Mem : Mem_Array ;
0 1 2
To Array ca cc Record dng trong cc Array ca cc record thng c

ng dng x l gi tin (packet handling)
type Data_Array is array ( 0 to 2 ) of OPCODE ; signal My_Data : Data_Array ;
type OPCODE is record PARITY : bit; ADDRESS : std_logic_vector ( 0 to 3 ); DATA_BYTE : std_logic_vector ( 7 downto 0 ); NUM_VALUE : integer range 0 to 6; STOP_BITS : bit_vector (1 downto 0); end record ; ... signal TX_PACKET, RX_PACKET : OPCODE;
My_Data ...
DATA_BYTE NUM_VALUE STOP_BITS
PARITY
ADDRESS
... ...
Php gn cc Array 2-D
Vi hu ht cc ng dng ca memory, vector a ch Read/Write c chuyn thnh dng integer, tham tr ti mt phn t trong array 2-D - Hm bin i conv_integer c trong gi
ieee.std_logic_unsigned
type Mem_Array is array ( 0 to 3 ) of std_logic_vector ( 7 downto 0 ); signal My_Mem : Mem_Array ; signal R_Addr, W_Addr : std_logic_vector (1 downto 0 ) ;
7
0 1 2 3
0
My_Mem (conv_integer( W_Addr)) <= Data_In ; ... D_Out <= My_Mem (conv_integer (R_Addr));
Initializing a ROM Array
Vi cc ng dng ROM, php kt tp (aggregate) l mt cng c tin ch kch hot mng array 2-D
type ROM_Array is array ( 0 to 3 ) of std_logic_vector ( 7 downto 0); constant My_ROM : ROM_Array := --continued below
7 0 1
0
constant My_ROM : ROM_Array := ( 0 => (others => 1) , 1 => 10100010, 2 => 00001111, 3 => 11110000 ) ;
2
3
Kiu con trong VHDL
Mt kiu con (subtype) trong VHDL l mt tp hp c hn ch ca mt kiu (type) c
Kiu c cng c th l mt kiu c nh ngha trong IEEE1076 hoc cng c th do ngi dng to ra subtype My_Int is integer range 0 to 255 ;
Label
Base Type
Constraint
subtype My_Small_Int is My_Int range 5 to 30 ; Cc kiu con (Subtypes) thng c dng pht hin li out-of-range trong kt qu m phng, v cng c th c tc dng ti u ho qu trnh tng hp logic
S dng kiu con trong VHDL

type My_State is ( Load, Jump, Add, Sub, Div, Mult, StorA, StorB) ; signal Curr_State, Next_State : My_State ;
subtype Arith_Ops is My_State range Add to Mult ; Label Base Type Constraint
subtype My_OHE_State is std_logic_vector ( 3 downto 0 ) ; constant Init_St0 : My_OHE_State := 0001 ; constant Load_St1 : My_OHE_State := 0010 ; constant Jump_St2 : My_OHE_State := 0100 ; constant Stor_St3 : My_OHE_State := 1000 ;
Bi 4
Operators v Expressions
Cc ton t trong VHDL
VHDL cha mt lng ln cc ton t (operator) dng cho vic m hnh ho phn cng Tuy nhin, mi ton t c s dng vi (nhng) kiu d liu (data type) nht nh
c bit, cn lu cc ton t s hc (arithmetic) khng dng c vi cc kiu d liu phc hp (bit_vector and std_logic_vector), v cc array khng c gi tr bng s tng minh
Cc Function (subprogram) c to ra khc phc nhng vn lin quan
Cc hm ny c trong cc gi c gi l arithmetic packages
Operator Overloading
Operator overloading (chng hm) trong VHDL c ngha l mt ton t c th (v d, + ) c th c dng vi cc data type khc nhau
iu ny xy ra do cc subprogram ring bit c vit cho tng data type nht nh

signal A, B : std_logic_vector ( 3 downto 0 ) ; signal C, D : integer range 0 to 31 ; signal Q_Out : std_logic_vector ( 15 downto 0 ); Y <= A + B ; F <= C + D ; Q_Out <= Q_Out + 1; -- add 2 vectors -- add 2 integers -- add vector and integer
Compiler t ng chn sub-function thch hp da trn data type ca cc operands

Cc ton t Logic
Cc logical operator c nh ngha vi cc ton hng c kiu (data type) bit, boolean, bit_vector v std_logic_vector
A Z B F Z <= A and B ; H Y G Y <= G or ( F and H ) ;
and or nand nor xor not xnor (VHDL-93)
Cc ton t Logic vi bin kiu Array

signal A_vec, B_vec, C_vec : bit_vector ( 7 downto 0 ) ;
A_vec (7) B_vec (7) A_vec (6) B_vec (6) A_vec (5) B_vec (5)
C_vec (7) C_vec (6) C_vec (5)
C_vec <= A_vec and B_vec ;
. . .
C_vec (0)
A_vec (0) B_vec (0)
Quy tc s dng vi bin kiu Array 1. Cc array phi c cng kiu (type) 2. Cc array phi c cng kch thc 3. Php ton thc hin vi cc phn t cng v tr trong mi array, t tri sang phi
Cc ton t quan h
Cc ton t quan h c th dng vi hu ht cc data type Tt c cc ton t quan h u cho kt qu kiu (type) Boolean
= /= < <= > >= Equality Inequality Less than Less than or equal Greater than Greater than or equal
signal FLAG_BIT : boolean ; signal A, B : integer ;
FLAG_BIT <= ( A > B ) ;
Nu A ln hn B, FLAG_BIT s c gn gi tr true, ngc li FLAG_BIT c gn gi tr false
Ton t quan h vi cc Array

signal A_vec : bit_vector ( 7 downto 0 ) := 11000110 ; signal B_vec : bit_vector ( 5 downto 0 ) := 111001 ;
Rules for use on Arrays 1. Arrays must be same type 2. Arrays may be different lengths 3. Arrays of different lengths are aligned left and then lexically compared -- Compares ASCII values
Quy tc: m bo php so snh s c hp l cc array cn phi c cng kch thc
if ( A_vec > B_vec ) then State <= Normal else State <= Code_Red d ny cho kt qu l false end if Cc vector c so snh t tri sang phi. Vic so snh c thc hin ln lt theo tng phn t
Cc ton t s hc
Cc ton t s hc dng vi cc kiu d liu (data type) integer, real, v physical

Cc ton t s hc vn khng dng vi cc d liu c kiu array
+ * / abs **
Addition Subtraction Multiplication Division Absolute Value Exponentiation
signal A_num, B_num : integer range 0 to 15 ; signal Z_num : integer range 0 to 31 ; Z_num <= ( A_num + B_num ) ; A_num
+
B_num
Z_num
Infers a 5-bit adder
Php tnh s hc vi cc bin Array
thc hin cc php tnh s hc cn c cc function nh ngha sn trong IEEE hoc t cc hng cung cp phn mm thit k
Cc function nh vy thng c t trong cc gi gi l arithmetic packages. Mt s cng c (tool) dch sn cc gi ny v t th vin ca chng Cc gi std_logic_unsigned v std_logic_arith c xc lp trong th vin IEEE pht huy kh nng trao i m ngun gia cc cng c khc nhau
package STD_LOGIC_UNSIGNED is function + (A,B: std_logic_vector) return std_logic_vector ; function + (A: std_logic_vector, B: integer ) return std_logic_vector ; function + (A,B: std_logic_vector) return integer ; .... library IEEE ; use IEEE.std_logic_1164.all ; use IEEE.Std_Logic_Unsigned.all ; Ton t + l overloaded use IEEE.Std_Logic_Arith.all;
Array Arithmetic
Nu c cc function thch hp c th dng c trong module thit k (thng qua mnh use), th compiler s t ng truyn tham s cho tr li kt qu tnh t subprogram
Nu khng, compiler s thng bo li rng cc operator l undefined

signal signal signal signal A_vec : std_logic_vector ( 7 downto 0 ) := 11001001 ; B_vec : std_logic_vector ( 7 downto 0 ) := 11100100 ; Z_vec : std_logic_vector ( 8 downto 0 ) ; D_int : integer range ( 0 to 9 ) ;
Z_vec < = A_vec + B_vec ; Z_vec < = A_vec + D_int ;
Cc ton t Shift (dch)
Cc ton t Shift c nh ngha trong VHDL-93 v rt hay c s dng, nht l khi cn m t hot ng ca cc phn t trong cu trc my tnh
Mi ton t c hai ton hng, ton hng tri c kiu array one-dimension (1-D) v ton hng phi c kiu nguyn (integer) ch s bc cn dch (hoc quay). S m cng c dng ch chiu dch (hoc quay) ngc li
Kt qu ca cc php dch (hoc quay) c cng kiu v kch thc vi ton hng tri
Cc ton t Shift (dch)

sll - Logical left shift srl - Logical right shift sla - Arithmetic left shift sra - Arithmetic right shift rol - rotate left logical ror - rotate right logical
Shift Operator - Cc v d
V d: signal A_vec : bit_vector (7 downto 0) := 11000110; signal D_vec : bit_vector (7 downto 0); D_vec <= A_vec sll 2; D_vec <= A_vec sra 2; D_vec <= A_vec ror 3; D_vec <= A_vec srl 2; D_vec <= A_vec sra -2; 00011000 11110001 11011000 00110001 00011000
cho kq
Concatenation
Ton t ni (concatenation) & cho php kt ni cc bin kiu scalar v kiu array thnh kiu array ln hn
Cc php gn c thc hin vi s tng hp v tr (positional association)

signal signal signal signal signal A_vec, B_vec : std_logic_vector ( 7 downto 0 ) ; Z_vec : std_logic_vector ( 15 downto 0 ) ; A_bit, B_bit, C_bit, D_bit : std_logic ; X_vec : std_logic_vector ( 2 downto 0 ) ; Y_vec : std_logic_vector ( 8 downto 0 ) ;
Z_vec <= A_vec & B_vec ; X_vec <= A_bit & B_bit & C_bit ; Y_vec <= B_vec & D_bit ;
Nhm cc ton t
C th s dng du ngoc n nhm cc ton t trong mt biu thc cho lm cho n d c hn
Z <= A + B + C + D ; A B
Z <= ( A + B ) + ( C + D ) ; A B Z C D
+
C
+
D
+
+ +
Z
3 logic levels
2 logic levels
This is especially important when the target technology is LUT (Look-Up Table) based. Each added level of logic incurs additional block and routing delays
Cc Slice ca Array
Mt nhm cc phn t k cn nhau trong mt array c goi l mt slice v c th c tham tr ng thi
Cc phn t khc ca array khng b nh hng bi php gn slice
signal A_vec, B_vec : std_logic_vector (7 downto 0) ; signal Z_vec : std_logic_vector (15 downto 0) ; signal A_bit, B_bit, C_bit, D_bit : std_logic ;
Z_vec (15 downto 8) <= A_vec ; B_vec <= Z_vec (12 downto 5) ; A_vec (1 downto 0) <= C_bit & D_bit ; ... Z_vec (5 downto 1) <= B_vec (1 to 5 ) ;
The direction (ascending or descending) of the slice must be consistent with the direction of the array as it was originally declared
Slice v Concatenation
V d, m hnh ho mt biu thc c iu kin vi cc phn t c chn khng lin nhau (9,8,3,2,1, v 0) t Status bus gm 16-bit
Gii m ton b bus c th lm tng s lng mch logic t hp v lm cho thit b lm vic chm hn)
signal Status_Bus : std_logic_vector (15 downto 0) ;
process ( Status_Bus ) begin case ( Status_Bus ) is when 1101111101010011 => < sequential statement(s) > ; when . . .
Inefficient !!
signal Int_Bus : std_logic_vector ( ... Int_Bus <= Status_Bus ( 9 downto 8 ) & Status_Bus ( 3 downto 0 ) ;
process ( Status_Bus ) begin case ( Status_Bus(9 downto 8) & Status_Bus (3 downto 0)) is when 110011 => < sequential statement(s) > ; process ( Int_Bus ) when . . . begin case ( Int_Bus ) is when 110011 => 5 downto 0 ) ; < sequential statement(s) > ; when . . .
Will Not Compile!
Optimal !!
Bi 5
Cc cu lnh Concurrent v Sequential
M hnh ho phn cng
m hnh ho mt thc th phn cng mt cch c hiu qu, VHDL s dng c cc cu lnh concurrent (ng thi) ln sequential (tun t) Cc cu lnh c gi l concurrent khi chng c thc hin khng tu thuc vo v tr ca chng trong chng trnh Cc cu lnh c gi l sequential khi chng c thc hin mt cch tun t theo trnh t vit chng trong chng trnh, ging nh cc lnh trong cc phn mm thng thng
Tt c cc cu lnh vit trong mt process l nhng lnh sequential
Cu trc ngn ng
architecture RTL of ENTITY_1 is . . . begin concurrent statements ; ... process begin sequential statements ; ... end process ; ... concurrent statements ; ... process begin sequential statements ; ... end process ; ... end architecture RTL ;
Mi cu lnh nm ngoi mt process u l lnh concurrent
Process
Mt process bao gm cc cu lnh sequential
Cc cu lnh trong mt process c thc hin ln lt
Mi process u phi c hot kch theo mt cch nht nh
architecture RTL of My_And2 is begin ... process (A, B) begin C <= A and B ; end process ; ... end architecture RTL;
Thng l do s thay i ca cc tn hiu trong process, hoc cc iu kin c th trong mt cu lnh wait
Cc Process l ng thi
Trong vic m hnh ho phn cng, quan im v concurrency (tnh ng thi) l rt cn thit
Bt k s thay i no tn hiu C - ca ra ca cng G1, cng u c ng thi a ti ca vo ca cc cng G2 v G3 Process 1 Process 2

C C
If C = 1 then ...
A B G1
G2
C<=A and B ...
Process 3
G3
process (C,..) begin
M hnh kt ni trong VHDL
Ch c cc tn hiu (signal) l c th chuyn gi tr t mt process sang mt process khc
Cc process concurrent, c lin kt bi cc tn hiu, thng c gi l VHDL Connectivity Model (m hnh kt ni) Process n Process n1
Sig1 Sig2
C<=A and B ...
C C
If C = 1 then ...
Process n3
process (...
Process n4
process n
Process n2
process (C,..) begin
Rst
Cc thnh phn ca Process

Keyword Optional Label Signals in sensitivity list create implied wait condition
Signal updated with new value when process suspends
Keywords end and process
architecture Behave of DFF is begin ... Reg1: process (Clock, Reset) begin if Reset = 1 then Q <= 0 ; elsif ( Clockevent and Clock = 1 ) then Q <= D ; end if ; end process; All statements within ... the process are handled sequentially, in order end Behave ;
Bn trong v bn ngoi Process

architecture ... process ( ) begin Out1 <= A; Out1 <= B; ... end process ; end architecture ;
Out1
Ch c php gn cui cng l c hiu lc
A
architecture . . . begin Out1 <= A; Out1 <= B; ... end architecture ;
?
B
Out1
Cn phi c mt hm resolution cho tn hiu ra Out1
Tm dng cc Process
Mi process cn phi c mt c ch kch hot, iu cng c ngha l c c ch tm dng (suspending) process
iu ny to nn trng thi i (wait) cho process
Vi on m RTL, cc tn hiu trong sensitivity list to nn mt iu kin wait mc nhcho process i vi cc m hnh hnh vi, ngi thit k thng dng cc cu lnh wait. Trong VHDL c bn dng lnh wait
wait on... wait until... wait for ... wait An event on given signal A specific condition A specified time amount Indefinite suspension wait on A, B ; wait until CLK = 1 ; wait for 10 ns ; wait;
Cc iu kin Wait
V d di y so snh cc iu kin wait t cc cu lnh c vit r rng (explicit) v iu kin wait n (implicit)
Note: Mt s compiler dng tng hp mch khng h tr iu kin explicit wait

process begin wait on A, B ; C <= A and B ; end process ; process begin C <= A and B ; wait on A, B ; end process ;
process (A, B) begin C <= A and B ; end process ;
FYI: Another important consideration is that all processes are initialized before simulation, that means they are run until the first wait condition is met Given that fact, what is the value on C at simulation time zeroassuming use of std_logic for each of the examples above ?
Modeling Concurrency
Cng c m phng VHDL c hot kch theo s kin
Ti mt thi im bt k trong thi gian m phng, (1) tt c cc process c thc hin cho n khi b tm dng, (2) gi tr ca cc tn hiu c cp nht, (3) s thay i gi tr cc tn hiu lm cho cc process lin quan c thc hin
Thi gian gia cc cng on ny c gi l delta cycle Theo cch , cc process v cc lnh concurrent c coi nh xy ra ng thi ti mi im m phng
Concurrent Operations Delta cycles in-between Delta cycles in-between
...
Simulation discrete time step
D1 1001
D+1
D+2 . . . D+n 1002
D1
D+1
D+2
998
999
1000
Sp xp trnh t cc Event
C ch sp xp trnh t cc event l ht nhn ca mi trng m hnh ho hnh vi trong VHDL Mi hot ng (transaction) ca thc th c sp t mt thi im thch hp Bc thi gian ch tng ln khi khng cn transaction no khc thi im m phng
Scheduling Events
Delta cycles Simulation discrete time steps Delta cycles
...
ns
D1
D+1
D+2 . . . D+n t+4
D1
D+1
D+2
t+1
t+2
t+3
Transaction Queue
Out1 <= 1 ; Out2 <= 0 ; ... Int <= 1 after 1 ns; ... Data <= 0 after 2 ns; ...
t+3 Out1<= 1
Delta Cycles
Out2<= 0 ...
t+4 Int <= 1 ...
t+5 Data<= 0 ...
Discrete Time
Transactions
Cu lnh gn tn hiu Z <= A to ra mt transaction trong VHDL

process (. . .) begin Z <= A ; F <= G ; ... end process ;
C th, gi tr hin ti ca A c c v c dng gn cho tn hiu Z
Events
Nu gi tr ca Z hoc F thc s c thay i sau lnh gn (transaction), ta ni c mt event xut hin tn hiu Mi mt php gn tn hiu u gy ra mt transaction, nhng khng phi tt c cc transaction u lm xut hin cc event tn hiu c gn Mt event mt tn hiu cho c th hot kch mt process ch khi tn hiu c tn trong sensitivity list ca proccess
process (A, G) begin Z <= A; F <= G; ... end process ;

Process 1
Z<=A; ...
Process 2
Z Z
If Z = 1 then ...
Process 3
process (Z,..) begin
Building Registers
process ( Clk) begin if (Clkevent and Clk = 1) then C <= A and B ; end if; end process;
Mi php gn tn hiu xy ra sau mnh :

if clockevent and clock = 1 then...
u to ra mt cu trc thanh ghi (register)

A B
Clk C
Khi qut v Signal v Variable trong VHDL

Hu nh mi kt ni gia cc im trong mt thc th u c th c m hnh ho bng signal (tn hiu) hoc variable (bin) Tuy nhin, cn phn bit cch dng, cc kh nng v nhng hn ch ca tng i tng ny mc thc th, tt c cc port c khai bo thuc lp signal, chng c kh nng trao i gi tr vi cc module khc, v c th dng c cho mi process c khai bo trong cc architecture body l thuc Trong mi architecture body, tt c cc tn hiu c khai bo ch c tc dng cc b vi architecture , v ch c dng vi cc process c khai bo trong cng architecture Trong mi process, c th khai bo v s dng variable m phng cc mi lin kt cc b
Phm vi ca Signal v Variable

Port l signal, c khai bo mc cao nht (entity) Trong mi architecture c th c cc signal cc b Trong mi process c th c cc variable cc b entity architecture process Variables
Signals
Input Ports Output Ports
Php gn vi Signal
VHDL phn bit rt r rng trong vic x l vi cc i tng thuc cc lp signal v variable Cc quy tc c bn l:
Tt c cc signal v variable c gn phi c cng kiu (type) Tt c cc signal v variable c gn phi c cng kch thc (size)
Nu signal l mt port, ngi thit k phi lu thm:
Signals c mode in c th c nhng khng c gn gi tr Signals c mode out c th c gn gi tr trong process, nhng khng c c
Php gn vi Signal
Internal_Cnt entity Count_1 is port (Clk, D : in bit ; Q : out integer range...); end Count_1;
Counter
architecture WRONG of Count_1 is begin process (Clk) begin If Clkevent and Clk =1 then Q <= Q + 1; end if ; end process ;
Will produce compiler error
architecture RTL of Count_1 is signal Internal_Cnt : integer range ... ; begin process (Clk) begin If Clkevent and Clk =1 then Internal_Cnt <= Internal_Cnt + 1 ; end if ; end process ; Q <= Internal_Cnt ;
Using Variables
V phm vi ca mt variable ch gii hn trong process n c khai bo, ta khng th s dng n trao i gi tr vi cc module khc, nh cch s dng cc signal Bt k variable no c c trc khi gi tr ca n c xc nh, u s c suy din nh l mt register trong cu trc hardware nu nh n c dng vi mt process c clock
Phi cn thn khi s dng variable trong cc process c clock
Tuy nhin, rt nn s dng cc variable c trong cc mch logic t hp trung gian Chng lm tng tc ca vic chy m phng v ch cn t delta cycles cho vic cp nht cc tn hiu ra
Variable trong cc Process c Clock

process ( Clk ) variable B, C, D : bit := 1 ; begin If (Clkevent and Clk =1) then B := A ; C := B ; D := C ; end if ; end process ; process ( Clk ) variable B, C, D : bit := 1 ; begin If ( Clkevent and Clk =1 ) then D := C ; C := B ; B := A ; end if ; end process ;
Clk
Clk
Alternate Solution
Internal_Cnt entity Count_1 is port (Clk, D : in std_logic ; Q : out std_logic_vector ...); end Count_1;
Counter
architecture WRONG of Count_1 is begin process (Clk) begin If Clkevent and Clk =1 then Q <= Q + 1; end if ; end process ; Will produce
compiler error
architecture RTL of Count_1 is begin process (Clk) variable Internal_Cnt : std_logic_vector.. begin If Clkevent and Clk =1 then Internal_Cnt := Internal_Cnt + 1 ; Q <= Internal_Cnt ; end if ; end process ;
Bi 6
Cc lnh iu khin chng trnh trong VHDL
2003 Xilinx, Inc. All Rights Reserved
Cu trc ngn ng
Cc lnh if/else,
case hoc loop

phi c vit bn trong mt process
architecture RTL of ENTITY_1 is . . . begin concurrent statements ; ... process begin case ( sel_a ) is when ... end case ; end process ; ... ... process begin if (sel_b = 00) then ... else. end if ; end process ; ... end architecture RTL ;
Cc cu lnh If/Else
Cu lnh if/else lm cho cc giao dch c thc hin da trn nhng iu kin nht nh. C ba dng lnh if/else c bn sau:
process begin if (boolean expression) then sequential statements; end if ; process begin if (boolean expression) then sequential statements ; else sequential statements ; end if ; process begin if (boolean expression 1) then sequential statements ; elsif (boolean expression 2) then sequential statements ; elsif (boolean expression 3) then sequential statements ; else sequential statements ; end if ;
V d v lnh If/Elsif
1. iu kin u tin tho mn s c thc hin ngay 2. Cc iu kin c th gi nhau 3. iu kin u tin ca lnh if/elsif c u tin cao nht
process (A, B, C, D, Sel) D begin If (Sel = 00) then C Z <= A ; elsif (Sel = 01) then Z <= B ; B elsif (Sel = 10) then Z <= C ; elsif (Sel = 11) then A Z <= D ; end if; end process ; Sufficient for std_logic? A B C D Sel Z
Z Late arriving signal?
Cu lnh Case

Cu lnh case lm cho cc giao dch c thc hin tu thuc vo gi tr ca biu thc chn Lnh case c hai dng c bn:
process () begin case ( selector expression ) is when ... => sequential statements ; when ... => sequential statements ; when ... => sequential statements ; end case ; ... end process ; process (...) begin case ( selector expression ) is when ... => sequential statements ; ... when others => sequential statements ; end case ; ... end process ;
V d v lnh Case
Tt c cc gi tr c th c ca biu thc chn u phi c ch r (specified) trong cu lnh Cc iu kin khng c chng cho (gi) nhau Gii cc gi tr c m t phi hu hn (discrete) Lnh Case thch hp vi cc cu trc kiu LUT
Hu ht cc cng c tng hp mch process (A, B, C, D, Sel ) u to ra cu trc MUX t lnh case begin
A B C D Sel Z
case Sel is when 00 when 01 when 10 when 11

end case ; ... end process ;
=> => => =>
Z Z Z Z
<= A ; <= B ; <= C ; <= D ;
Is this sufficient for std_logic?
Cc iu kin chng cho
V d di y minh ho trng hp cc iu kin chng cho nhau. Khi ta ch c th s dng lnh if/elseif. Mun s dng lnh case phi chnh li cc iu kin
process (A, B, C, D, Sel) begin If (Sel <= 3) then Z <= A ; elsif (Sel <= 5) then Z <= B ; elsif (Sel <= 7) then Z <= C ; elsif (Sel <= 9) then Z <= D ; end if; end process ;
D C B Z
Gii hu hn cc gi tr
Nu mt gii cc gi tr c dng lm iu kin ca mt lnh case hoc if/else, n cn phi hu hn (discrete)

process () begin if (x = 12 to 14) then ... case ( selector expression ) is when 0 to 7 => when 4.3 to 7.7 => when 1000 to 1010 => when 1000 | 1010 => ... end process ;
sequential statements ;
sequential statements ; sequential statements ; sequential statements ; sequential statements ;
Lnh gn Signal c iu kin
Lnh gn tn hiu c iu kin l mt dng c tc dng tng ng lnh if/else

architecture ... begin process ( A,B, C, Sel ) begin if (Sel = 00 ) then Z <= A ; elsif (Sel = 10) then Z <= B ; elsif (Sel = 11) then Z <= C ; else Z <= X ; end if ; end process ; end architecture ;
architecture ... begin Z <= A when Sel = 00 else B when Sel = 10 else C when Sel = 11 else X ; end architecture ;
C hai cu lnh u c chung mt kt qu khi m phng hoc tng hp mch
Tuy nhin, cu trc bn phi lm cho chng trnh ngn gn hn
Lnh gn Signal c la chn
Lnh gn tn hiu c la chn l mt dng lnh c tc dng tng ng vi lnh case Quy tc s dng hon ton ging vi lnh case:

(1) Tt c cc iu kin phi c lit k (2) Cc iu kin khng c chng cho nhau
architecture ... begin process ( A,B,C, SEL ) begin case (SEL) is when 00 => Z <= A ; when 10 => Z <= B ; when 11 => Z <= C ; when others => Z <= X ; end case ; end process ; end architecture ;
architecture... with SEL select Z <= A when 00 , B when 10 , C when 11 , X when others ; end architecture ;
Outline
If/else Statements Case Statement Concurrent Form of If/else and Case Statements Loop Statements Summary
Cc cu lnh Loop

Cc cu lnh loop c th c dng cho mi trng hp c vng lp Lnh loop c nhiu dng khc nhau, mi dng s dng mt phng php iu khin lp ring. Dng thng dng nht l for loop
Bin ch s index cho vng lp khng c khai bo process ( A, B_bus ) ring, khng th gn gi begin tr cho n, v khng c for i in 7 downto 0 loop s dng ngoi vng lp C_bus (i) <= A and B_bus (i) ; N c dng nh l end loop ; mt hng s Sau mi php lp, gi tr ca n c cp nht theo chiu hng ghi trong cu lnh t tri sang phi
S dng cc lnh Loop
Khi tng hp, lnh loop c dn tri ra
Vic tng hp mch da trn kt qu logic ca tng php lp
process ( A, B_bus ) begin for i in 7 downto 0 loop C_bus (i) <= A and B_bus (i) ; end loop ;
Khi m phng, cc lnh loop to nn mt cng c linh hot m hnh ho hnh vi Cc lnh loop c bit cn hay c s dng trong cc chng trnh con (function v procedure)
A B_bus (7) A B_bus (6)
C_bus (7) C_bus (6)
. . .
C_bus (0)
A B_bus (0)

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Bi 1

Vn M t phn cng (Hardware Modeling)

Cn VHSIC l t vit tt ca Very High Speed Integrated Circuit

Tip theo, chng ta bt u tm hiu v xut x v mc ch ca ngn ng ny

VHDL - Mc ch v s hnh thnh

VHDL, trc ht v ch yu l mt cng c m hnh ho phn cng (hardware modeling)

m phng (simulation) v tng hp (synthesis) mch

Ging nh cc chun kc ca IEEE, chun IEEE 1076 c sa i theo chu k ti thiu l 5 nm

IEEE 1076 (synthesis)

IEEE 1076 (modeling)

Cc mc tru tng trong m t phn cng

Chi tit hn, ph thuc cng ngh, thit k v m phng chm hn

S chng cho trong VHDL

FPGA Vendor Library

Place & Route Utility

Trnh t thit k Top-Down

VHDL h tr hng tip cn top-down trong thit k

Tn hiu ra c cht (Register) ti bin gii cc module

Gim n ti thiu s clock trn mi block

Duy tr cc tn hiu then cht trong phm vi mi block

Kch thc ca tng block nh c th kim tra nhanh chng

Mu th nhanh, n gin cho mi sub-module

Cu trc Top - Down

Kim tra thit k

Gate-Level Functional (Netlist-driven )

VHDL Initiative Toward ASIC Libraries

Place & Route

Gate-Level Timing (Back-annotated netlist )

SDF (Standard Delay Format) & Structural VHDL File

Cc bc kim tra thit k

Thc hin m ngun m t hnh vi, dng testbench

(2) M phng RTL

(3) M phng chc nng trong VHDL

VHDL modules Synthesis

(4) M phng chc nng thit b mc cng

(5) M phng theo quan h thi gian trong VHDL

Place & Route

(6) M phng quan h thi gian mc cng

M phng netlist post P&R EDN netlist, s dng cc delays

Kim tra thit k?

Design Units trong VHDL

Entity Architecture Configuration Package Package Body Library

Chng trnh VHDL bao gm cc design units.

Cc loi Design Unit

Trong VHDL c hai loi design unit, l:

Khng ph thuc vo cc design unit khc Ph thuc vo primary design unit

port (A, B : in std_logic ;

Architecture m t hot ng bn trong ca thc th (entity) gn vi n (primary unit)

Mt architecture th hin mt chc nng ca thc th gn vi n, c th c nhiu architecture cho mt thc th

architecture My_Arch of Half_Add is begin Sum <= A xor B ;

Carry <= A and B ;

C th c nhiu architecture cng tn ti m t hot ng ca mt thc th

Constants, data types, subtypes, subprogram v function declarations, v.v

Subprograms, deferred constants

V c bn, tt c cc i tng VHDL u c lu

Theo nh ngha, th vin l mt tp hp cc n v

Tn ca library n thun l mt tham tr v mt logic

package Fast_Counters is..

package DSP_Filters is..

Thng thng, cn phi to cc th vin trong mi tool c th thay v attach cc th vin c u

t tn cho library, v sau phn tch cc design unit c chn a vo n

package Fast_Counters is..

package DSP_Filters is..

Ch : hin th library l nhn tn ca design unit ch khng phi l tn ca source file