Diode-Transistor Logic (DTL)

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Diode Logic
VA VB OR GATE VOUT AND GATE VA VB VCC

VOUT

n n

Diode Logic suffers from voltage degradation from one stage to the next. Diode Logic only permits the OR and AND functions. Diode Logic is used extensively but not in integrated circuits!

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Level-Shifted Diode Logic

AND GATE VA VB VCC=5V RH x VOUT DL RL
With either input at 0V, Vx=0.7V, DL is just cut off, and VOUT=0V. With both inputs at 1V, VX=1.7V and VOUT=1V. With VA=VB=5V, both input diodes are cut off. Then

VOUT
n n n

VCC 0.7V = RL RH + RL

Level shifting eliminates the voltage degradation from the input to the ouput. However, the logic swing falls short of rail-to-rail, and the inverting function still is not available without using a transistor!
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Diode-Transistor Logic (DTL)

VCC VA VB VC Q1 RC VOUT Primitive Precursor to DTL

n n n n

If any input goes high, the transistor saturates and VOUT goes low. If all inputs are low, the transistor cuts off and VOUT goes high. This is a NOR gate. Current Hogging is a problem because the bipolar transistors can not be matched precisely.
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Diode-Transistor Logic (DTL)

VCC RB VA VB VC If all inputs are high, the transistor saturates and VOUT goes low. If any input goes low, the base current is diverted out through the input diode. The transistor cuts off and VOUT goes high. This is a NAND gate. The gate works marginally because VD = VBEA = 0.7V.
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RC VOUT Q1

Improved gate with reversed diodes.

n n n n

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Diode-Transistor Logic (DTL)

VCC
RB RC

VA VB VC

x Q1
RD

VOUT

Basic DTL NAND gate.

n n n

If all inputs are high, Vx = 2.2V and the transistor is saturated. If any input goes low (0.2V), Vx=0.9V, and the transistor cuts off. The added resistor RD provides a discharge path for stored base charge in the BJT, to provide a reasonable tPLH.
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DTL VTC
VCC VOUT
RB RC
5 4

VA VB VC

x Q1
RD

VOUT

3 2 1 0 0 1 2 3 4 5 VIN

VOH = VOL =
n

VIL = VIH =

The noise margins are more symmetric than in the RTL case.
62

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DTL Power Dissipation

RB=3.4k RC=4.8k RD=1.6k RB

VCC
RC

PL =
VOUT Q1

VA VB VC

RD

PH =
n

Scaling RB and RC involves a direct tradeoff between speed and power.

P=
63

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DTL Fanout
RB=3.4k RC=4.8k RD=1.6k F=50

VCC
RB RC

I CS =

VA VB VC

x Q1
RD

VOUT

I BS = I CS = N max =
64

Good fanout requires high F, large RD /RB.

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930 Series DTL (ca 1964 A.D.)

F=50
1.75k 2k

VCC
6k

VA VB VC

Q1 Q2
5k

VOUT

One of the series diodes is replaced by Q1, providing more base drive for Q2 and improving the fanout (Nmax = 45). Does Q1 saturate? 930 DTL Characteristics 5.0V / 0.2V VOH / VOL 1.5V / 1.4V VIH / VIL 45 Fanout 10mW Dissipation 75ns tP
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930 DTL Propagation Delays

F =50 CL=5pF
1.75k 2k

VCC
6k

tPLH >> tPHL tPLH = tS+tr /2

ts =
Q1 Q2
5k

VA VB VC

VOUT

tr
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Transistor-Transistor Logic (TTL)

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Why TTL?
VA VB VC
n n

DTL

The DTL input uses a number of diodes which take up considerable chip area. In TTL, a single multi-emitter BJT replaces the input diodes, resulting in a more area-efficient design. DTL was ousted by faster TTL gates by 1974.

VA VB VC

TTL
n

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Basic TTL NAND Gate.

VCC=5V RB D1 RCP VOUT QO RD n n

ALL INPUTS HIGH.

QI is reverse active. QO is saturated. VOL = VCES

VA VB VC

QI

ANY INPUT LOW.

QI is saturated. QO is cut off. VOH = VCC

Multi-emitter transistor. Forward-biased emitter base junctions override reverse-biased junctions in determining the base and collector currents.
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TTL Switching Speed: tPLH

VCC=5V RB RC RCP VOUT QO RD CL
n n n

VA VB VC

QI

QS

The depletion capacitance of the QI EB junction must discharge; Base charge must be removed from the saturated QS; Ditto for QO; and The capactive load must be charged to VCC.

Multi-emitter transistor. Forward-biased emitter base junctions override reverse-biased junctions in determining the base and collector currents.
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TTL Switching Speed: tPLH

VCC=5V RB RC RCP VOUT QO RD CL
n n

VA VB VC

QI

QS

The time required to discharge the QI depletion layers is << 1ns. The time required to extract the QS base charge is also << 1ns: QI becomes forward active; |IBR| becomes large for QS

Removal of base charge from QO is similar to the DTL case. With RD = 1 k, ts = 10ns (these are typical values for 7400 series TTL).
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TTL Switching Speed: tPLH

VCC=5V RB RC RCP
3 5 4

VOUT

VA VB VC

QI

QS QO RD

VOUT CL

2 1 0 0 100 200

t (ns)
300

Charging of the capacitive load can be slow with passive pullup. e.g., with a 5k pull-up resistor and a 15 pF load (ten TTL gates) RC = 75 ns and tr = 2.3RC = 173 ns!
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TTL with Active Pullup

n

In the previous example, the dominant switching speed limitation was the charging of capacitive loads through the pullup resistor. A small pullup resistance will improve the switching speed but will also increase the power and reduce the fanout.
VCC RC QP VOUT QO RD
n

With active pullup, we can achieve the best of both worlds:

n

When the output is low, QP is cutoff, minimizing the power and maximizing the fanout; when the output goes high, QP becomes forward active to provide maximum drive current for a quick rise time.
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TTL with Active Pullup

n

With a high output, n QS is cutoff n QP is forward active With a low output, n QS is saturated n QP should be cutoff

VCC=5V RB RC QP VOUT QO RD

The low output case is unsatisfactory with this circuit: VBP = VBEP = VEP =

VA VB VC

QI

QS

The Totem Pole Output solves this problem.

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TTL with Totem Pole Output

VCC=5V RB RC QP RCP
n n

VA VB VC

QI

QS QO RD

During turn-off, QS switches off before QO. QP begins to conduct when VCS = VCESO+VD+VBEAP = 1.6V Initially,

DL VOUT

I BP =

RCP limits the collector current to a safe value.

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Typical 74xx Series TTL

VCC=5V

4k

1.6k

130

QP

VA VB VC

QI

QS QO
1k

DL VOUT

74xx TTL Characteristics 12 ns tPLH 8 ns tPHL 10 Fanout 10 mW Dissipation 100 pJ PDP

1/3 T. I. 7410 triple 3-input NAND

The anti-ringing diodes at the input are normally cut off. During switching transients, they turn on if an input goes more negative than -0.7V.
76

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Standard TTL: VTC

F =70 R = 0.1
4k

VCC=5V
RC 1.6k

VIN=0. QI is saturated; QS, QO are cutoff; QP is forward active. VOH =

130

QP

VIN

QI

QS QO
1k

DL VOUT
n

(the drop in the base resistor is small) First Breakpoint. QS turns on. VIL = (at the edge of conduction, IC=0)
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1/6 NSC 7404 Hex Inverter

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Standard TTL: VTC

F =70 R = 0.1
4k

VCC=5V
RC 1.6k

Second Breakpoint. QO turns on. VIN = VOUT =

130

QP

VIN

QI

QS QO
1k

DL VOUT

Third Breakpoint. QO saturates. VIH =

1/6 NSC 7404 Hex Inverter

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Standard TTL: VTC

1/6 NSC 7404 Hex Inverter 4k

VCC=5V
RC 1.6k

VOUT
5 4 3

130

QP

VIN F =70 R = 0.1

QI

QS QO
1k

DL VOUT

2 1 0

VIN
1 2 3 4 5

VNML =
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VNMH =
79

Standard TTL: Low State ROUT

100
2.4 mA 2 mA 1.6 mA

collector current (mA)

80
0.08V 1.2 mA 0.8 mA

For the saturated BJT with IB = 2.4 mA, the output impedance is

60
21 mA

ROL =
The very low output impedance means that noise currents are translated into tiny noise voltages. Thus only a small noise margin is neccesary.
80

40
IB = 0.4mA

20
Characteristics for a 0 Texas Instruments junction isolated digital npn BJTat 25 oC.

0.1

0.2

0.3

0.4

0.5

collector-emitter voltage (V)

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Standard TTL: Input Current

1/4 TI 7400 Quad VCC=5V 2-input NAND 4k RC 1.6k 130
n

IIH

(QI is reverse active)

I BI =

QP VA VB QI QS QO
1k
n

DL VOUT

I IH =
IIL (QI is saturated)

F =70 R = 0.1

I IL =
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Standard TTL: DC Fanout

1/4 TI 7400 Quad VCC=5V 2-input NAND 4k RC 1.6k 130
n

With high inputs,

I CI = I CS = I BO =
n

QP VA VB QI QS QO
1k

DL VOUT

F =70 R = 0.1

To keep QO saturated,

N max =

AC considerations usually limit the fanout to a much lower number.

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Standard TTL: DC Dissipation

1/4 TI 7400 Quad VCC=5V 2-input NAND 4k RC 1.6k 130

PH =

QP VA VB QI QS QO
1k

DL VOUT

PL =

F =70 R = 0.1 N = 10

P=
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Advanced TTL Designs

n n

Schottky Clamping. QS and QO may be Schottky clamped,

preventing saturation. This greatly improves tPLH.

Darlington Pullup. The Darlington pullup arrangement

increases the average output drive current for charging a capacitive load. Although RCP limits the maximum output current, this maximum drive is maintained over a wider range of VOUT than with a single pullup transistor.

Squaring Circuit. Active pull-down for the base of the output

transistor squares the VTC, improving the low noise margin. An added benefit is faster charge removal for the output transistor.

Improved Fabrication. Smaller devices, and oxide isolation,

have steadily reduced parasitic capacitances and reduced RC time constants.

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84

Darlington Pullup
VCC=5V
RC
900

RCP
50

QP

QP2
REP
3.5k

VOUT

QP2 is added, forming a Darlington pair with QP. The EB junction of QP2 introduces a 0.7V level shift, so DL can be eliminated. QP2 can not saturate, so Schottky clamping is not neccessary. REP is needed to provide a discharge path for QP2 base charge.

The Darlington emitter follower provides a very low output impedance, approaching RC / 2. This greatly reduces the rise time.

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Squaring Circuit
VOUT
QS QO RBD
500

VOUT
RCD
250

VIL BP2

VOH 4
3 2

7400 74S00

QD

VOL

1 0 1

BP3 VIH
2 3 4 5

VIN

n n n n

There is no path for QS emitter current until QD and QO turn on. QS and QO begin to conduct simultaneously. BP1 is eliminated from the VTC; in other words, the VTC is squared. VIL is increased, improving the low noise margin.
86

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Schottky TTL (74S / 54S Series)

1/4 74S00 quad 2-input NAND RB
2.8k

VCC=5V
RCP
50

Features:
n n n n n

RC
900

QP

QP2

VA VB

QI

QS REP
3.5k

Schottky clamping Schottky anti-ringing diodes Darlington pullup circuit Squaring circuit Scaled resistors

VOUT
QO RBD
500

Performance:
n n n

RCD
250

QD

P = 20 mW tP = 3 ns (15 pF) PDP = 60 pJ

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