PRIST UNIVERSITY

PUDUCHERRY CAMPUS

PRE SEMESTER
Course:B.Tech [Part-Time] Dept: CSE Sub: COMPUTER ARCHITECTURE AND ORGANIZATION Answer the following Questions: 1. Define: pipelining. 2. Define Stall. 3. Define: Cache Memory 4. Define TLB. 5. Differentiate memory mapped I/O and mapped I/O. 6. Define privilege exception. 7. Give any 2 disadvantage of hardwired control? 8. List out the objectives of USB. 9. Define: hardwired control. 10. What is meant by Hazard? Answer the following Questions: 11. a) i) Narrate the features and working of Super Scalar operation. ii) Explain Execution of a complete instruction. (08) (Or)
b) Discuss Data Hazards in detail.

Semester: I Date: 24.12.2012 (10*2=20)

(5*16=80) (08)

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12. a) i)Explain multiple bus Organization with a neat diagram ii) Explain some fundamental Concepts to execute a Program. (Or) b) Explain in brief about Hard Wired control unit with a neat diagram. 13. a ) Briefly explain the principles and working of Virtual Memory. (Or) b) Discuss in detail about various Secondary Storage Devices. 14. a ) i)Discuss about Cache Memory. ii) What is ROM? Explain the types of ROM. (Or) b) Explain in detail about Interrupts. 15. a) Give a brief explanation about Direct Memory Access. (Or) b) Briefly explain the principles and working of USB.