The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation

ABSTRACT
When the DA (distributed arithmetic) algorithm is directly applied in FPGA (field programmable gate array) to realize FIR (finite impulse response) filter, it is difficult to achieve the best configuration in the coefficient of FIR filter, the storage resource and the computing speed. According to this problem, the paper provides the detailed analysis and discussion in the algorithm, the memory size and the look-up table speed. Also, the corresponding optimization and improvement measures are discussed and the concrete hardware realization of the circuit is presented. The results of simulation and test show that this method greatly reduces the FPGA hardware resource and the high speed filtering is achieved. The design has a big breakthrough compared to the traditional FPGA realization. The sigma-delta modulator based closed loop systems make high resolution, high SNR, low frequency systems. The sigma-delta analog to digital converter consists of the modulator followed by the decimation filter. In this project the design and FPGA implementation of decimation filter, which performs the action of filtering the shaped quantization noise and converting 1-bit data stream into 20 bit high-resolution output is reported. The multi-stage decimation methodology is adapted, with the Cascaded Integrator Comb (CIC) filter followed by a FIR filters. The specifications of decimation filter are derived from the specifications of a third-order single bit sigma-delta modulator. Distributed arithmetic algorithm is used to design FIR filters. The hardware model for the filter is developed using verilog HDL

ADVANTAGES:
Analog Mixed Signal Designing Signal Processing Applications

LANGUAGE USED:
Verilog HDL

TOOLS REQUIRED:
MODELSIM Simulation XILINX-ISE Synthesis

PROJECT MEMBERS GUIDE: ARCHANA A.Suneel Kumar (09d91a0408) A.l.Manikanta (09d91a0409)