EFFICIENT DESIGN OF APPLICATION SPECIFIC DSP CORES

USING FPGAs
Saniay Attri, Electronics & Commn Engg.Deptt., Technical Teachers' Training Institute, Sector-26,
Chandigarh, India. Tel: +91-0172-794349, E-mail: sattri@yahoo.com
B.S. Sohi, Electronics & Cornmn Engg.Deptt., Technical Teachers' Training Institute, Sector-26,
Chandigarh, India. Tel: +91-0172-791349, E-mail: bssohi@yahoo.com
Y.C. Chopra, Electronics & Commn Engg. Deptt., BBSB Engineering College, Fatehgath Sahib,
Punjab, India. Tel: +91-0172-791349, E-mail: ycchopra@?yahoo.com

Abstract ever decreasing time to market has

This paper focuses on design of digital
signal processing (DSP) cores for
compact and efficient implementations
of real fime DSP applications on field
programmable gate arrays (FPGAs)
using distributed arithmetic. The
resulting serial distributed arithmetic
(SDA) and the parallel-distributed
arithmetic (PDA) designs are
implemented. As an example, the
implementation of a 16-tap 8-bit Finite
impulse response (FIR) filter on a Xilinx
XC4000E FPGA using SDA and PDA
techniques has been examined. An
anaiysis of fhe performance comparison
is described. The results show that PDA
designs with a digit size of 2 bits are
more efficient in area-time product
parameter than those of SDA
implementations.
1. Introduction
The increasing need to digitally
process analog information signals, like
audio and video, is causing a major shift
in the DSP implementation techniques.
Since DSP is the mathematical
manipulation of these digitized
information signals, specialized circuitry
is required for efficient signal
processing. Moreover, in this era of
rapid system design the goals that are
to be met are reduction in design and
verification time, reduction in cost of
design and its Iife cycle and capability of
insertion of new innovations in the
design. The increasing complexity of
modern integrated circuits coupled with
0-7803-6677-8/01/$10.0002001 IEEE.
pushed the design complexity and
correctness to such a level that it has
necessitated the use of pre-verified
functions. A pre-defined and pre-verified
complex functional block that is
integrated into the designer's logic is
called a core. The rapid trend towards
sub-micron technologies has brought
forth the new concept of System-Level-
Integration (SLI). This new approach
makes use of a core to save
development time while focusing
engineering time and energy on those
parts of the design that add value and
differentiate the product.
2. Core-based design
Core-based designs have several
benefits like
shorter design-cycle times
reduced risk and
0 improved performance through
higher levels of integration
The end result of designs based on core
lead to shorter time-to-market, lower
production costs, and improved system
profit margins [I],
The advent of large, fast FPGAs with
dedicated arithmetic capabilities has
created an opportunity to perform
flexible, re-programmable DSP functions
in dedicated lagic, rather than DSP
processors [Z], [3].The advantages of
this approach are multiple:
A higher speed with respect to the
general-purpose DSP solution can
be obtained.

462
 Re-configurable systems can be
realized using the re-
programmability of the FPGAs.
DSP and ASIC based systems can
be fast prototyped, different design
options can be emulated, and long
simulations can be avoided.
Off-chip interconnections and
external components like FlFOs or
RAMS can be integrated in the
embedded applications.
Hard-wired DSP cores can be
simplified and optimized for a given
application.
The FPGAs have the ability to
implement a DSP function using one of
several techniques, which depend on
the performance required. These
techniques can be used to optimize the
implementation of many different types
of data processing or MAC-based
techniques. In the areas where the
speed of conventional bit parallel circuits
is not needed, techniques based on
distributed arithmetic (DA) can be used
141. Parallel Distributed Arithmetic (PDA)
techniques are used to achieve the
fastest sample rates, while lower rates
can be sustained with Serial Distributed
Arithmetic (SDA) techniques that use
less FPGA resources (i.e. configurable
logic blocks (CLBs)). In addition, a serial
stream of data matches better with the
structure of an FPGA. Thus, in an actual
implementation, the speed of a full serial
circuit is not N times lower than the
equivalent N-bit parallel approach [5].
The primary design concern is the
performance or the sample rate of the
filter and the design must work at the
desired sample rate without over-
consuming the resources. The designs
thus obtained can be verified and built
into a core for use with various DSP
systems.
3. FIR filters
In this paper design of FIR filter, that
is a fit case for being built into a core, is
463
taken up. A filter is used to remove
unwanted portions from a stream of
data. FIR filters are common
components in many DSP systems and
are used to perform signal pre-
conditioning, anti-aliasing, band
selection, interpolation, low-pass filtering
etc. The advantages of the FIR filter
include guaranteed stability for all
realizable filter coefficient values,
absence of overflow oscillations and the
ability to implement filters with linear
phase response. There are several
basic structures of FIR filters such as
canonical, pipelined and inverted form.
In FIR filter applications, arithmetic
elements for operations such as
addition, multiplication and delay are
commonly required[6], [a. These
arithmetic circuits can be designed and
implemented using common sub-circuit
building blocks.
3.1 16 tap, 8 bit FIR filter design
The response of a K tap FIR filter
can be expressed as the following sum
of products:
k=l
Where y(n) is the response at time n,
xk(n) is the k th prior input data at time n
and the Ak are the coefficients of the
filter. Each term, when expanded,
involves only one bit of the input data
with all the bits of the coefficients. This
allows constructing a look-up table that
can be addressed by the same bit of all
input variables. This look-up table holds
all the additive combinations. Figure 1
gives the data flow diagram for a 16-tap,
8-bit FIR filter that is based on
distributed arithmetic [8]. The filter
consists of the following seven major
components:
0 a parallel to serial converter,
0 a RAM-based shift register ,
 a serial adder,
a Look-Up Table (LUT),
a complementing register,
an adder and
a scaling accumulator.
] the lookup tables to generate the
Figure 1. Data Flow diagram of a 16 Tap, 8
bit FIR Filter
An 8-bit data sample is loaded into
the parallel to serial converter (PSC) at
the sample rate. The PSC generates a
serial output stream that is supplied to
the RAM-based shift registers at the bit
clock rate. The bit clock rate is
determined by
bit clock rate = (n + 1)wample rate
where (n+l) represents the number of
data bits per sample plus an overflow
bit.
FIR filters consume a large number
of registers (N bits T taps). This is
particularly demanding in any FPGA
architecture because the logic in front of
the flip-flops is wasted. The XC4OOOE
on-chip RAM significantly reduces the
cost of data storage. Using this feature,
up-to-64 bits of data can be stored in a
single CLB that otherwise could only
store two bits in its flip-flops. This
situation is exploited by using a look-up
table (LUT) based approach. By doing
this a SDA based MAC gets reduced to
the one shown in Figure 2.
This RAM-based shift register
approach, rather than a more traditional
cascade of data registers, significantly
reduces the overall size of the FIR filter.
The outputs of the registered serial
464
adders are presented to the lookup
tables. Since the coefficients are
symmetric, the sums generated by the
adders can be multiplied by the same
coefficients. Since all possible partial
products are pre-computed, the outputs
of the serial adders are used to address
appropriate multiplication results. The
outputs of the registered lookup tables
are summed, except for the sign result
that is complemented before being
summed. The registered summation is
then fed into a scaling accumulator.
Figure 2 suggests that the number of
MACs for a 16 Tap, 8 Bit FIR Filter
should be four. However, the number of
MACs reduces by a factor of two if we
consider the filter to be symmetrical [9].
A
f %
__
S-REG
LOOK. '
C
UP
I t
__
S-REG
c
'4
I TABLE
' D --
.
...
Figure 2. LUT based SDA for a four product
MAC
In this case a 16 Tap, 8 Bit FIR Filter
core is designed. The core is then
embedded into Xilinx XC4000E series
FPGA chip using Synopsis FPGA
Express software tool [IO]. The core is
developed to operate at a sampling rate
of 5.44 MHz and a clock frequency of 49
MHz. The look-up tables contain
coefficients corresponding to a low pass
filter which has a cut-off frequency of 2.2
MHz. FPGA Express was used to create
two types of implementations. One
implementation was done for speed
optimization and it gave an estimated
clock speed of 53.79 MHz. The other
implementation was for siticon area
optimization and it gave an estimated
clock speed of 33.48 MHz. These
results show the trade-off between
silicon area and speed of the
implementation. Thus a filter design
implemented in an FPGA with SDA
gives a significant amount of
performance in a modest number of
CLBs i.e. 68. SDA uses the smallest
number of CLBs while processing all
data samples (TAPS) in parallel.
Parallel Distributed Arithmetic
Parallel Distributed Arithmetic (PDA)
is used to increase the overall
performance of Serial Distributed
-I-,A
Is=+
Arithmetic. With PDA, the number of bits
being processed during each clock cycle
is increased. For this, the data words of
size W bits are partitioned into digits of
size N bits (the digit-size, N, is divisor of
the word-size, W) and are processed
serially one digit at a time with the least
significant digit first [Ill.A complete
word is processed in W/N clock cycles
and consecutive words follow each
other continuously. The time W/N is
called sample period. The digit-serial
operators are cascaded following the
data-flow algorithm in a pipelined
fashion. Hence, a set of PDA
architectures can be designed by using
different digit-sizes.
Note that increasing the number of
bits sampled has a significant effect on
the number of CLBs used for the design.
Therefore, the number of parallel bits
sampled should be increased only to
meet the required performance.
Increasing the number of bits processed
from I-bit, in the case of SDA, to a 2-bit
PDA results in half the number of
processing clock cycles. Hence, 2-Bit
PDA results in twice the throughput.
With 2-bit PDA, the serial shift registers,
referenced in the discussion on SDA,
are each replaced with two similar I-bit
shift registers at half the bit depth. The
two parallel shift registers are spilt, such
465
that one stores the even-bits and the
other stores the odd-bits. The 2-bit
parallel data samples require twice the
number of LUTs. There is also the
addition of a 1-bit scaling adder,
required to add the two partial sums,
which results from each of the two
parallel sample bits. The scaling
accumulator’s input bus is expanded to
accommodate the larger partial sum and
the final scaling accumulator is changed
from a 1- to a 2-bit shift for scaling. A
four product MAC with a digit-size of two
is shown in Figure 3.
* BITS[(~.I),...,5,3.ij
I
LOOK-
UP
TABLE
. PS-BITS-0
Figure 3. LUT based four product MAC for
PDA of digit size two
These changes in MAC structure
essentially double the resources
required compared to that of the SDA
design. Thus, it is possible to choose
the digit-size that best suits the speed of
the application while minimizing the cost
in terms of area [12].
The performance for the 16-Tap FIR
filter example, implemented with a PDA
algorithm having digit size of 2, resulted
in a sample rate of 10.88 MHz, in 130
CLBs. Thus a filter design implemented
in an FPGA with 2-Bit PDA results in
twice the performance and about twice
the number of CLBs compared to the
same function with SDA. 2-Bit PDA uses
more number of CLBs than that of SDA,
while still processing all data samples
(TAPS) in parallel, at twice the SDA
data sample rate. The number of bits
being processed during each clock cycle
can be increased until a BDA
implementation with digit size n is
reached, for n-bit data samples. When
the design is an n-Bit PDA, the sample
data rate is at a maximum.
With FDA, each additional parallel
bit requires an additional level of scaling
(by powers of 2) and summation for
each partial product pair of bits. The
LUTs for SDA and PDA can always be
the same for any given 4-MAC block,
regardless of the number of bits in the
sample data. This is true for PDA only if
common bit-weighted sample inputs are
used to address the LUT.
It may be necessary to tune a filter in
a system, or even have multiple filter
settings. Here the SRAM technology of
the XC4000E can be exploited by
reconfiguring the parameterized part.
The changes to the filter lie in the
coefficients with the actual structure of
the design remaining unchanged. These
coefficients are stored as partial
products. In case, it is desired to change
the filter characteristics, it can be
achieved by simply altering the VHDL
fife that contains the coefficients for the
desired filter.
Conclusion
A study of SDA and PDA FIR filters
with programmable coefficients is
presented. The design methodology
using each of these structures is
detailed and finally the results of their
implementation in Xilinx XC4000E
FPGA are given. The results of 2-bit
PDA are more efficient in area-time
product parameter. The throughput
achieved lets the filters be used in
applications where the sample rate
466
range goes up to 6 MHz using the bit-
serial approach optimized for speed and
more than 50MHz with bit-parallel one.
All filters have been automatically
implemented using Synopsis Workview
office tools. Further, hand optimisation is
known to yield still better results in most
of these cases.
In order to tune a filter in a system,
or even have multiple filter settings, the
SRAM technology of the XC4000E can
be exploited by reconfiguring the
parameterized part.
References
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