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  • Multiplexor Stimulus Verilog Code

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    Miguel Bruno
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    This document describes a stimulus for testing a 4 to 1 multiplexor. It initializes the multiplexor inputs to arbitrary values, sets the control lines to different binary combinations, and displays the output each time to verify the multiplexor is functioning properly. The control lines are set to 00, 01, 10, and 11 sequentially while monitoring the output to ensure it matches the expected value based on the control line values and the input signals.

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    This document describes a stimulus for testing a 4 to 1 multiplexor. It initializes the multiplexor inputs to arbitrary values, sets the control lines to different binary combinations, and displays the output each time to verify the multiplexor is functioning properly. The control lines are set to 00, 01, 10, and 11 sequentially while monitoring the output to ensure it matches the expected value based on the control line values and the input signals.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    1 views1 page

    Multiplexor Stimulus Verilog Code

    Uploaded by

    Miguel Bruno
    This document describes a stimulus for testing a 4 to 1 multiplexor. It initializes the multiplexor inputs to arbitrary values, sets the control lines to different binary combinations, and displays the output each time to verify the multiplexor is functioning properly. The control lines are set to 00, 01, 10, and 11 sequentially while monitoring the output to ensure it matches the expected value based on the control line values and the input signals.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    27/12/12

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    Stimulus for the 4 to 1 Multiplexor
    m o d u l em u x s t i m u l u s ; r e gi n 1 ,i n 2 ,i n 3 ,i n 4 ; r e gc n t r l 1 ,c n t r l 2 ; w i r eo u t ; m u l t i p l e x o r 4 _ 1m u x 4 _ 1 ( o u t ,i n 1 ,i n 2 ,i n 3 ,i n 4 ,c n t r l 1 ,c n t r l 2 ) ; i n i t i a lb e g i n i n 1=1 ;i n 2=0 ;i n 3=1 ;i n 4=0 ; $ d i s p l a y ( " I n i t i a la r b i r t a r yv a l u e s " ) ; # 0$ d i s p l a y ( $ t i m e ,"i n p u t 1 = % b ,i n p u t 2 = % b ,i n p u t 3 = % b ,i n p u t 4 = % b " , i n 1 ,i n 2 ,i n 3 ,i n 4 ) ; { c n t r l 1 ,c n t r l 2 }=2 ' b 0 0 ; # 1$ d i s p l a y ( $ t i m e ,"c n t r l 1 = % b ,c n t r l 2 = % b ,o u t p u ti s% b " , c n t r l 1 ,c n t r l 2 ,o u t ) ; { c n t r l 1 ,c n t r l 2 }=2 ' b 0 1 ; # 1$ d i s p l a y ( $ t i m e ,"c n t r l 1 = % b ,c n t r l 2 = % b ,o u t p u ti s% b " , c n t r l 1 ,c n t r l 2 ,o u t ) ; { c n t r l 1 ,c n t r l 2 }=2 ' b 1 0 ; # 1$ d i s p l a y ( $ t i m e ,"c n t r l 1 = % b ,c n t r l 2 = % b ,o u t p u ti s% b " , c n t r l 1 ,c n t r l 2 ,o u t ) ; { c n t r l 1 ,c n t r l 2 }=2 ' b 1 1 ; # 1$ d i s p l a y ( $ t i m e ,"c n t r l 1 = % b ,c n t r l 2 = % b ,o u t p u ti s% b " , c n t r l 1 ,c n t r l 2 ,o u t ) ; e n d e n d m o d u l e

    www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/Branches/stimulus.html

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