LU HANH NOI BO 07/2005 Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 1 CHUONG I TONG @UAN
Verilog HDL la mot trong hai ngon ng mo phong phan cng thong dung nhat, c dung trong thiet ke IC, ngon ng kia la VHDL. HDL cho phep mo phong cac thiet ke de dang, sa cha loi, hoac thc nghiem bang nhng cau truc khac nhau. Cac thiet ke c mo ta trong HDL la nhng ky thuat oc lap, de thiet ke, de thao g, va thng de oc hn dang bieu o, ac biet la cac mach ien ln. Verilog thng c dung e mo ta thiet ke bon dang: Thuat toan (mot so lenh giong ngon ng C nh: if, case, for,while). Chuyen oi thanh ghi (ket noi bang cac bieu thc Boolean). Cac cong ket noi( cong: OR, AND, NOT). Chuyen mach (BJT, MOSFET). Ngon ng nay cung ch ro cach thc ket noi, ieu khien vao/ra trong mo phong. Cau truc chng trnh dung ngon ng Verilog
// Khai bao module Module ten chng trnh (ten bien I/O); // ten chng trnh trung ten file.v. Input [msb:lsb] bien; Output [msb:lsb] bien;
Reg [msb:lsb] bien reg; Wire [msb: lsb] bien wire;
// Khai bao khoi always, hoac khoi initial. cac lenh
Endmodule
Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 2 Chuong II CHUC NANG CAC TU VUNG TRONG VERILOG
Nhng tap tin van ban nguon Verilog bao gom nhng bieu hien thuoc tnh t vng sau ay: I. Khoang trang Khoang trang ngan nhng t va co the cha khoang cach, khoang dai, dong miva dang ng dan. Do o, mot lenh co the a ra nhieu dong phc tap hn ma khong co nhng ac tnh ac biet. II. Chu giai Nhng chu giai co the ch nh bang hai cach: ( giong trong C/C++) Chu giai c viet sau hai dau gach xien (//). c viet tren cung mot dong. c viet gia /* */, khi viet nhieu dong chu giai. III. Ch so: Lu tr so c nh ngha nh la mot con so cua cac bit, gia tr co the la: so nh phan, bat phan, thap phan, hoac thap luc phan. V du: 3b001, 5d30 = 5b11110, 16h5ED4 = 16d24276 = 16b0101111011010100 IV. T nh danh: T nh danh do ngi dung quy nh cho bien so, ten ham, ten moun, ten khoi va ten trng hp. T nh danh bat au bang mot mau t hoac ng gach di _ ( khong bat au bang mot con so hoac $ ) va ke ca moi ch so cua mau t, nhng con so va ng gach di, t nh danh trong Verilog th phan biet dang ch. V. Cu phap: K hieu cho phep: ABDCEabcdef1234567890_$ Khong cho phep: cac k hieu khac -, &, #, @ Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 3 VI. Toan t: Toan t la mot, hai, hoac ba k t dung e thc hien cac toan hang tren bien. Cac toan t bao gom >, +, &, !=. VII. T khoaVerilog: Co nhng t ma phai co y ngha ac biet trong Verilog. V du: assign, case, while, wire, reg, and, or, nand, va module. Chung khong c dung nh t nh danh. T khoa Verilog cung bao gom ca ch dan chng trnh bien dch va System Task (he thong soan thao) va cac ham.
Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 4 Chuong III CAC CONG CO BAN TRONG VERILOG
Cac cong logic c s la mot bo phan cua ngon ng Verilog. Co hai ac tnh c ch ro la: drive_strenght va delay. Drive_strenght ch sc ben cua cong. o ben ngo ra la s ket noi mot chieu en nguon, ke o tao nen s ket noi trong suot trans dan, ket thuc la tong tr keo len hoac xuong. Drive_strenght thng khong c ch ro, trong trng hp nay o ben mac nh la strong1 va strong0 . Delay: neu delay khong c ch ro, th khi o cong khong co tr hoan truyen tai; neu co hai delay c ch nh, th trc tien la mieu ta tr hoan len, th hai la tr hoan xuong. Neu ch co mot delay c ch nh, th khi o tr hoan len xuong la nh nhau. Delay c bo qua trong tong hp. Phng phap cua s tr hoan ch nh nay la mot trng hp ac biet cua Parameterized Modules. Cac tham so cho cac cong c s phai c nh ngha trc nh delay. I. Cac cong c ban: Cac cong c ban co mot ngo ra, va co mot hoac nhieu ngo vao. Trong cac cong, cu phap cu the bieu dien ben di, cac t khoa cua cac cong: and, or, nand, nor. 1. Cu phap: GATE (drive_strength)#(delays) Ten t khoa cong _ten (output, input_1, input_2, , input_N); Delay: #( len, xuong) hoac #len_va_xuong hoac #( len_va_xuong) 2. V du: And c1 (o, a, b, c. d); // co 4 ngo vao cong And goi la c1 c2 (p, f, g); // va 2 ngo vao cong and goi la c2 Or #(4,3) ig ( o, b, c); // cong Or c goi la ig, rise time = 4, fall time = 3 Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 5 Xor #(5) xor1 (a, b, c); // sau 5 n v thi gian th a = b xor c II. Cong buf, not: Cac cong nay thc thi em va ao theo theo th t mh san. Chung co mot ngo vao, hai hay nhieu ngo ra. Cu phap cu the bieu dien ben di, t khoa buf, not. 1. Cu phap: Ten t khoa cong _ten (output_1, output_2, , output_N, input); 2. V du: Not #(5) not_1( a,c); // sau 5 n v thi gian th a = ao c Buf c1 (o, p, q, r, in); // bo em 5 ngo ra va 2 ngo ra c2 (p, f, g); Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 6 Chuong IV CAC DANG DU LIEU
I. at gia tr: Verilog bao gom 4 gia tr c ban. Hau het cac dang d lieu Verilog cha cac gia tr sau: 0: mc logic 0, hoac ieu kien sai. 1: mc logic 1, hoac ieu kien ung. X: mc logic tuy nh Z: trang thai tong tr cao. X va Z dung co gii han trong tong hp (synthesis) II. Wire: Mo ta vat lieu ng day dan trong mot mach ien va c dung e ket noi cac cong hay cac module. Gia tr cua Wire co the oc, nhng khong c gan trong ham (function) hoac khoi (block). Wire khong lu tr gia tr cua no nhng van phai c thc thi bi 1 lenh gan ke tiep hay bi s ket noi Wire vi ngo ra cua 1 cong hoac 1 module. Nhng dang ac biet khac cua Wire: Wand(wired_and): gia tr phu thuoc vao mc logic And toan bo bo ieu khien ket noi en Wire. Wor (wired_or): gia tr phu thuoc vao mc logic Or toan bo bo ieu khien ket noi en Wire. Tri(three_state): tat ca bo ieu khien ket noi en 1 tri phai trang thai tong tr cao. 1. Cu phap: Wire [msb:lsb] ten bien wire. Wand [msb:lsb] ten bien wand. Wor [msb:lsb] ten bien wor. Tri [msb:lsb] ten bien tri. 2. V du: Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 7 Wire c; Wand d; Assign d= a; Assign d= b;// gia tr d la mc logic cua phep And a va b. Wire [9:0] A; // vect A co 10 wire. III. Reg: Reg (register) la mot oi tng d lieu ma no cha gia tr t mot thu tuc gan ke tiep. Chung ch c dung trong ham va khoi thu tuc. Reg la mot loai bien Verilog va khong nhat thiet la thanh ghi t nhien. Trong thanh ghi nhieu bit, data c lu tr bang nhng ch so khong dau va khong co k hieu uoi m rong, c thc hien ma ngi s dung co chu y la so bu hai. 1. Cu phap: Reg [msb:lsb] ten bien reg. 2. V du: Reg a; // bien thanh ghi n gian 1 bit. Reg [7:0] A; // mot vect 8 bit; mot bank cua 8 thanh ghi. Reg [5:0]b, c; // hai bien thanh ghi 6 bit. IV. Input, Output, Inout: Nhng t khoa nay bieu th ngo vao, ngo ra, va port hai chieu cua mot module hoac task. Mot port ngo ra co the c cau hnh t cac dang: wire, reg, wand, wor, hoac tri. Mac nh la wire. 1. Cu phap: Input [msb:lsb] port ngo vao. Output [msb:lsb] port ngo ra. Inout [msb:lsb] port ngo vao,ra hai chieu. 2. V du: Module sample (b, e, c, a); Input a; // mot ngo vao mac nh la kieu wire. Output b, e; // hai ngo ra mac nh la kieu wire. Output [1:0] c; /* ngo ra hai bit, phai c khai baotrong mot lenh rieng*/ Reg [1:0] c; // ngo c c khai bao nh mot reg. Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 8 V. Integer (So nguyen): Integer la mot bien a nang. Trong tong hp chung c dung chu yeu cho vong lap, tham so, va hang so. Chung hoan toan la reg. Tuy nhieu chung cha d lieu bang nhng so co dau, trong khi o khai bao dang reg cha chung bang so khong dau. Neu chung cha nhng so ma khong nh ngha thi gian bien dch th kch thc mac nh la 32 bit. Neu chung cha hang, s tong hp ieu chnh cac so co kch thc nho nhat can thiet cho s bien dch. 1. Cu phap: Integer ten bien nguyen; ten hang nguyen; 2. V du: Integer a; // so nguyen n gian 32bit. Assign b= 63; // mac nh la mot bien 7 bit. VI. Supply 0, Supply1: Xac nh cho ng dan len mc logic 0 ( at), logic 1( nguon) theo th t nh san. VII. Time: Time la mot lng 64 bit ma c s dung cung vi $time, he thong thao tac cha lng thi gian mo phong. Time khong c ho tr tong hp va v the ch c dung trong muc ch mo phong. 1. Cu phap: Time bien time; 2. V du: Time c; c = $time; // c = thi gian mo phong dong ien. VIII. Parameter (Tham so): Mot Parameter xac nh 1 hang so ma c at khi ban cho v du cu the la mot module. Cac nay cho phep ta co the sa cha. 1. Cu phap: Parameter par_1= gai tr, par_2= gai tr, ; Parameter [gii han] par_3 = gia tr; 2. V du: Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 9 Parameter add = 2b00, sub = 3b111; Parameter n = 4; Parameter [3:0] par_2 = 4b1010;
reg [n-1:0] harry;// mot thanh ghi 4 bt ma o rong c at bi tham so n tren. always @(x) y = {{(add - sub) {x}}} if (x) begin state = par_2[1]; else state =par_2[2]; end. Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 10 ChuongV TOAN TU
I. Toan t so hoc: Nhng toan t nay thc hien cac phep tnh so hoc. Dau + va - co the c s dung mot trong hai toan t n (-z) hoac kep (x - y). 1. Toan t: +, -, *,
/, %. 2. V du: parameter n = 4; Reg[3:0] a, c, f, g, count; f= a +c; g= c n; count = (count +1) % 16; // co the em t 0 en 15. II. Toan t quan he: Toan t quan he so sanh hai toan hang va tra ve mot n bit la 0 hoac 1. Nhng toan t nay tong hp vao dung cu so sanh. Bien Wire va Reg la nhng bien dng. V the, (-3b001) = (3b111) va (-3b001) > ( 3b110) nhng neu la so nguyen th -1< 6. 1. Cac toan t quan he: <, <=, >, >=, = =, !=. 2. V du: If (x= =y) e =1; Else e= 0; // so sanh hai vector a, b reg [3:0] a, b; if (a[3] = =b [3]) a[2:0] >b[2:0]; else b[3]; Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 11 III. Toan t bit_wire: So sanh tng bit hai toan toan hang. 1. Cac toan t: ~ (bitwire NOT), & (bitwire AND), | (bitwire OR), ^ (bitwire XOR), ~^ hoac ^~ (bitwire XNOR). 2. V du: Module and2(a, b, c); Input [1:0] a, b; Output [1:0] c; Assign c = a & b; Endmodule IV. Toan t logic: Toan t logic tra ve 1 bit n 0 hoac 1. chung giong nh toan t bitwire ch la nhng toan hang n bit. Chung co the lam viec tren bieu thc, so nguyen hoac nhom bit, va coi nhu tat ca cac gia tr khong bang 0 la 1. Toan t logic c dung nhieu trong lenh ieu kien (if else), khi chung lam viec tren bieu thc. 1. Toan t: !(NOT), && (AND), || (OR) 2. V du: Wire [7:0] x, y, z; Reg a;
if ((x= = y)&&(z)) a=1; else a=! x; V. Toan t bien oi: Co tac dung tren tat ca cac bit cua mot vect toan hang va tra ve gia tr n bit. Nhng toan t nay la hnh thc t oi so cua cac toan t bitwire tren. 1. Cac toan t: ~ (bien oi NOT), & (bien oi AND), ~&( bien oi NAND), | (bien oi OR), ~| (bien oi NOR), ^ (bien oi XOR), ~^ hoac ^~ (bien oi XNOR). 2. V du: Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 12 Module chk_zero (a,z); Input [2:0] a; Output z; Assign z = ~| a; Endmodule VI. Toan t ghep: Dch toan t au bang ch so cua cac bit c nh ngha bi toan t thou hai. V tr con trong se c ien vao vi nhng so 0 cho ca hai trng hp dch trai hoac phai. 1. Toan t: << ( dch trai), >> (dch phai). 2. V du: assign c = a<<2; c = a dch trai 2 bit cac cho trong c ien vi nhng so 0. VII. Toan t dch: Ghep hai hoac nhieu toan hang thanh mot vect ln. 1. Toan t: {} (concatenation) 2. V du: Wire [1:0] a, b; Wire [2:0] x; Wire [3:0] y, Z; Assign x = {1b0, a}; // x[2] = 0, x[1] = a[1], x[0] = a[0]. Assign y = {a, b}; // y[3]= a[1], y[2] = a[0], y[1] = b[1], y[0] = b[0]. VIII. Toan t th ban: Tao ra nhieu ban sao cua mot muc chon. 1. Toan t: {n{ muc chon }} n nhom th ban trong mot muc chon. 2. V du: Wire [1:0] a, b; Wire [3:0] x; Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 13 Assign x = {2{1b0},a}; // x= {0, 0, a}. IX. Toan t ieu kien: Giong nh C/C ++ . Chung nh gia mot trong hai bieu thc c ban trong mot ieu kien. No se tong hp thanh bo a cong (MUX). 1. Toan t : (ieu kien)? ket qua khi ieu kien ung : ket qua khi ieu kien sai. 2. V du: assign a = (g) ? x : y; Assign a = ( inc = =2) ? a+1: a-1; X. Th t toan t: Nhng toan t trong mc giong nhau nh gia t trai sang phai Toan t Ten [ ] Chon bit, chon phan ( ) Phan trong ngoac n !, ~ Mc logic va bit_wire NOT &, |, ~&, ~|, ^, ~^ Bien oi: AND, OR, NAND, NOT, XOR, XNOR. +, - Dau ch so am so dng. { } Ghep noi { 3b101,3b110} = 6b101110 {{ } } Th ban {3{3b101 } }=9b101101101 *, /, % Nhan, chia, phan tram. +, - Cong tr nh phan. <<, >> Dch trai, phai. <, <=, >, >= Dau so sanh. Bien Reg va wire c lay bang nhng so dng. = =, != Bang va khong bang trong toan t logic. & Bit_wire AND, and tat ca cac bit vi nhau. ^, ~^ Bit_wire XOR, Bit_wire XNOR. | Bit_wire OR. &&, || Toan t logic AND, OR. ?: x = ( ieu kien ) T:F Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 14 Chuong VI TOAN HANG
I. Literals (dang k t): La toan hang co gia tr khong oi ma c dung trong bieu thc Verilog. Co hai dang k t la: Chuoi: la mot mang co nhieu k t c at trong dau . Ch so: la nhng so khong oi, nh phan, bat phan, thap phan, hoac so hex. 1. Cu phap cac ch so: nF dddd Trong o: n : so nguyen mieu ta so bit. F: mot trong bon nh dang sau: b( so nh phan), o( so bat phan), d( so thap phan), h( so hex). 2. V du: time is// chuoi k t. 267 // mac nh 32 bit so thap phan. 2b01 // 2 bit nh phan. 20h B36E // 20 bit so hex. o62 // 32 bit bat phan. II. Chon 1 phan t bit va chon 1 phan cac bit. ay la s la chon mot bt n hoac mot nhom bit theo th t, t mot wire, reg hoac t tham so at trong ngoac [ ]. Chon 1 phan t bit va chon 1 phan cac bit co the c dung nh la cac toan hang trong bieu thc bang nhieu cach thc giong nhau ma cac oi tng d lieu goc c dung. 1. Cu phap: Ten bien [ th t bit]. Ten bien [ msb: lsb]. 2. V du: Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 15 Reg [7:0] a, b; Reg [3:0] ls; c = a[7] & b[7]; ls = a[7:4] + b[3:0]; III. Goi ham chc nang: Gia tr tra ve cua mot ham co the c dung trc tiep trong bieu thc ma khong can gan trc cho bien reg hoac wire. Goi ham chc nang nh la mot trong nhng toan hang. Chieu rong bt cua gia tr tra ve chac chan c biet trc. 1. Cu phap: Ten ham(danh sach bien). 2. V du: Assign a = b & c & chk_bc(b, c); Function chk_bc; Input c, b; Chk_bc = b^ c; Endfunction IV. Wire, reg, va tham so: Wire, reg, va tham so co the uc dung nh la cac toan hang trong bieu thc Verilog. Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 16 Chuong VII MODULES
I. Khai bao modules: Mot module la ban thiet ke chu yeu ton tai trong Verilog. Dong au tien cua khai bao module ch ro danh sach ten va port (cac oi so). Nhng dong ke tiep ch ro dang I/O (input, output, hoac inout) va chieu rong cua moi port. Mac nh chieu rong port la 1 bit. Sau o, nhng bien port phai c khai bao wire, wand, , reg. Mac nh la wire. Nhng ngo vao ac trng la wire khi d lieu c chot bean ngoai module. Cac ngo ra la dang reg neu nhng tn hieu cua chung c cha trong khoi always hoac initial. 1. Cu phap: Module ten module (danh sach port); Input [msb:lsb] danh sach port ngo vao; Output [msb:lsb] danh sach port ngo ra; Inout [ msb:lsb ] danh sach port vao_ ra; cac lenh endmodule 2. V du: Module add_sub(add, in1, in2, out); Wire, reg, va tham so: Input[7:0 ] in1, in2; Wire in1, in2; Output [7:0] out; Reg out; cac lenh khac Endmodule
Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 17 II. Ch nh lien tiep: Cac ch nh lien tiep c dung e gan mot gia tr len tren mot wire trong mot module. o la cac ch nh thong thng ben ngoai khoi always hoac khoi initial. Cac ch nh lien tiep c thc hien vi mot lenh gan (assign) ro rang hoac bang s ch nh mot gia tr en mot wire trong luc khai bao. Chu y rang, cac lenh ch nh lien tiep th ton tai va c chay lien tuc trong suot qua trnh mo phong. Th t cac lenh gan khong quan trong. Moi thay oi ben phai cua bat c ngo vao se lap tc thay oi ben trai cua cac ngo ra. 1. Cu phap: Wire bien wire = gia tr; Assign bien wire = bieu thc; 2. V du: Wire [ 1:0 ] a = 2b 01; Assign b = c &d; Assign d = x | y; III. Module instantiations: Nhng khai bao module la nhng khuon mau ma no c tao nen t cac oi tng thc te ( instantiation). Cac module n c ben trong cac module khac, va moi dan chng tao mot oi tng oc nhat t khuon mau. Ngoai tr o la module mc tren la nhng dan chng t chnh chung. Cac port cua module v du phai thoa nhng dnh ngha trong khuon mau. ay la mat ly thuyet: bang ten, s dung dau cham(.) .ten port khuon mau ( ten cua wire ket noi en port). Bang v tr, at nhng port nhng v tr giong nhau trong danh sach port cua ca khuon mau lan instance. 1. Cu phap: Ten instance1 (danh sach ket noi port ); Ten instance2(danh sach ket noi port);
2. V du: // nh ngha module module and4(a,b,c); input [3:0]a,b; output [3:0]c; Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 18 assign c = a&b; endmodule // module instantiations wire [3:0] in1, in2; wire [3:0] o1, o2; // at v tr and4 C1(in1, in2,o1); // ten and4 C2(.c(o2), .a(in1), .b(in2)); Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 19 Chuong VIII KHUON MAU HANH VI (BEHAVIORALJ
Verilog co 4 mc khuon mau: Chuyen mach. Khong c e cap en ay. Cong. Mc tran d lieu. Hanh vi hoac thu tuc c e cap ben di Cac lenh thu tuc Verilog c dung tao mot mau thiet ke mc cao hn. Chung ch ra nhng cach thc manh cua vec lam ra nhng thiet ke phc tap. Tuy nhien, nhng thay oi nho n phng phap ma hoa co the gay ra bien oi ln trong phan cng. Cac lenh thu tuc ch co the c dung trong nhng thu tuc. I. Nhng ch nh theo thu tuc: La nhng ch nh dung trong pham vi thu tuc Verilog (khoi always va initial). Ch bien reg va integers (va chon n bit/ nhom bit cua chung, va ket noi thong tin) co the c at ben trai dau = trong thu tuc. Ben phai cua ch nh la mot bieu thc ma co the dung bat c dang toan t nao. II. Delay trong ch nh: Trong ch nh tre t la khoang thi gian trai qua trc khi mot lenh c thc thi va ben trai lenh gan c tao ra. Vi nhieu ch nh tre (intra-assignment delay), ben phai c nh gia tr trc tiep nhng co mot delay cua t trc khi ket qua c at ben trai lenh gan. Neu them mot qua trnh thay oi na canh ben phai tn hieu trong khoang thi gian t,th khong cho ket qua ngo ra. Delay khong c ho tr bi cac cong cu. 1. Cu phap ch nh thu tuc: Bien = bieu thc; Ch dnh tre: Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 20 #t bien = bieu thc; intra_assignment delay: bien = #t bieu thc. 2. V du: Reg [6:0] sum; reg h, zilch; Sum[7] = b[7]^c[7]; // thc thi tc thi; Ziltch = #15 ckz & h; // ckz & h nh gia tr tc thi; ziltch thay oi sau 15 n v thi gian. #10 hat = b & c;/* 10 n v thi gian sau khi ziltch thay oi, b & c c nh gia va hat thay oi*/ III. Ch nh khoi: Ch nh khoi (=) thc hien lien tuc trong th t lenh a c viet. Ch nh th hai khong c thc thi neu nh ch nh au cho hoan thanh. 1. Cu phap: Bien = bieu thc; Bien = #t bieu thc; #t bien = bieu thc; 2. V du: Initial Begin a = 1; b = 2; c = 3; #5 a = b + c; // sau 5 n v thi gian thc hien a = b + c = 5. d = a; // d = a = 5. Always @(posedge clk) Begin Z = Y; Y = X; // thanh ghi dch. y = x; z = y; // flip flop song song. IV. Begin end: Lenh khoi begin end c dung e nhom mot vai lenh ma mot lenh cu phap c cho phep. Bao gom function, khoi always va khoi initial. Nhng khoi nay co the c tuy y goi ten. Va bao gom khai bao reg, integer, tham so. Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 21 1. Cu phap: Begin: ten khoi Reg[msb:lsb] danh sach bien reg; Integer [msb:lsb] danh sach integer; Parameter [msb:lsb] danh sach tham so; cac lenh End 2. V du: function trivial_one;// ten khoi la: trivial_one input a; begin: adder_blk integer i; lenh end V. Vong lap for: Giong nh c/c ++ c dung e thc hien nhieu lan mot lenh hoac khoi lenh. Neu trong vong lap ch cha mot lenh th khoi begin end co the bo qua. 1. Cu phap: For (bien em = gia tr 1; bien em </ <=/ >/ >= gia tr 2; bien em = bien em +/- gia tr) begin lenh end 2. V du: For (j = 0; j<=7; j = j+1) Begin c[j] = a[j] & b[j]; d[j] = a[j] | b[j]; end VI. Vong lap while: Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 22 Vong lap while thc hien nhieu lan mot lenh hoac khoi lenh cho en khi bieu thc trong lenh while nh gia la sai. 1. Cu phap: While (bieu thc) Begin cac lenh end 2. V du: While (!overflow) @(posedge clk); a = a +1; end VII. Khoi lenh if else if else: Thc hien mot lenh hoac mot khoi lenh phu thuoc vao ket qua cua bieu thc theo sau menh e if. Cu phap If (bieu thc) Begin cac lenh end else if (bieu thc) Begin cac lenh end else Begin cac lenh end VIII. Case: Lenh case cho phep la chon trng hp. Cac leng trong khoi default thc thi khi khong co trng hp la chon so sanh giong nhau. Neu khong co s so Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 23 sanh, bao gom ca default, la ung, s tong hp se tao ra chot khong mong muon. 1. Cu phap: Case (bieu thc) Case 1: Begin cac lenh end Case 2: Begin cac lenh end Case 3: Begin cac lenh end
default: begin cac lenh end endcase 2. V du: Case (alu_clk) 2b00: aluout = a + b; 2b01: aluout = a - b; 2b10: aluout = a & b; default: aluout = 1bx; endcase Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 24 Chuong IX KHOI ALWAYS VA KHOI INITIAL
I. Khoi always: La cau truc chn trong khuon mau RTL (Register Transfer Level). Giong ch nh lien tuc, ay la trang thai ton tai ma c thc thi lien tuc trong khi mo phong. Cai nay cung co ngha la tat ca cac khoi always trong mot module thc thi mot cach lien tuc. Khoi always co the c dung trong chot, flip flop hay cac ket noi logic. Neu cac lenh cua khoi always nam trong pham vi khoi begin end th c thc thi lien tuc, neu nam trong khoi fort join, chung c thc thi ong thi (ch trong mo phong). Khoi always thc hien bang mc, canh len hoac canh xuong cua mot hay nhieu tn hieu (cac tn hieu cach nhau bi t khoa OR). Cu phap: Always @(s kien 1 or s kien 2 or) Begin cac lenh end Always @(s kien 1 or s kien 2 or) Begin: ten khoi cac lenh end II. Khoi initial Giong nh khoi always nhng khoi initial ch thc thi mot lan t luc bat d8au cua qua trnh mo phong. Khoi nay th tieu bieu e bien khi chay va ch nh dang song tn hieu trong luc mo phong. Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 25 1. Cu phap: Initial Begin cac lenh end 2. V du: Initial Begin Clr = 0; Clk = 1; End Initial Begin a = 2b00; #50 a = 2b01; #50 a = 2b10; end Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 26 Chuong X HAM
Ham c khai bao trong pham vi mot module, va co the c goi t nhng lenh lien tuc, khoi always, hoac nhng ham khac. Trong lenh ch nh lien tuc, cung c ch nh lien tuc khi bat k cac ham khai bao ngo vao thay oi. Trong chng trinh chung c ch dng ti khi can goi. Cac ham mo ta s ket noi logic, va khong tao ra chot. Do o mot lenh if ma khong else se mo phong , mac du no co chot d lieu nhng mo phong th khong co. ay la trng hp d cua tong hp khong co mo phong theo sau. ay la khai niem tot e ma hoa ham, v vay chung se khong tao ra chot neu ma ham c dung trong mot chng trnh. I. Khai bao ham: Khai bao ham la ch ra ten ham, chieu rong cua ham gia tr tra ve, oi so ham d lieu vao, cac bien (reg) dung trong ham, va tham so cuc bo cua ham, so nguyen cua ham. 1. Cu phap: Function [msb:lsb] ten ham; Input [msb:lsb]bien vao; Reg [msb:lsb]bien reg; Parameter [msb:lsb] tham so; Integer [msb:lsb] so nguyen; cac lenh endfunction 2. V du Function [7:0] my_func; // ham tra ve gia tr 8 bit Input [7:0] i; Reg [4:0] temp; Integer n; Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 27 temp = i[7:4]| (i[3:0]); my_func = {temp,i[1:0]}; endfunction II. V du: Mot ham ch co cha mot d lieu ra. Neu co nhieu hn mot gia tr tra ve c yeu cau, ngo ra se phai ket noi tao thanh mot vector trc khi at gia tr cho ham e goi ten ham. Goi ten chng trnh module co the trch ra sau o, rieng oi vi ngo ra t cac bieu mau noi vao nhau. V du di ay minh hoa tong quat cach dung va cu phap ham trong verilog. 1. Cu phap: Ten ham = bieu thc. 2. V du: Module simple_processor (instruction, outp); Input [31:0] instruction; Output [7:0] outp; Reg [7:0] outp;// co the c gan trong khoi always. Reg func; Reg [7:0] opr1, opr2; Function[16:0] decode add(instr) Input [31:0] instr; Reg add_func; Reg [7:0] opcode, opr1, opr2; Begin Opcode = instr[31:24]; Opr1 = instr[7:0]; Case (opcode) 8b 10001000: begin add_func = 1; opr2 = instr[15:8]; end Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 28 8b 10001001: begin add_func = 0; opr2 = instr[15:8]; end 8b 10001010: begin add_func = 1; opr2 = 8b 00000001; end default: begin add_func = 0; opr2 = 8b00000001; end endcase decode_add = {add_func, opr2, opr1}; end endfunction always @(intruction) begin {func, opr2, opr1}= decode_add (intruction); if (func= =1) outp = opr1+ opr2; else outp = opr1 opr2; end endmodule Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 29 Chuong XI CHUC NANG LINH KIEN
Chot d lieu (latches): c suy neu mot bien, mot trong cac bit khong c gan trong cac nhanh cua mot lenh if. Chot d lieu cung c suy ra t lenh case neu mot bien c gan ch trong mot vai nhanh. Hoan thien ma co the oc c dung lenh if e tong hp chot v that kho e ch nh ro rang. Theo ly thuyet, mot s xac lap hp l nen c suy ra t ma Verilog. Cu phap: If else if else va case. I. Thanh ghi Edge_triggered, flip_flop, bo em: Mot thanh ghi (flip_flop) c suy luan bang viec dung xung kch canh len hoac xuong trong danh sach s kien cua lenh khoi always. Cu phap: Always @(posedge clk or posedge reset1 or nesedge reset2) Begin If (reset1) begin Cac ch nh reset end else if (reset2) begin Cac ch nh reset End Else begin Cac ch nh reset End II. Bo a cong: c suy ra bi viec gan mot bien ma gia tr moi bien khac nhau trong moi nhanh cua lenh if hoac case. Co the tranh cac ch nh va moi nhanh co the Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 30 ton tai bang viec s dung ngoai nhng nhanh mac nh. Chu y rang chot se c tao ra neu mot bien khong c gan cho cac ieu kien nhanh co the ton tai. e hoan thien ma co the oc c, dung lenh case e tao mau a cong ln. III. Bo cong, tr: Toan t cong tr trong bo cong tr ma co chieu rong phu thuoc vao chieu rog cua toan t ln hn. IV. Bo em 3 trang thai: Bo em ba trang thai c suy ra neu bien c gan theo ieu kien gia tr tong tr cao Z dung mot trong cac toan t: if, case, V. Cac linh kien khac: Hau het cac cong logic c suy ra t viec dung nhng toan hang tng ng cua chung. Nh mot s la chon mot cong hoac mot thanh phan co the c giai thch ro rang bang v du cu the va s dung cac cong c s (and, or, nor, inv) mien la bang ngon ng Verilog. Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 31 Chuong XII MOT SO V DU
I. Cau truc mot chng trnh dung ngon ng Verilog:
// Khai bao module Module ten chng trnh (ten bien I/O); // ten chng trnh trung ten file.v. Input [msb:lsb] bien; Output [msb:lsb] bien;
Reg [msb:lsb] bien reg; Wire [msb: lsb] bien wire;
// Khai bao khoi always, hoac khoi initial. cac lenh
Endmodule
II. Mot so v du: Phan men ho tr: MAX+plusII 10.0 BASELINE 1. V du 1: a. Chng trnh tnh NOR cac bit cua bien vao
module vdcong(in,out); input[3:0] in; output out;
assign out= ~|in;
endmodule
Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 32 b. Mo phong
case(w) 2'b00: y<=4'b1000; 2'b01: y<=4'b0100; 2'b10: y<=4'b0010; default:y<=4'b0001; Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 34
wire [3:0] bcd; Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 37 reg [7:0] led;
always @(bcd)
begin case(bcd) 4'b0000: led = 8'b00000011; 4'b0001: led = 8'b10011111; 4'b0010: led = 8'b00100101; 4'b0011: led = 8'b00001101; 4'b0100: led = 8'b10011001; 4'b0101: led = 8'b01001001; 4'b0110: led = 8'b01000001; 4'b0111: led = 8'b00011111; 4'b1000: led = 8'b00000001; 4'b1001: led = 8'b00001001; default: led = 8'b00000000; endcase
end
endmodule
b. Mo phong
Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 38 7. V du 7: a. Chng trnh giam t 9 xuong 0, hien th ra led 7 oan
always @(posedge clock ) begin if (rst == 1'b1) bcd <= 4'b1001; else if (s1 == 1'b1) bcd <= bcd - 1'b1; if (bcd == 4'b0) bcd <= 4'b1001; end
always @(posedge clock) begin case(bcd) 4'b0000: led = 8'b11111100; 4'b0001: led = 8'b01100000; 4'b0010: led = 8'b11011010; 4'b0011: led = 8'b11110010; 4'b0100: led = 8'b01100110; 4'b0101: led = 8'b10110110; 4'b0110: led = 8'b10111110; 4'b0111: led = 8'b11100000; 4'b1000: led = 8'b11111110; 4'b1001: led = 8'b11100110; default: led = 8'b11111111; endcase
end
endmodule Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 39 b. Mo phong
8. V du 8: a. Chng trnh tang t 0 en 9, hien th ra led 7 oan
always @(posedge clock ) begin if (rst == 1'b1) bcd <= 4'b0; else if (s1 == 1'b1) bcd <= bcd + 1'b1; if (bcd == 4'b1001) bcd <= 4'b0000; end
Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 40 always @(posedge clock) begin case(bcd) 4'b0000: led = 8'b11111100; 4'b0001: led = 8'b01100000; 4'b0010: led = 8'b11011010; 4'b0011: led = 8'b11110010; 4'b0100: led = 8'b01100110; 4'b0101: led = 8'b10110110; 4'b0110: led = 8'b10111110; 4'b0111: led = 8'b11100000; 4'b1000: led = 8'b11111110; 4'b1001: led = 8'b11100110; default: led = 8'b11111111; endcase
end
endmodule
b. Mo phong
Tom tat bai giang TK He Thong So Phan Verilog GV: Nguyen Trong Hai Trang 41
TAI LIEU THAM KHAO
1. Verilog Digital System Design Zainalabedin Navadi Northeastern University University of Tehran 2. Introduction of Verilog Peter M. Nyasulu 3. Cadence Verilog XL Reference Manual 4. Synopsys HDL Compiler for Verilog Reference Manual 5. Diglab 10K10 Mannual