POWER RECTIFIER ASIC CONTROLLER

M.G. Giamusi, M.N. Cirstea, M. McCormick

De Montfort UniversiQ, Department o f Electronic & Electrical Engineering, Queens Building, The Gateway, Leicester, LE1 9BH, UK.
ABSTRACT This paper presents the Application Specific Integrated Circuit (ASIC) implementation of an accurate digtal control for the three phase six pulse controlled rectlfiers, which was achleved using Electronic Design ,4utomation (EDA) techniques. The controller was simulated and then implemented into two Field Programmable Gate Arrays (FPGAs). The complete three phase six pulse rectfier system including the ASIC controller, the zero-crossing detector and an iinterface/pulse shaping circuit was commissioned. The experimental results show that the proposed scheme gives a good performance of the three phase controlled reczifier system. Keywords: ASIC, P G A , Computer Aided Design. INTRODUCTION

Controller, RecMier,

The use of EDA techniques allows the dgital design engneer to create, simulate and vex@ a design without the need to breadboard a prototype, allowing complex systems and ideas to be evaluated in a short period of time, giving an extremely high confidence in the final product before committing to experimental hardware. With the constantly declining cost of very large scale integrat.ion (VLSI) ICs, the use of powerful ASICs as controllers for power Electronic Converters [1],[2] has become more and more popular. The ASIC improves the flexibility and the reliability of the controller. Moreover, a single-chip ASIC can implement the controller with lower cost and smaller size than the general-purpose microprocessor or a microcontroller. The six pulse phase-controlled rectifier is one of the most widely used solid-state converters. Many scientific papers have dealt with the microprocessorbased digital control of the three phase six pulse rectifier over the last decades [3]-[6]. Microprocessors were used to control the firing of the bridge elements. These methods, however, enlarge the memory size and require software to' be developed in parallel with the hardware. Thls paper describes an alternative of using a novel ASIC-based direct digital controller instead of microprocessors. The control ASIC was simulated and then implemented into two XILINX FPGAs.

For a three-phase six-pulse power rectifier, six pulses need to be provided by a zero crossing detector to perform the synchronisation of the control system (firing pulses for the thyristors) with the power voltages. Several works have been published concerning this subject [7]-[9]. A microprocessor based synchronisationalgorithm was used by Gerson H. P. [7] who acheved good detection results in the presence of distortions caused by the commutation of the rectifier elements. A simple control method is proposed in [8] for six pulse low power transistor rectfiers. In [9] a synchronisation method for thyristor power converters applied to weak ac-systems was proposed. The high performance and resolution of the zero crossing detectors mentioned above is achieved at the expense of the complexity in hardware andor software. This paper also describes the practical implementation of a new zero crossing detection circuit for the six line-to-line power voltages, which eliminates the use of transformers and performs a good galvanic isolation in conjunctionwith a hlgh noise immunity. The complete system block diagram, including the power rectifier, is illustrated in Figure 1.

1 bR&:
~

INTERFACE CIRCUIT

ETECToR
1

ASIC CONTROLLER
I

Figure 1: Complete System Block Diagram

THE ASIC CONTROLLER

The ASIC controller of the three phase six pulse rectifier consists mainly of two FPGAs: One is called the Synchro Emulator (SE), the other is called the Counter Comparator Pulse Ampllfier (CCPA). In

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addition there are two booting memories and some auxiliary circuits such as the 1 M H z TTL square wave generator, a seven bit switch, seven monitoring LEDs and others. Figure 2 illustrates the circuit of the complete ASIC controller

This fimction eliminates the use of an external phase locked loop, which would normally be used for correct synchronisation and measurement of the delay firing angle.

Figure 3: Synchro-EmulatorCircuit

Counter Comparator Pulse Amplifier (CCPA)

Figure 2: Complete ASIC Controller Circuit Diagram

Synchro Emulator (SE)

The first function of the control system is performed by the synchro emulator circuit (Figure 3). This FPGA generates the digital sampling frequency of 25.6 KHz, which is used as clock for generating the firing pulses for each thyristor. The synchro emulator also provides six signals representing the zero-crossing pulses. These pulses can be generated internally within the synchro emulator or delivered by the real zero crossing pulses produced from the three phase supply (zero-crossing of the line to line voltages). Using internal generated zero crossing pulses has an advantage when testing the control ASIC and enables the controller board to be commissioned without connection to the three phase supply ([1],[2]). A new selector/synchroniser digital module has been incorporated into the synchro emulator, which gives the synchro emulator the ability to be self phase locked to the supply voltages via the real zero crossing pulses.

The second P G A of the control system is the Counter Comparator Pulse Ampldier (CCPA) whch consists of six firing modules. The main function of this P G A is to generate 6 sets of firing pulses, one for each of the thyristors in the power converter, in the appropriate firing sequence required by a 6-pulse bridge configuration of the recbfier. Each of the six modules shown in Figure 4 provides two groups of 16 firing pulses to the correspndmg thyristor via an addtional interface and pulse shaping circuit.

Figure 4: One Firing Module Circuit

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Figure 5 shows the complete Circuit diagram for the CCPA. Figure 6 shows the correct simulation results for two cl~annels,with a firing delay of 4.9" which is equivalent to 7 clock pulses (07 Hex). The real output signals obtained from the ASIC controller are shown in Figure 7. The advantage of using the selector/synchroniser module is demonstrated. CH 1 represents the real zero crossing pulse for thyristor number 1, CH2 represents the synchronised zero crossing pulse after being applied to the selector/synchroniser module, CH3 illustrates the sampling frequency clock and CH4 represents the generated firing pulses corresponding to a delay of 7 clock pulses. This design was performed using hierarchcal design and partitioning techniques using the XLLINX XC3000 library, then simulated using VIEWlogic software (Viewsim) and implemented into two XDLINX FPGAs.
Figure 5: Counter Comparator Pulse Amplifier Circuit

Figure 6: Simulation of Firing Pulses on Two Output Channels

CH

CH

C H

CH

Figure 7: Real Firing Pulses Generation with the advantage of using Selector/Synchroniser

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THE ZERO CROSSING DETECTOR

A new circuit design was investigated for detecting the negative to positive zero crossing of the six line-to-line voltages of a 3-phase system. It avoids the use of transformers on the input side, using instead high ohmic resistance to provide the voltage level requested by the ICs. The present circuit schematic illustrated in Figure 8 uses three TCA785 Siemens Integrated Circuits (ICs), which can be supplied from the 3 phase power system. They provide separate adjustment over a wide range (20'-160) of the delay of the zero crossing pulses from real zero crossing instances. The three input phase-to-neutral voltages are detected, allowing a very precise adjustment of the line-to-line voltages with a 90' phase shift. The circuit performs galvanic

isolation by using six Schmidt-trigger optoisolators with hysteresis (411L1) on each output channel, providing a high noise immunity. This version of the zero crossing circuit proved to be more reliable than other versions tested and less sensitive to noise interference. The width of each zero crossing pulse generated by the Siemens TCA785 circuit is about 100psec which is convenient as an input for the ASIC controller (the pulses provided by the synchro-emulator for simulation and testing are 78 psec wide, therefore they are in the same width range). The pulses generated by the TCA785 are then bufered through optoisolators and inverting buffers, which improves the shape and filters the noise. These are the pulses which are fed into the control ASIC to activate the firing pulses. Figure 9 show the generated zero crossing pulses for thyristor number 1 in the rectifier bridge

Figure 8: The Zero-Crossing Detector Circuit Diagram

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CONCLUSIONS

This paper presents an original design of an ASIC controller for three phase six pulse rectifier systems (figure 2). The direct dlgital control of the bridge rectifier was implemented with a minimal control hardware sitructure using Xilinx (XC3042PC84) low-cost FPGAs, with high confidence of the system working correctly right first time. The controller was developed from an idea, through the design and simulation stages, to the complete manufactured system in a very short timc. The proposed controller gives a good overall performance to the rectifier system using thyristors. The main achievements of t h s system are: a) A 6-pulse synchro-emulator was designed and implemented as part of the control ASIC, allowing easy simulation and testing of the system, without connection to the tluee phase supply. b) The incorporiition of the selectorhynchroniser module inside the synchro emulator, give two advantages. First, it eliminates the use of extemal phase locked loop 1 : o synchronies the generated signals; secondly, it eliminated the use of extemal three state buffer IC to select the desired zero crossing signals. f the complete controller can be c) The testing o acheved using t h e synchro emulator generated zero crossing signals rather than connecting the controller to the zero crossing dietector and the three phase supply. d) A control ASIC whch allows a precise and reliable dlgital control of the mean value of the dc output voltage, by providing the firing pulses for the power thyristors in the appropriate 6-pulse sequence and with the appropriate delay time. e) The downloadmg of the schematic configuration into FPGAs is easily achieved while powering on the circuit. f ) The ability of changng the firing strategy, simply by changing the CCPA EPROM. g) The controller was designed in such way that another controller can be fit in parallel and the two can be used in 12 pulse rectifier system. h) A new zero-crossing detection circuit providing the following advantages: -Small size and weight and low cost in comparison with other zero-cralssing detectors. -It avoids the use of transformers and requires just three power resistors. -It performs galvanic isolation and high noise immunity by using Schmidt-trigger optoisolators with hysteresis.

-Rgh reliability and stability in the presence of noise due to the commutation of the recMier elements. There is a wide range of applications for such an ASIC controlled power rectifier, such as dc link power converters, dc motor drives, automation industry and uninterruptble power supplies.

REFERENCES

[11 M. N. Cirstea : An investigation into ASIC control of a 6-pulse cycloconverter for a quad-winding induction motor, PhD thesis, The Nottingham Trent University, 1996. [2] E. B. Patterson, D Morley, C Oswald and P. G. Holmes : ASIC chip set for a cycloconverter dnve PCB, IEEE, Euro ASIC92, Paris, 1992. (Best Circuit Award). [3] G. Oliver, V. R. Stefanovic, and G. E. April : Microprocessor controller for a thyristor converter with an improved power factor, IEEE Trans. Ind. Electron. Contr. Instrum., vol. IECI-28, pp. 188-194, aug. 1981. [4] P. C. Tang, S. S. Lu, and Y. C. Wu : Mcroprocessor-based design of a firing circuit for three-phase full-wave thyristor dual converter,, IEEE Trans. Ind. Electron., vol. IE-29, pp. 67-73, Feb. 1982. [5] G. H. Witscher : A Microprocessor-based synchronisation scheme for Qgtally controlled threephase thyristor power converters, IEEE Trans. Ind. Electron., vol. IE-30, pp. 330-333, Nov. 1983. [6] A. Ivlirbod and A. El-Amawy : A general-purpose microprocessor based control circuit for a three-phase controlled rectfier bridge IEEE Trans. Ind. Electron., vol. E-33, pp. 310-317, Aug. 1986. [7] H. P. Gerson : A Microprocessor-Based Synchronisation Scheme for Digitally Controlled Three-phase Thyristor Power Converters, IEEE Trans. on Industrial Electronics , vol. IE-30, 110.4, Nov. 1983, pp. 330-333. [SI L. X. Le. and G. J. Berg : Firing Circuit for A Three-phase SCR Voltage Controller, IEEE Trans. on Industrial Electronics ,vol. IE-31, no.4, Nov. 1984, pp. 389-390. [9] W. Fkhard and P. D. Francis : New synchronisation Method for Thyristor Power Converters to Weak AC-Systems, IEEE Trans. on Ind. Electronics, vol. 40, no. 5, Oct. 1993, pp. 505-511.

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