Response to ideal square wave signal

Capacitor:

Consider a simple RC circuit which all of us must have seen before. By simply applying Kirchoffs Law we can find out the relationship between applied voltage, current and voltage across capacitor ( Vc ) , Where Therefore,
dq (t ) q (t ) V (t ) + = dt RC R
dt To solve the above differential equation multiply both sides by e RC = et / RC . We get 1

V (t ) i (t ) R Vc (t ) = 0 q (t ) dq(t ) and i = Vc (t ) = C dt

q (t )et / RC =

1 V (t )et / RC dt R

For V (t ) = V0 with initial condition Vc (t = t0 ) = Vc 0 , we get

Vc (t ) = V0 1 e ( t t0 )/ RC + Vc 0 e (t t0 )/ RC

For V (t ) = mt with initial condition q (t = 0) = 0 , we have

q (t ) = CV (t ) ( mRC 2 ) (1 e t / RC )

Vc (t ) = V (t ) (mRC ) (1 e t / RC )

This is the response of capacitor for a linear wave. Now consider a pulse with very high value of m which rises to some finite value, say V0 , in very short interval t0 . Putting the series form of exponential, 1 1 Vc (t0 ) = V (t0 ) (mRC ) 1 1 t0 / RC + (t0 / RC ) 2 (t0 / RC )3 + ... 2! 3!

1 t0 1 t0 2 Vc (t0 ) = V0 + ... 2 3 2! ( RC ) 3! ( RC ) By taking the limit m tending to infinite and therefore t0 tending to zero one finds Vc (t0 ) = 0 .

Now consider an ideal square wave of 50% duty cycle with time period 2T. By ideal we mean that the time for switching from one voltage level to another is zero (infinite m).

As shown above, capacitor doesnt respond to such pulse of infinite m. Therefore we can think of square wave as a DC source with voltage

V V (t ) = 0 V0
For n = 0, 2, 4..

for nT < t (n + 1)T for (n + 1)T <t (n + 2)T

Vc [( n + 1)T ] = V0 (1 e T / RC ) + Vc [nT ]e T / RC Vc [(n + 2)T ] = V0 (1 e T / RC ) + Vc [(n + 1)T ]e T / RC

By combining above two equations we get,

Vc [(n + 2)T ] = V0 (1 e T / RC ) 2 + Vc [ nT ]e 2T / RC Putting n = n-2, n-4 ...2, 0 in equation (0) Vc [ nT ] = V0 (1 e T / RC ) 2 + Vc [( n 2)T ]e 2T / RC
T / RC 2 2T / RC

..0

.1

.2 Vc [(n 2)T ] = V0 (1 e ) + Vc [( n 4)T ]e ............... .. Vc [( n 2k + 2)T ] = V0 (1 e T / RC ) 2 + Vc [( n 2k )T ]e 2T / RC .k

Vc [2T ] = V0 (1 e T / RC ) 2 + Vc [0]e 2T / RC

n/2

Multiplying kth equation by e 2 kT / RC and adding

Vc [( n + 2)T ] = V0 (1 e T / RC ) 2 {1 + e 2T / RC + e 4T / RC + ... + e nT / RC } + Vc [0]e ( n + 2)T / RC

(1 eT / RC ) 2 Vc [(n + 2)T ] = V0 (1 e ( n + 2)T / RC ) + Vc [0]e ( n + 2)T / RC 2T / RC (1 e ) For the limit n

(1 e T / RC )2 (1 e2T / RC ) This is the steady-state peak voltage across capacitor. Now, Vc [] = V0 d Vc [] 2e T / RC (1 eT / RC ) 2 = dT V0 RC (1 e2T / RC ) 2 = +ve T > 0 Therefore Vc [] increases with T. Also,

Vc [] = V0 / 2 for T = RC ln 3