2-bit ripple binary counter using JK flip flops (asynchronous counters)

1 J CP K Q0 CP Q0 Q0 Q1 K Q0 J Q1

J 0 0 1 1

K 0 1 0 1

Q(t+1) Q(t) 0 1 Q(t)

Q1

0 0

1 0

0 1

1 1

0 0

1 J CP

3-bit ripple binary counter using JK flip flops (asynchronous counters)

Q0 J Q1 J Q2

K Q0 CP Q0 Q0 Q1 Q2

Q1

Q2

Simple Registers
No external gates. Example: A 4-bit register. A new 4-bit data is loaded on every clock cycle.
A4 A3 A2 A1

Q D CP I4

Q D

Q D

Q D

I3

I2

I1

(Control Signal) Load I1

4-bit register with parallel load

S Q R A1

I2

S Q R

A2

I3

S Q R

A3

I4

S Q R

A4

CP Clear

Register with Parallel Load Using D Flip Load Flops Load A + Load I
1 1

D Q I1

A1

D Q I2

A2

I3

D Q

A3

I4 CP Clear

D Q

A4

Using Registers to implement Sequential Circuits

A sequential circuit may consist of a register (memory) and a combinational circuit. Next-state value Register
Inputs

Clock Pulse

Combinational Circuit

Outputs

The external inputs and present states of the register determine the next states of the register and the external outputs, through the combinational circuit. The combinational circuit may be implemented by any of the methods covered in MSI components and Programmable Logic Devices.

Using Registers to implement Sequential Circuits

Example 1: Design a Sequential Circuit whose state table is given below
A1+ = m(4,6) = A1. x' A2+ = m(1,2,5,6) = A2.x' + A'2 .x = A2 x y = m(3,7) = A2.x Present State A1 A2 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1
using two flip-flops.

State Table
Input x 0 1 0 1 0 1 0 1

Next State A1+ A2+ 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0

Logic Diagram
Output y 0 0 0 1 0 0 0 1 x y

A1 . x A2 x

A1 A2

Sequential Circuit Implementation

Using Registers to implement Sequential Circuits

Address Outputs 1 2 3 1 2 3 A1 A2 x A1 A 2 y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 0 0 1 ROM truth table

Example 2: Repeat example 1, but use a ROM &Register.

A1 x A2

1 2 3

8X3 ROM

1 2 3 y

Sequential circuit using a register and a ROM

Serial IN/Serial Out Shift Registers

Accepts data serially one bit at a time and also produces output serially.
Serial Input (SI) D Q Q0 D Q Q1 D Q Q2 D Q Q3 Serial Output (SO)

CLK

Shift Register

Serial In/Serial Out Shift Registers

Application: Serial transfer of data from one register to another.

SI Clock Shift Control Clock Shift Control CP

1011 Shift register A CP

SO

SI

0010 Shift register B

SO

Wordtime

T1

T2

T3

T4

Serial In/Serial Out Shift Registers

Serial-transfer example.

Timing Pulse Initial value After T1 After T2 After T3 After T4

Shift Register A 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1

Shift Register B 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1

Serial output of B 0 1 0 0 1

Bidirectional Shift Registers

4-bit bidirectional shift register with parallel load
Parallel outputs A4 A3 A2 A1

Clear

Q D

Q D

Q D

Q D

CLK

S1 S0

4x1 MUX 3 2 1 0

4x1 MUX 3 2 1 0

4x1 MUX 3 2 1 0

4x1 MUX 3 2 1 0

Serial input for shift-right

I4

I3 Parallel inputs

I2

I1

Serial input for shift-left

Bidirectional Shift Registers

4-bit bidirectional shift register with parallel load. Mode Control s1 s0 Register Operation 0 0 No change 0 1 Shift right 1 0 Shift left 1 1 Parallel load

An Application-Serial Addition
Most operations in digital computers are done in parallel. Serial operations are slower but require less equipment. A serial adder is shown below. A A+B.
SI 1010 Shift register A SI 0111 Shift register B SO SO x y FA z Q D S C

Shift-right CP External input

Clear

Excitation table for a serial adder

Example: Design a serial adder using a sequential logic procedure Q(t) Q(t+1) J K with JK flip-flops.
Present State Q 0 0 0 0 1 1 1 1 Inputs x 0 0 1 1 0 0 1 1 y 0 1 0 1 0 1 0 1 Next State Q 0 0 0 1 0 1 1 1 Output S 0 1 1 0 1 0 0 1 Flip-flop inputs JQ 0 0 0 1 X X X X KQ X X X X 1 0 0 0 0 0 1 1 0 1 0 1 0 1 X X

X 1 X 0

S=x+y + Q JQ = xy KQ = xy =(x+y)

Shift-right CP External input

Shift register A

SO=x

Shift register B SO=y

J Q

Clear

Second form of a serial adder

S=x+y + Q JQ = xy KQ = xy =(x+y)

4-bit binary ripple counter

J 0
A4 A3 A2 A1

K 0 1 0 1
J 1

Q(t+1) Q(t) 0 1 Q(t)

0 1 1

Q To next stage

Count pulses K 1 K 1 K 1 K 1

Count sequence for a binary ripple counter

Count sequence A4 A3 A2 A1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Condition for complementing flip-flops Complement A1 Complement A1 Complement A1 Complement A1 Complement A1 Complement A1 Complement A1 Complement A1 A1 will go from 1 to 0 and complement A2; A2 will go from 1 to 0 and complement A3; 1 0 0 0 A3 will go from 1 to 0 and complement A4 And so on A1 will go from 1 to 0 and complement A2 A1 will go from 1 to 0 and complement A2 A2 will go from 1 to 0 and complement A3 A1 will go from 1 to 0 and complement A2

State diagram of a decimal BCD counter

0000

0001

0010

0011

0100

1001

1000

0111

0110

0101

Logic diagram of a BCD ripple counter

0 Q8 0 Q4 0 Q2 0 Q1

1 Q J

0 Q J

0 Q J

1 Q J 1 Count pulses

J 0 0 1 1

K 0 1 0 1

Q(t+1) Q(t) 0 1 Q(t)

Timing diagram for the decimal counter

Count pulses

Q1 Q2 0 Q3 0 Q4 0 Q5 0
1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0

Block diagram of a 3-decade decimal BCD counter

Q8 Q4 Q2 Q1

Q8 Q4 Q2 Q1

Q8 Q4 Q2 Q1

BCD Counter
102 digit 0-999

BCD Counter
101 digit 0-99

BCD Counter
100 digit 0-9

Count pulses

J 0 0 1 1

K 0 1 0 1

Q(t+1) Q(t) 0 1 Q(t)

4-bit synchronous binary counter

A4

A3

A2

A1

Q/
K

Q J

Q/ K

Q J

Q/ K

Q J

Q/ K

Q J CP

To next stage

Count enable

T 0 1

Q(t+1) Q(t) Q(t)

4-bit up-down binary counter

A4 A3 A2 A1 Q

Q/ T

Q/ T

Q/ T

Q/ T

CP

To Next stage

UP

Down

Design a BCD counter using T flip-flops

Excitation table for a BCD counter

Count Sequence
Q8
0 0 0 0 0 0 0 0 1 1

Flip-flop inputs
Q1
0 1 0 1 0 1 0 1 0 1

Output Carry
y
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

Q4
0 0 0 0 1 1 1 1 0 0

Q2
0 0 1 1 0 0 1 1 0 0

TQ8
0 0 0 0 0 0 0 1 0 1

TQ4
0 0 0 1 0 0 0 1 0 0

TQ2
0 1 0 1 0 1 0 1 0 0

TQ1

Using K-maps, we get TQ1 =1 TQ2 = Q/8Q1 TQ4 = Q2Q1 TQ8 = Q8Q1 + Q4Q2Q1 y = Q8Q1 Now logic diagram can be drawn for BCD synchronous counter

Q(t) Q(t+1) 0 0 1 1 0 1 0 1

T 0 1 1 0

Q8 Q8
T CP

Q4 Q4
T

Q2 Q2

Q1 Q1

TQ1 =1 TQ2 = Q/8Q1 TQ4 = Q2Q1 TQ8 = Q8Q1 + Q4Q2Q1 y = Q8Q1

Counters with Parallel Load 4-bit counter with parallel load.

Clear 0 1 1 1 CP X X Load X 0 1 0 Count X 0 X 1 Function Clear to 0 No Change Load inputs Next State (counting)

Count Load I1

JQ K

A1

I2

JQ K

A2

I3

JQ K

A3

J 0 0 1 1

K 0 1 0 1

Q(t+1) Q(t) 0 1 Q(t)

I4

JQ K

A4

Clear CP

4-bit binary counter with parallel load

Carry out

Counters with Parallel Load Different ways of getting a MOD-6 counter

A4 A3 A2 A1 Load I 4 I 3 I2 I1 Inputs = 0 Count = 1 Clear = 1 CP Clear I 4 I 3 I2 I1 A4 A3 A2 A1 Count = 1 Load = 0 CP

(a) Binary states 0,1,2,3,4,5

A4 A3 A2 A1 Carry-out Load I4 I 3 I2 I 1 1 0 1 0 Count = 1 Clear = 1 CP

(b) Binary states 0,1,2,3,4,5

A4 A3 A2 A1 Load I4 I 3 I2 I 1 0 0 1 1 Count = 1 Clear = 1 CP

(c) Binary states 10,11,12,13,14,15 (d) Binary states 3,4,5,6,7,8

Timing Sequences
Start CP Stop R S Q Word-time control

CP

3-bit counter

Count enable

(a) Circuit Diagram

CP Start Stop Q Word-time = 8 pulses

(b) Generation of a word-time control for serial operations

Shift right

T0

T1

T2

T3

(a) ring-counter (initial value = 1000)

T0 T1 T2 T3 CP T0 T1 T2 T3

2X4 decoder
Count enable

2-bit counter

(b) Counter and Decoder

(c) Sequence of four timing signals

D Q

D Q

D Q

D Q

A/

B/

C/

E/

CP

(a) 4-stage switch tail ring counter Sequence number

1 2 3 4 5 6 7 8

Flip-flop outputs A B C E
0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1

And gate required for outputs

A/ E/ A B/ B C/ C E/ AE A/ B B/ C C/ E

(b) Count sequence and required decoding