Analysis and Synthesis of

Synchronous Sequential Circuits

Synchronous Sequential Circuits
• Finite State Machine (FSM)
- Combination of combinatorial and sequential logic. Mealy and
Moore types - Digital control circuits.
- The general structure of such a circuit is shown in figure.1

Figure.1 The general form of a sequential circuit

 Basic Design Steps

Suppose that we wish to design a circuit that meets the following specification :
1.A circuit has one input w and one output z.
2.Use positive edge clock.
3.Output z = 1 if during two immediate preceding clock cycles the input w was
equal to 1, Otherwise z= 0.

figure.4.2 Sequences of input and output signals

 Basic Design Steps (contd.,)

• The first step in designing a FSM is to determine how many states are
needed and which transitions are possible from one state to another.
• There is no procedure for this task.

• The designer must carefully think about that what the machine has to
accomplish.
• A Good way to begin is to select one particular state as starting state.

• A designer maps the descriptive specification onto a state diagram.

 State diagram
• Nodes (Circles) represent states
and directed arcs represent transitions
from one state to another.
• Starting state after reset.

Figure.4.3 State diagram of a simple sequential circuit

 State Tables
• A State Table tabulates Next States as a function all possible Present
States and the inputs to the circuit.
• The State Machine moves from the Present State to Next State after
each clock transition

Figure.4.4 State diagram of a simple sequential circuit

 State Assignment
• In an implementation each State is represented by a particular valuation
(combination of values) of State Variables.
• Each state variable is implemented in the form of a flip-flop.

Figure.4.5. A General sequential circuit with input w, output z and two state flipflops
 State-assignment table
• Similar to the state table, but with state names replaced by state variables.
• y1 and y2 are called present-state variables.
• Y1 and Y2 are called next-state variables.
• Note don’t care (d) state in figure.6

Figure.4.6. A State-assigned table for the sequential circuit in figure

 Choice of flip-flops and Derivation of Next-State
and Output Expressions
• Using D-type flip-flops is easy and straight forward, because the input is transferred
unchanged to the output.
• See figures.7 and 8 for implementation.

Figure.4.7 Figure.4.8
 Timing diagram
•Figure.9 shows the timing diagram, with delays, for the above example.

Figure.4.9 Timing diagram for the circuit in figure.8

 Summary of design steps

1.Obtain specification.
2.Derive state diagram.
3.Minimize states (later).
4.State assignment.
5.Choose flip-flops.
6.Implement circuit.
•A slightly more complex example of a
•control circuit.
•A typical instruction in a computer is to
swap the values of two registers via a three-
state bus.
•See figure 7.56 and 7.57.
 State assignment problem

• In general, circuits are much larger than our example, and different state

assignments can have a substantial effect on the cost of the final implementation.

• Alternate assignment of values to states can lead to simpler designs, but there is

no formal procedure.

• CAD tools use proprietary heuristic techniques.

• See first example in figures 4.10 and 4.11

Figure 4.10 Improved state assignment Figure 4.11 Final circuit for the improved state
assignment
 One-hot encoding
• One-hot encoding can be used to represent states
instead of binary encoding as used up to now.
• In this method, for each state all but one of the
variables are equal to 0.
• The variable whose value is 1 is deemed to
be “hot”
• Disadvantage: requires more flip-flops.
• Advantage: simpler output circuit.

Figure 4.12 One-hot state assignment

 Mealy State Model
•Moore model – output only a function of the present state.
•Mealy model – output a function of the present state and the input(s).

•Example: modification of previous example – see

figures 8.22 to 8.26.
•NB. During present clock cycle the output is
determined by the state from which the arc emanates
and the input value on the arc.
 The Synchronous Sequential Circuit Model

• Synchronous sequential circuits are realized using combinational logic and

one or more flipflops.
• The general structure of such a circuit is shown in figure 8.1.

x1 z1
...

...
xn C o m b in a t i o n a l zm
lo g ic

y1 ... yr Yr ... Y1

M em ory

Figure 8.1

C lo c k
• Sequential circuits are also called Finite state machine (FSMs)
• FSM-Functional behavior of these circuits can be represented using a finite
number of states.
Mealy Machine Model

A
1 /1 1 /0
0 /1
0 /0 0 /0 1 /0
B C
X /Z
(a )

P resen t In p u t x
sta te 0 1
A B /1 C /0
B B /0 A /1
C A /0 C /0
N e x t s ta te /o u tp u t
(b )

Figure 8.2
 Mealy Machine Timing Diagram -- Example 8.1

T0 T1 T2 T3 T4 T5
C lo c k
S ta te A B A C A C A

In p u t x 0 1 1 0 1 0
O u tp u t z 1 1 0 0 0 0

Figure 8.3
Moore Machine Model
0
1
W /0 X /1
0 0
1 1

Y /0
(a )

P resen t In p u t x
sta te 0 1 O u tp u ts
W Y X 0
X X Y 1
Y X W 0

(b )

Figure 8.4
Moore Machine Timing Diagram -- Example 8.2

T0 T1 T2 T3 T4 T5

C lo c k
S ta te W Y W X X Y X
In p u t x 0 1 1 0 1 0

O u tp u t z 0 0 0 1 1 0

Figure 8.5
Analysis of Sequential Circuit State Diagrams --
Example 8.3

x /z
0 /0 1 /0 1 /1

1 /0 0 /0
00 01 11

0 /0

Figure 8.6
 Timing Diagram for Example 8.3

C lo c k
x 0 0 1 1 1 0 1 1 0 0

y1 0 0 0 0 0 0 1 1 1 0
0
y2 0 0 0 1 1 1 1 1 1
z 0 0 0 0 0 0 1 1 0 0

Figure 8.7
Analysis of Sequential Circuit Logic Diagrams
C o m b in a tio n a l lo g ic

y Y
Q D

y
Q C C lo c k

M em ory
(a )
D t


C

0 1 2 3 4 t/D t
(b )

Figure 8.8
 Timing Diagram for Figure 8.8 (a)

C lo c k

x 0 1 1 0 1 0 0 0

y 0 0 1 0 0 1 1 1

Y = D 0 1 0 0 1 1 1 1

z 0 0 1 0 0 0 0 0
0 1 2 3 4 5 6 7 8 t/D t
G litc h

Figure 8.9
State Table and State Diagram for Figure 8.8 (a)

In p u t x k In p u t x k In p u t x k
P resen t 0 1 P resen t 0 1 P resen t 0 1
sta te sta te sta te
0 0 0 /0 1 /0 A A /0 B /0
y k y k

1 1 1 /0 0 /1 B B /0 A /1

N e x t s ta te /o u tp u t N e x t s ta te /o u tp u t
(a ) (b ) (c )
x/
z
0 /0 0 /0
1 /0
A B
1 /1
(d )

Figure 8.10
 K-Maps for Circuit of Figure 8.8 (a)

x k
xk In p u t x k
0 1 0 1 P resen t 0 1
sta te
0 0 1 0 0 0 A A /0 B /0
k k
y y
1 1 0 1 0 1 B B /0 A /1

yk + 1
/z k
(a ) (b ) (c )

Figure 8.11
Synchronous Sequential Circuit with T Flip-Flop --
Example 8.4

z
x

y
Q T
y
Q C C lo c k

Figure 8.12
 Timing Diagram for Example 8.4

C lo c k
x 0 1 1 0 1 0 0 0

y 0 1 0 0 1 0 1 1

T
z 0 1 0 0 1 0 0 0
0 1 2 3 4 5 6 7 8

Figure 8.13
State Table and State Diagram for Example 8.4

k
x xk x k

yk 0 1 yk 0 0 1 P resen t 0 1
sta te
1 1 /0 0 /0 A B /0 A /0
0 1 1 /0 0 /1 B B /0 A /1
yk + 1/z k yk + 1/zk N e x t s ta te /o u tp u t
(a ) (b ) (c)
x/
z
1 /0
0 /0
A B
1 /1 0 /0
(d )

Figure 8.14
 K-Maps for Example 8.4
xk x k xk
0 1 0 1 0 1

0 0 0 0 1 0 0 1* 0
k k k
y y y
1 0 1 1 0 1 1 1 0*

zk T k yk + 1

(a ) (b ) (c)

k
x
0 1

0 1 /0 0 /0
yk
1 1 /0 0 /1

yk + 1
/z k
(d )

Figure 8.15
Synchronous Sequential Circuit with JK Flip-flops --
Example 8.5
z

J Q y1
1
C
K Q
1 y1

J Q y2
2
C
K 2
Q y2

C lo c k

Figure 8.16
Timing Diagram and State Table for Example 8.5
C
x 0 0 1 1 1 1 0 0
y1 1 0 0 0 1 1 1 0
y2 0 0 0 1 0 1 1 0
J1 = xy2

K1 = x
J2 = x
K 2 = x + y1
z = xy1 y2 0 0 0 0 0 1 0 0

(a )

x
y1 y2 0 1

00 0 0 /0 0 1 /0

01 0 0 /0 1 0 /0

11 0 0 /0 1 1 /1

10 0 0 /0 1 1 /0

(b )

Figure 8.17
K-Maps for Example 8.5
x x
y1 y2 0 1 y1 y2 0 1

00 0 0 00 1 0

01 0 1 01 1 0

11 0 1 11 1 0

10 0 0 10 1 0

J1 K 1

x x x
y1 y2 0 1 y1 y2 0 1 y1 y2 0 1

00 0 1 00 1 1 00 0 0

01 0 1 01 1 1 01 0 0

11 0 1 11 1 0 11 0 1

10 0 1 10 1 0 10 0 0

J2 K 2
z

Figure 8.18
Generating the State Table From K-maps --
Example 8.5
x
y1 y2 0 1

00 01 01 00 11
x x
y1 y2 y1 y2
0 1 0 1
01 01 01 10 11
00 00 01 00 0 0 /0 0 1 /0
11 01 01 10 10 01 00 10 01 0 0 /0 1 0 /0
11 00 11 11 0 0 /0 1 1 /1
10 01 01 00 10
10 00 11 10 0 0 /0 1 1 /0
J1 K 1
J2 K 2
J1 K 1
J2 K 2 Y1 Y2 Y 1 Y 2/z
(a ) (b ) (c )

Figure 8.19
Synchronous Sequential Circuit Synthesis
x
0 1
A 1 /0 B
A D /0 B /0
1 /1
0 /0 1 /0 B D /0 C /0
0 /0 1 /0
0 /0 D C D /0 B /0
0 /0 C
D D /0 A /1

(a ) C o m p le te ly s p e c ifie d c ir c u it

x
A B 0 1
1 /1 0 /- 0 /0
A B /- -/1
1 /-
0 /- 1 /1 B B /0 C /1
C C A /- A /-

(b ) I n c o m p le te ly s p e c ifie d c ir c u it

Figure 8.20
Introductory Synthesis Example -- Example 8.6
x

z
x x
0 1 S ta te
y1 y2 y1 y2 0 1
A A /0 B /0 A 0 0 00 0 0 /0 0 1 /0
B A /0 C /1 B 0 1 01 0 0 /0 1 1 /1
C B /0 D /0 C 1 1 11 0 1 /0 1 0 /0
D C /1 D /0 D 1 0 10 1 1 /1 1 0 /0
(b ) S ta te ( c ) T rY a 1n Ys i 2t /i oz n
(a ) S ta te ta b le a s s ig n m e n t ta b le

x x x
y1 y2 0 1 y1 y2 0 1 y1 y2 0 1

00 0 0 00 0 0 00 0 1 y1
Q D 1
y1
01 0 1 01 0 1 01 0 1 Q C

11 0 0 11 0 1 11 1 0
y2
Q D 2
10 10 10 y2
1 0 1 1 1 0 Q C C lo c k
z D 1 (= Y 1) D 2 (= Y 2)
(d ) O u tp u t K -m a p (e ) E x c ita tio n K -m a p s (f) L o g ic d ia g r a m

Figure 8.21
Flip-flop Input Tables -- Example 8.6
S ta te R e q u ir e d S ta te R e q u ir e d
tr a n s itio n s in p u ts tr a n s itio n s in p u ts
Q (t) Q (t + e ) D (t) Q (t) Q (t + e ) S (t) R (t)
0 0 0 0 0 0 d
0 1 1 0 1 1 0
1 0 0 1 0 0 1
1 1 1 1 1 d 0
(a ) D flip -flo p (b ) C lo c k e d S R

S ta te R e q u ir e d S ta te R e q u ir e d
tr a n s itio n s in p u ts tr a n s itio n s in p u ts
Q (t) Q (t + e ) T (t) Q (t) Q (t + e ) J (t) K (t)
0 0 0 0 0 0 d
0 1 1 0 1 1 d
1 0 1 1 0 d 1
1 1 0 1 1 d 0
(c ) C lo c k e d T flip -flo p (d ) C lo c k e d J K flip -flo p

Figure 8.22
Generating the JK Flip-flop Excitation Maps --
Example 8.7
x x x
y1y2 0 1 y1y2 0 1 y1y 2 0 1
0 0 0 0 /0 0 1 /0 00 0d 0d 00 0d 1d
0 1 0 0 /0 1 1 /1 01 0d 1d 01 d1 d0
1 1 0 1 /0 1 0 /0 11 d1 d0 11 d0 d1
1 0 1 1 /1 1 0 /0 10 d0 d0 10 1d 0d
Y 1 Y 2/z J 1K 1 J 2K 2
(a ) T r a n s itio n ta b le (b ) E x c ita tio n ta b le

x x x x
y 1y2 0 1 y1y2 0 1 y 1y2 0 1 y1y 2 0 1

00 0 0 00 d d 00 0 1 00 d d

01 0 1 01 d d 01 d d 01 1 0

11 d d 11 1 0 11 d d 11 0 1

10 d d 10 0 0 10 1 0 10 d d

J1 K 1
J 2
K 2
(c ) E x c ita tio n m a p s

Figure 8.23
Clocked JK Flip-Flop Implementation --
Example 8.7
x

y1
Q J1
C
y1
Q K 1

y2
Q J2
C
y2
Q K2

C lo c k

Figure 8.24
Application Equation Method for Deriving
Excitation Equations -- Example 8.8
x x
y1 y2 0 1 y1 y2 0 1

00 0 0 00 0 1

01 0 1 01 0 1
y2
11 0 1 11 1 0
y1
10 1 1 10 1 0

Y 1
Y 2

Figure 8.25
Sequence Recognizer for 01 Sequence --
Example 8.9

1 /0 1 /0 0 /0
A A B

(a ) (b )

1 /0 0 /0 0 /0 1 /0 0 /0 0 /0
A B A B
1 /1
(c ) (d )

Figure 8.26
Synthesis of the 01 Recognizer with SR Flip-flops
x x x
0 1 yk 0 1 yk 0 1
A B /0 A /0 0 1 0 0 0 0

B B /0 A /1 1 1 0 1 0 1

yk+ 1 z
(a ) S ta te ta b le (b ) T r a n sitio n ta b le a n d o u tp u t m a p

x x x S Q yk
yk 0 1 yk 0 1 C
0 0 R Q
1 0 0 d

1 d 0 1 0 1
C lo c k
S R
(c ) E x c ita tio n m a p s
(d ) L o g ic d ia g r a m z

C lo c k
x 0 1 0 1 0 1
S = x 1 0 0 0 1 0 1 1 0 0 0
R = x 0 1 1 1 0 1 0 0 1 1 1
y
z

(e ) T im in g d ia g r a m

Figure 8.27
Realization of 01 Recognizer with T Flip-flops
x
yk 0 1 x
T Q y
0 1 0
C Q
1 0 1

T C lo c k
(a ) C lo c k e d T flip -flo p (b ) C lo c k e d T flip -flo p
e x c ita tio n m a p im p le m e n ta tio n

x x
yk 0 1 yk 0 1

0 1 0 0 d d

1 d d 1 0 1

J K
(c ) C lo c k e d J K e x c ita tio n m a p s

Figure 8.28
Design of a Recognizer for the Sequence 1111 --
Example 8.11
0 /0 1 /1 x
0 /0 0 1
0 /0
A B C D A A /0 B /0
1 /0 1 /0 1 /0
B A /0 C /0
0 /0
D A /0 D /1
(a ) S ta te d ia g r a m
C A /0 D /0

(b ) S ta te ta b le

x x
y 1ky 2k
y 1ky 2k 0 1 0 1
00 00 01 00 0 0

01 00 10 01 0 0

11 00 11 11 0 1

10 00 11 10 0 0

y 1k+1y 2k+1 z
(c ) T r a n s itio n ta b le (d ) O u tp u t m a p

Figure 8.29
SR Realization of the 1111 Recognizer
x x
y 1ky 2k 0 1 y 1ky 2k 0 1
00 0 0 00 d d

01 0 1 01 d 0

11 0 d 11 1 0

10 0 d 10 1 0

S 1
R 1

x x
y 1ky 2k 0 1 y 1ky 2k 0 1
00 0 1 00 d 1

01 0 0 01 1 1

11 0 d 11 1 0

10 0 1 10 d 0

S 2 R 2

Figure 8.30
Clocked T and JK Realizations of the 1111
Recognizer
x x
y 1ky 2k y 1ky 2k
0 1 0 1
00 0 0 00 0 1

01 0 1 01 1 1

11 1 0 11 1 0

10 1 0 10 0 1

T( a1 ) C l o c k e d T e x c i t a t i o n m a p sT 2

x x x x
y 1ky 2k y 1ky 2k y 1ky 2k y 1ky 2k
0 1 0 1 0 1 0 1
00 0 0 00 d d 00 0 1 00 d d

01 0 1 01 d d 01 d d 01 1 1

11 d d 11 1 0 11 d d 11 1 0

10 d d 10 1 0 10 0 1 10 d d

J1 K J K
( b )1 C l o c k e d J K e x c i t a t i o n m a p s 2 2

x x
y1 y2 0 1 y1 y2 0 1
00 0 0 00 0 1

01 0 1 01 0 0
y2
11 0 1 11 0 1
y1
10 0 1 10 0 1

Y Y
( 1c ) E x c i t a t i o n K - m a p s 2

Figure 8.31
Clocked JK Flip-Flop Realization of a 1111
Recognizer
C lo c k
y1
J 1 Q
C
x K 1 Q

J Q
2 y2
C
K 2
Q

Figure 8.32
Design of a 0010 Recognizer
0 /0 0 /0 1 /0 0 /1 0 /0 0 /0 1 /0 0 /1
A B C D E A B C D E
0 /0

G C om e h ere for a n G
in c o r r e c t in p u t x = 0 1 /0 1 /0
1 /0 1 /0
F C om e h ere for a n F
in c o r r e c t in p u t x = 1
(a ) (b )
0 /0
0 /0 0 /0 1 /0 0 /1
0 /0 A B C D E
0 /0 0 /0 1 /0 0 /1 0 /0
0 /0
A B C D E 0 /0
0 /0 1 /0 G
1 /0
1 /0 1 /0 1 /0
1 /0 G F
1 /0
1 /0 1 /0
F
1 /0
(c ) (d )

x
0 1
A B /0 F /0 x 0 /0
B C /0 F /0 0 1
C G /0 D /0 A B /0 A /0 1 /0 G
D E /1 F /0 B C /0 A /0 1 /0
0 /0
1 /0
E C /0 F /0 C G /0 D /0 0 /0 1 /0
A B C D
0 /0
F B /0 F /0 D B /1 A /0 0 /1
G G /0 F /0 G G /0 A /0
1 /0
(e ) (f) (g )

Figure 8.33
 Design of a Serial Binary Adder

ai a ib i/ s i
S h ift r e g is te r A 0 0 /0 0 1 /0
S e r ia l si 0 1 /1 1 1 /0 1 0 /0
bi adder 1 0 /1 0 1 1 1 /1
S h ift r e g is te r B c i-1 = 0 0 0 / 1 c i-1 = 1
(b )

(a )

ai
bi S i

ai bi c i-1 ci si
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 C i
C i-1
D Q
1 0 0 0 1
1 0 1 1 0 C
1 1 0 1 0
1 1 1 1 1
C lo c k

(c) (d )

Figure 8.34
Design of a Four-State Up/Down Counter
x x
z = 0 z = 1 0 1 y 1ky 2k 0 1
0 0 1 0 1 /0 3 /0 00 01 11
1
1 2 /1 0 /1 01 10 00
0 1 1 0
2 3 /2 1 /2 11 00 10
1
3 0 2 3 0 /3 2 /3 10 11 01
z = 3 z = 2 y1k + 1y2k + 1
(a ) S ta te d ia g r a m (b ) S ta te ta b le (c ) T r a n s itio n ta b le

x x
y1y2 0 1 y1y2 0 1

00 0 d 1 d 00 1 d 1 d

01 1 d 0 d 01 d 1 d 1

11 d 1 d 0 11 d 1 d 1

10 d 0 d 1 10 1 d 1 d

J1 K 1 J 1 K 1 J2 K 2 J2 K 2
(d ) E x c ita tio n m a p s

Figure 8.35
An Implementation of the Up/Down Counter

C lo c k
y1
x J Q
1
C
K 1 Q

J Q
1 y2
1 C
K 1 Q LE D s

Figure 8.36
Design a BCD Counter
x
y3k y2ky1ky0k 0 1
0000 0000 0001
0001 0001 0010
x
0010 0010 0011
0 1
0011 0011 0100
0 0 1
0100 0100 0101
1 1 2
0101 0101 0110
2 2 3
0110 0110 0111
3 3 4
0111 0111 1000
4 4 5
1000 1000 1001
5 5 6
1001 1001 0000
6 6 7
1010 dddd dddd
7 7 8
1011 dddd dddd
8 8 9
1100 dddd dddd
9 9 0
1101 dddd dddd
(a )
1110 dddd dddd
1111 dddd dddd

y 3k + 1y k + 1y k + 1y k + 1
2 1 0

(b )

Figure 8.37 (a) and (b)

 Design of the BCD Counter (con’t)
x x x x x x x x
y3k y 2ky1ky0k 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0000 0 0 d d 0 0 d d 0 0 d d 0 1 d d
0001 0 0 d d 0 0 d d 0 1 d d d d 0 1
0010 0 0 d d 0 0 d d d d 0 0 0 1 d d
0011 0 0 d d 0 1 d d d d 0 1 d d 0 1
0100 0 0 d d d d 0 0 0 0 d d 0 1 d d
0101 0 0 d d d d 0 0 0 1 d d d d 0 1
0110 0 0 d d d d 0 0 d d 0 0 0 1 d d
0111 0 1 d d d d 0 1 d d 0 1 d d 0 1
1000 d d 0 0 0 0 d d 0 0 d d 0 1 d d
1001 d d 0 1 0 0 d d 0 0 d d d d 0 1
1010 d d d d d d d d d d d d d d d d
1011 d d d d d d d d d d d d d d d d
1100 d d d d d d d d d d d d d d d d
1101 d d d d d d d d d d d d d d d d
1110 d d d d d d d d d d d d d d d d
1111 d d d d d d d d d d d d d d d d
J3 K 3 J2 K 2 J1 K 1 J0 K 0

(c )

Figure 8.37 (c)

Realization of the BCD Counter Design
y2ky3k
y1ky0k 00 01 11 10 00 01 11 10

00 0 d d 0 0 d d 0

01 0 d d 0 0 d d 0

11 0 d d d 1 d d d

10 0 d d d 0 d d d

x = 0 x = 1
(d )

y0 J0
y1 J1
y2 J2 C
y3 J3 C
C K
C K
0
K 1
K 2
3

C lo c k

L ig h ts

(e )

Figure 8.37 (d) and (e)

 K-map For Y1 in Example 8.16

y
y3 y3

0 0 d 0 0 0 d 0

0 0 d 0 1 1 d 0
y0 y0
1 1 d d 0 0 d d
y1 y1
1 1 d d 1 1 d d

y2 y2

Figure 8.38
Robot Controller Floor Plan -- Example 8.17

E x it

B o tto m v ie w
M o v a b le of robot
b lo c k s S en sor
(X )

R obot

W h e e ls

Figure 8.39
 Robot Controller Design
x x
0 /0 0 1 /0 1 y1y 2
1 /0 1 y 1y2 0 1 0 1
A B A A /0 0 B /0 1 00 0 0 /0 0 0 1 /0 1
B C /0 0 B /0 1 01 1 1 /0 0 0 1 /0 1
0 /0 0 X /Z 1/Z 2
0 /0 0
C C /0 0 D /1 0 11 1 1 /0 0 1 0 /1 0
D C D A /0 0 D /1 0 10 0 0 /0 0 1 0 /1 0
1 /1 0 N S /z1z2 Y 1 Y 2 /z 1z 2
1 /1 0 0 /0 0
(a ) (b ) (c )

x x x x
y 1y2 0 1 y1y2 0 1 y1y2 0 1 y1y 2 0 1
00 0 0 00 0 1 00 0 0 00 0 1

01 0 0 01 0 1 01 1 0 01 1 1

11 0 1 11 0 0 11 1 1 11 1 0

10 0 1 10 0 0 10 0 1 10 0 0
z1 z2 Y 1
Y 2
(d ) (e )

Figure 8.40 (a) -- (e)

Robot Controller Realization
x z1

z2

Q 1
J1

Q 1 K 1

Q 2
J2

Q 2 K 2

C lo c k
(f)

Figure 8.40 (f)

Candy Machine Controller Design -- Example 8.18
R R e le a se
N candy
C o in C o n tr o l
d e te c to r D u n it
R e le a se
C change
(a )

N D /R C

0 0 /0 0 0 0 /0 0
1 0 /0 0
0
0 1 /0 0 5
1 0 /1 0 , 0 1 /0 0
0 1 /1 1
1 0 /0 0
0 1 /1 0
0 0 /0 0 15
10
1 0 /0 0
0 0 /0 0

(b )

Figure 8.41
 Algorithmic State Machines (ASMs)

S ta te _ N a m e
M e a ly
M o o r e o u tp u ts 0 1 o u tp u ts
In p u t

(a ) (b ) (c )

Figure 8.42
 ASM Representation of a Mealy Machine
z = 0 A

1 /0
0 1 A
X 0 /0 B
0 /1
X /Y
z = 0 0 /0
1 /1 1 /0

(b )
B z = 1

1 0
X

z = 0

z = 0 C z = 1
Figure 8.43

0 1
X
(a )
ASM Representation of a Moore Machine

A
z = 0

0 1
X

1
A /0
0 1 B /1
B
z = 1 0
1 0

0 1 C /0
X
(b )

C
z = 0

0
X
1 Figure 8.44
(a )
Eight-Bit Two’s Complementer ASM --
Example 8.19

A
z = 0 L o o k fo r
fir st 1 b it

0 x
1

z = 1

B
z = 1 C o m p le m e n t z = 0
r e m a in in g b its

0 1
x

Figure 8.45
 Binary Multiplier Controller -- Example 8.20
S ta r t
A 0
R e g is te r A R e g is te r Q 4 M M u ltip lie r
M u lip lie r Q M u ltip lic a n d
C N T 0

0
2 -b it
4 c ou n te r A dd
4 4
C 1
out
Q 0 A A + M
Sum 4
0
4 P roduct
A dder Q 0
C 0
S h ift
H a lt S h ift r ig h t A : Q
C o n tr ol C N T C N T + 1
u n it
4
M u lip lic a n d H a lt
R e g is te r M
0 1
S ta r t A d d S h ift C 0 H a lt 1
R e g is te r c o n tr o l s ig n a ls
(a ) (b )

Figure 8.46
 One-Hot State Assignments

Sequential Assignment One-hot Assignment

State y1y0 y3y2 y1y0
A 00 0001
B 01 0010
C 10 0100
D 11 1000

Table 8.1
ASM Design Using One-Hot State Assignments
C lo c k

D A C

Q A
A
B e g in C lo c k S ta te A

S ta te A D C
A D B C
S ta te B
Q A Q B
A B
S ta te B

...

...
...
D B C
D C C
S ta te C
Q B
Q C
B
C
(a ) (b )

Figure 8.47 (a) -- (b)

ASM Design Using One-Hot Assignments (con’t)
C lo c k

S ta te A D A C

Q A
M oore
A o u tp u t
0 1 x
In p u ts

z = 1 M e a ly
S ta te B z ou tp u t

D D
A C A C
S ta te C
Q B Q C

(c )

Figure 8.47 (c)

One-hot Design of A Multiplier Controller --
Example 8.21
B e g in C lo c k

D A C
B e g in C lo c k
Q A
S ta rt

Q D
0 A C

Q A
x
D B C

Q B
A dd z

D C C
D B C
Q C
S h ift Q B
C 0 S ta rt

D D C
(b )
Q D
H a lt
(a )

Figure 8.48
Incompletely Specified Circuits -- Detonator
(Example 8.22)

1 /0 1 /0 1 /0 1 /1
x D e to n a to r z A B C D -
0 /0
(a ) (b )
x
0 1
A A /0 B /0
B -/- C /0
C -/- D /0
D -/- -/1
(c )

Figure 8.49
 Detonator Example K-maps

x y 2y x y 2y x y 2y x
y 2y 1 0 1 1 0 1 1 0 1 1 0 1
00 00 01 00 0 0 00 0 0 00 0 1

01 dd 10 01 d 0 01 d 1 01 d 1

11 dd dd 11 d 1 11 d d 11 d d

10 dd 11 10 d 0 10 d 0 10 d 1

y 2k+1y 1k+1 z T 2 T 1

Figure 8.50
 Detonator Realization

z
y1 y2
x T 1
Q T 2
Q
C Q C Q

C lo c k

Figure 8.51
Sate Assignments and Circuit Realization
x x
y 2y 1 0 1 y 2y 1 0 1

00 1 0 00 1 d 0 0
x
y 2y 1 0 1
01 0 0 01 1 0 0 0
00 0 d /1 0 0 /0
01 1 0 /0 0 0 /0 11 0 1 11 d d 1 0
11 d d /0 1 0 /1
10 d 1 10 d d 0 1
10 d d /d 0 1 /1
Y 2Y 1/z z D 2
D 1
D 2
D 1
(a ) (b ) (c )

x x x
y 2y 1 y 2y 1 y 2y 1
0 1 0 1 0 1

00 0 d 0 0 00 0 d 0 d 00 d d 0 d

01 1 1 0 1 01 1 d 0 d 01 d 1 d 1

11 d d 0 1 11 d d d 0 11 d d d 1

10 d d 1 1 10 d d d 1 10 d d 1 1

T 2
T 1
T 2
T 1
J2 K 2
J2 K 2
J1 K 1
J 1
K 1

(d ) (e )

Figure 8.52