Chapter 8 -- Analysis and Synthesis of

Synchronous Sequential Circuits

The Synchronous Sequential Circuit Model

x1 z1

...

...
xn C o m b in a tio n a l zm
lo gic

y1 ... yr Yr ... Y1

M em o ry

C lo ck

Figure 8.1
Mealy Machine Model

A
1 /1 1 /0
0 /1
0 /0 0 /0 1 /0
B C
X /Z
(a )

P resen t In p u t x
sta te 0 1
A B /1 C /0
B B /0 A /1
C A /0 C /0
N ex t sta te/o u tp u t
(b )

Figure 8.2
 Mealy Machine Timing Diagram -- Example 8.1

T0 T1 T2 T3 T4 T5
C lo c k
S ta te A B A C A C A

In p u t x 0 1 1 0 1 0
O u tp u t z 1 1 0 0 0 0

Figure 8.3
Moore Machine Model
0
1
W /0 X /1
0 0
1 1

Y /0
(a )

P resen t In p u t x
sta te 0 1 O u tp u ts
W Y X 0
X X Y 1
Y X W 0

(b )

Figure 8.4
Moore Machine Timing Diagram -- Example 8.2

T0 T1 T2 T3 T4 T5

C lock
S ta te W Y W X X Y X
In p u t x 0 1 1 0 1 0

O u tp u t z 0 0 0 1 1 0

Figure 8.5
Analysis of Sequential Circuit State Diagrams --
Example 8.3

x /z
0 /0 1 /0 1 /1

1 /0 0 /0
00 01 11

0 /0

Figure 8.6
 Timing Diagram for Example 8.3

C lo ck
x 0 0 1 1 1 0 1 1 0 0

y1 0 0 0 0 0 0 1 1 1 0
0
y2 0 0 0 1 1 1 1 1 1
z 0 0 0 0 0 0 1 1 0 0

Figure 8.7
Analysis of Sequential Circuit Logic Diagrams
C o m b in a tio n a l lo g ic

y Y
Q D

y
Q C C lo ck

M em o ry
(a )
Dt


C

0 1 2 3 4 t/D t
(b )

Figure 8.8
 Timing Diagram for Figure 8.8 (a)

C lo ck

x 0 1 1 0 1 0 0 0

y 0 0 1 0 0 1 1 1

Y=D 0 1 0 0 1 1 1 1

z 0 0 1 0 0 0 0 0
0 1 2 3 4 5 6 7 8 t/D t
G litch

Figure 8.9
State Table and State Diagram for Figure 8.8 (a)

In p u t x k In p u t x k In p u t xk
P resen t 0 1 P resen t 0 1 P resen t 0 1
sta te sta te sta te
0 0 0/0 1 /0 A A /0 B /0
yk yk
1 1 1/0 0 /1 B B /0 A /1

N ex t sta te/o u tp u t N ex t sta te/o u tp u t

(a ) (b ) (c)
x/
z
0 /0 0 /0
1 /0
A B
1 /1
(d )

Figure 8.10
 K-Maps for Circuit of Figure 8.8 (a)

xk xk In p u t xk
0 1 0 1 P resen t 0 1
sta te
0 0 1 0 0 0 A A /0 B /0
k k
y y
1 1 0 1 0 1 B B /0 A /1

y k + 1 /z k
(a ) (b ) (c)

Figure 8.11
Synchronous Sequential Circuit with T Flip-Flop --
Example 8.4

z
x

y
Q T
y
Q C C lo ck

Figure 8.12
 Timing Diagram for Example 8.4

C lo ck
x 0 1 1 0 1 0 0 0

y 0 1 0 0 1 0 1 1

T
z 0 1 0 0 1 0 0 0
0 1 2 3 4 5 6 7 8

Figure 8.13
State Table and State Diagram for Example 8.4

xk xk xk
yk 0 1 yk 0 0 1 P resen t 0 1
sta te
1 1 /0 0 /0 A B /0 A /0
0 1 1 /0 0 /1 B B /0 A /1
y k + 1 /z k y k + 1 /z k N ex t sta te/o u tp u t
(a ) (b ) (c)
x/
z
1 /0
0/0
A B
1 /1 0 /0
(d )

Figure 8.14
 K-Maps for Example 8.4
xk xk xk
0 1 0 1 0 1

0 0 0 0 1 0 0 1* 0
k k k
y y y
1 0 1 1 0 1 1 1 0*

zk Tk yk + 1
(a ) (b ) (c)

xk
0 1

0 1/0 0 /0
yk
1 1/0 0 /1

y k + 1 /z k
(d )

Figure 8.15
Synchronous Sequential Circuit with JK Flip-flops --
Example 8.5
z

J1 Q y1
C
K1 Q
y1

J2 Q y2
C
K2 Q y2

C lo ck

Figure 8.16
Timing Diagram and State Table for Example 8.5
C
x 0 0 1 1 1 1 0 0
y1 1 0 0 0 1 1 1 0
y2 0 0 0 1 0 1 1 0
J1 = xy2

K1 = x
J2 = x
K 2 = x + y1
z = x y1 y2 0 0 0 0 0 1 0 0

(a )

x
y1 y2 0 1

0 0 0 0/0 0 1/0

0 1 0 0/0 1 0/0

1 1 0 0/0 1 1/1

1 0 0 0/0 1 1/0

(b )

Figure 8.17
K-Maps for Example 8.5
x x
y1 y2 0 1 y1 y2 0 1

00 0 0 00 1 0

01 0 1 01 1 0

11 0 1 11 1 0

10 0 0 10 1 0

J1 K1

x x x
y1 y2 0 1 y1 y2 0 1 y1 y2 0 1

00 0 1 00 1 1 00 0 0

01 0 1 01 1 1 01 0 0

11 0 1 11 1 0 11 0 1

10 0 1 10 1 0 10 0 0

J2 K2 z

Figure 8.18
Generating the State Table From K-maps --
Example 8.5
x
y1 y2 0 1

00 01 01 00 11
x x
y1 y2 y1 y2
0 1 0 1
01 01 01 10 11
00 00 01 00 0 0/0 01 /0
11 01 01 10 10 01 00 10 01 0 0/0 10 /0
11 00 11 11 0 0/0 11 /1
10 01 01 00 10
10 00 11 10 0 0/0 11 /0
J1 K 1 J2 K 2 J1 K 1 J2 K2 Y1 Y2 Y 1 Y 2 /z
(a ) (b ) (c )

Figure 8.19
Synchronous Sequential Circuit Synthesis
x
0 1
A 1/0 B
A D /0 B /0
1 /1
0 /0 1 /0 B D /0 C /0
0 /0 1 /0
0 /0 D C D /0 B /0
0 /0 C
D D /0 A /1

(a ) C om p letely sp ec ified circ u it

x
A B 0 1
1 /1 0 /- 0 /0
A B /- -/1
1 /-
0 /- 1 /1 B B /0 C /1
C C A /- A /-

(b ) In com p le tely sp ec ifie d c ircu it

Figure 8.20
Introductory Synthesis Example -- Example 8.6
x

z
x x
0 1 S tate
y1 y2 y1 y2 0 1
A A /0 B /0 A 0 0 00 00 /0 0 1/0
B A /0 C /1 B 0 1 01 00 /0 1 1/1
C B /0 D /0 C 1 1 11 01 /0 1 0/0
D C /1 D /0 D 1 0 10 11 /1 1 0/0
(b ) S tate (c)T rYa1n Ysition
2 /z
(a ) S tate ta b le assign m en t ta b le

x x x
y1 y2 0 1 y1 y2 0 1 y1 y2 0 1

00 0 0 00 0 0 00 0 1 y1
Q D1
y1
01 0 1 01 0 1 01 0 1 Q C

11 0 0 11 0 1 11 1 0
y2
Q D2
10 10 10 y2
1 0 1 1 1 0 Q C C lock
z D 1 (= Y 1 ) D 2 (= Y 2 )
(d ) O u tp u t K -m ap (e) E xcitation K -m ap s (f) L ogic d ia gr a m

Figure 8.21
Flip-flop Input Tables -- Example 8.6
S ta te R eq u ired S ta te R eq u ir e d
tra n sition s in p u ts tra n sition s in p u ts
Q (t) Q (t + e) D (t) Q (t) Q (t + e) S (t) R (t)
0 0 0 0 0 0 d
0 1 1 0 1 1 0
1 0 0 1 0 0 1
1 1 1 1 1 d 0
(a ) D flip -flop (b ) C locked S R

S ta te R eq u ired S ta te R eq u ir e d
tra n sition s in p u ts tra n sition s in p u ts
Q (t) Q (t + e) T (t) Q (t) Q (t + e) J (t) K (t)
0 0 0 0 0 0 d
0 1 1 0 1 1 d
1 0 1 1 0 d 1
1 1 0 1 1 d 0
(c) C locked T flip -flop (d ) C locked JK flip -flop

Figure 8.22
Generating the JK Flip-flop Excitation Maps --
Example 8.7
x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1
0 0 0 0/0 0 1/0 00 0d 0d 00 0d 1d
0 1 0 0/0 1 1/1 01 0d 1d 01 d1 d0
1 1 0 1/0 1 0/0 11 d1 d0 11 d0 d1
1 0 1 1/1 1 0/0 10 d0 d0 10 1d 0d
Y 1 Y 2 /z J 1K 1 J2K 2
(a) T ra n sition ta b le (b ) E x cita tion ta b le

x x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1 y1y2 0 1

00 0 0 00 d d 00 0 1 00 d d

01 0 1 01 d d 01 d d 01 1 0

11 d d 11 1 0 11 d d 11 0 1

10 d d 10 0 0 10 1 0 10 d d

J1 K1 J2 K2
(c ) E x cita tion m a p s

Figure 8.23
Clocked JK Flip-Flop Implementation --
Example 8.7
x

y1
Q J1
C
y1
Q K1

y2
Q J2
C
y2
Q K2

C lock

Figure 8.24
Application Equation Method for Deriving
Excitation Equations -- Example 8.8
x x
y1 y2 0 1 y1 y2 0 1

00 0 0 00 0 1

01 0 1 01 0 1
y2
11 0 1 11 1 0
y1
10 1 1 10 1 0

Y1 Y2

Figure 8.25
Sequence Recognizer for 01 Sequence --
Example 8.9

1/0 1/0 0/0

A A B

(a) (b)

1/0 0/0 0/0 1/0 0/0 0/0

A B A B
1/1
(c) (d)

Figure 8.26
Synthesis of the 01 Recognizer with SR Flip-flops
x x x
0 1 yk 0 1 yk 0 1
A B /0 A /0 0 1 0 0 0 0

B B /0 A /1 1 1 0 1 0 1

yk + 1 z
(a) State table (b ) T ransition table and output m ap

x x x S Q yk
yk 0 1 yk 0 1 C
0 0 R Q
1 0 0 d

1 d 0 1 0 1
C lock
S R
(c) E xcitation m aps
(d) L ogic diagram z

C lock
x 0 1 01 01
S= x 1 0 0 0 1 0 1 1 0 0 0
R = x 0 1 1 1 0 1 0 0 1 1 1
y
z

(e) T im ing diagram

Figure 8.27
Realization of 01 Recognizer with T Flip-flops
x
yk 0 1 x
T Q y
0 1 0
C Q
1 0 1

T C lock
(a ) C locked T flip -flop (b ) C locked T flip -flop
excita tion m a p im p lem en ta tion

x x
yk 0 1 yk 0 1

0 1 0 0 d d

1 d d 1 0 1

J K
(c) C locked J K excitation m ap s

Figure 8.28
Design of a Recognizer for the Sequence 1111 --
Example 8.11
0/0 1/1 x
0/0 0 1
0/0
A B C D A A /0 B /0
1/0 1 /0 1/0
B A /0 C /0
0 /0
D A /0 D /1
(a ) State diagram
C A /0 D /0

(b ) State table

x x
y 1ky 2k
y 1ky 2k 0 1 0 1
00 00 01 00 0 0

01 00 10 01 0 0

11 00 11 11 0 1

10 00 11 10 0 0

y 1 k+ 1 y 2 k + 1 z
(c) T ran sition tab le (d) O utp ut m ap

Figure 8.29
SR Realization of the 1111 Recognizer
x x
y 1 ky 2 k 0 1 y 1 ky 2 k 0 1
00 0 0 00 d d

01 0 1 01 d 0

11 0 d 11 1 0

10 0 d 10 1 0

S1 R1

x x
y 1 ky 2 k 0 1 y 1 ky 2 k 0 1
00 0 1 00 d 1

01 0 0 01 1 1

11 0 d 11 1 0

10 0 1 10 d 0

S2 R2

Figure 8.30
Clocked T and JK Realizations of the 1111
Recognizer
x x
y 1 ky 2k y 1ky 2k
0 1 0 1
00 0 0 00 0 1

01 0 1 01 1 1

11 1 0 11 1 0

10 1 0 10 0 1

T(a) T
1 C lock ed T excitation m aps 2

x x x x
y 1ky 2k y 1 ky 2k y 1ky 2k y 1ky 2k
0 1 0 1 0 1 0 1
00 0 0 00 d d 00 0 1 00 d d

01 0 1 01 d d 01 d d 01 1 1

11 d d 11 1 0 11 d d 11 1 0

10 d d 10 1 0 10 0 1 10 d d

J1 K J K2
(b )1 C lock ed JK excita tion m aps 2
x x
y1 y2 0 1 y1 y2 0 1
00 0 0 00 0 1

01 0 1 01 0 0
y2
11 0 1 11 0 1
y1
10 0 1 10 0 1

Y1 Y2
(c) E xcitation K -m aps

Figure 8.31
Clocked JK Flip-Flop Realization of a 1111
Recognizer
C lock
y1
J1 Q
C
x K1 Q

J2 Q
y2
C
K2 Q

Figure 8.32
Design of a 0010 Recognizer
0 /0 0/0 1 /0 0 /1 0 /0 0 /0 1 /0 0/1
A B C D E A B C D E
0 /0

G C om e h ere for an G
in cor re ct in p u t x = 0 1 /0 1/0
1 /0 1 /0
F C om e h ere for an F
in cor re ct in p u t x = 1
(a ) (b )
0/0
0 /0 0 /0 1 /0 0/1
0 /0 A B C D E
0/0 0 /0 1 /0 0/1 0 /0
0/0
A B C D E 0 /0
0 /0 1 /0 G
1 /0
1 /0 1 /0 1/0
1 /0 G F
1 /0
1 /0 1 /0
F
1 /0
(c ) (d )

x
0 1
A B /0 F /0 x 0 /0
B C /0 F /0 0 1
C G /0 D /0 A B /0 A /0 1 /0 G
D E /1 F /0 B C /0 A /0 1 /0
0 /0
1 /0
E C /0 F /0 C G /0 D /0 0 /0 1 /0
A B C D
0 /0
F B /0 F /0 D B /1 A /0 0 /1
G G /0 F /0 G G /0 A /0
1 /0
(e) (f) (g )

Figure 8.33
 Design of a Serial Binary Adder

ai a i b i /s i
S h ift register A 0 0/0 0 1/0
S eria l si 0 1/1 11/0 1 0/0
bi a d d er 1 0/1 0 1 1 1/1
S h ift register B c i-1 = 0 00/1 c i-1 = 1
(b )

(a)

ai
bi Si

ai bi c i-1 ci si
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 Ci C i-1
D Q
1 0 0 0 1
1 0 1 1 0 C
1 1 0 1 0
1 1 1 1 1
C lock

(c) (d )

Figure 8.34
Design of a Four-State Up/Down Counter
x x
z=0 z=1 0 1 y 1ky 2k 0 1
0 0 1 0 1/0 3 /0 00 01 11
1
1 2/1 0 /1 01 10 00
0 1 1 0
2 3/2 1 /2 11 00 10
1
3 0 2 3 0/3 2 /3 10 11 01
z=3 z=2 y1k + 1y2k + 1
(a) Sta te d iag ram (b ) S tate tab le (c) T ra nsition tab le

x x
y1y2 0 1 y1y2 0 1

00 0 d 1 d 00 1 d 1 d

01 1 d 0 d 01 d 1 d 1

11 d 1 d 0 11 d 1 d 1

10 d 0 d 1 10 1 d 1 d

J1 K1 J1 K1 J2 K2 J2 K2
(d ) E xcitation m a ps

Figure 8.35
An Implementation of the Up/Down Counter

C lock
y1
x J1 Q
C
K1 Q

J1 Q
y2
1 C
K1 Q LEDs

Figure 8.36
Design a BCD Counter
x
y3k y2ky1ky0k 0 1
0000 0000 0001
0001 0001 0010
x
0010 0010 0011
0 1
0011 0011 0100
0 0 1
0100 0100 0101
1 1 2
0101 0101 0110
2 2 3
0110 0110 0111
3 3 4
0111 0111 1000
4 4 5
1000 1000 1001
5 5 6
1001 1001 0000
6 6 7
1010 dddd dddd
7 7 8
1011 dddd dddd
8 8 9
1100 dddd dddd
9 9 0
1101 dddd dddd
(a )
1110 dddd dddd
1111 dddd dddd

y 3k + 1y 2k + 1y 1k + 1y 0k + 1

(b )

Figure 8.37 (a) and (b)

 Design of the BCD Counter (con’t)
x x x x x x x x
y3k y2ky1ky0k 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0000 0 0 d d 0 0 d d 0 0 d d 0 1 d d
0001 0 0 d d 0 0 d d 0 1 d d d d 0 1
0010 0 0 d d 0 0 d d d d 0 0 0 1 d d
0011 0 0 d d 0 1 d d d d 0 1 d d 0 1
0100 0 0 d d d d 0 0 0 0 d d 0 1 d d
0101 0 0 d d d d 0 0 0 1 d d d d 0 1
0110 0 0 d d d d 0 0 d d 0 0 0 1 d d
0111 0 1 d d d d 0 1 d d 0 1 d d 0 1
1000 d d 0 0 0 0 d d 0 0 d d 0 1 d d
1001 d d 0 1 0 0 d d 0 0 d d d d 0 1
1010 d d d d d d d d d d d d d d d d
1011 d d d d d d d d d d d d d d d d
1100 d d d d d d d d d d d d d d d d
1101 d d d d d d d d d d d d d d d d
1110 d d d d d d d d d d d d d d d d
1111 d d d d d d d d d d d d d d d d
J3 K3 J2 K2 J1 K1 J0 K0
(c)

Figure 8.37 (c)

Realization of the BCD Counter Design
y2ky3k
y1ky0k 00 01 11 10 00 01 11 10

00 0 d d 0 0 d d 0

01 0 d d 0 0 d d 0

11 0 d d d 1 d d d

10 0 d d d 0 d d d

x=0 x=1
(d )

y0 J0
y1 J1
y2 J2 C
y3 J3 C
C K0
C K1
K2
K3

C lock

L igh ts

(e )

Figure 8.37 (d) and (e)

 K-map For Y1 in Example 8.16

y
y3 y3

0 0 d 0 0 0 d 0

0 0 d 0 1 1 d 0
y0 y0
1 1 d d 0 0 d d
y1 y1
1 1 d d 1 1 d d

y2 y2

Figure 8.38
Robot Controller Floor Plan -- Example 8.17

E xit

B ottom view
M ovable of robot
b lock s Sen sor
(X )

R obot

W heels

Figure 8.39
 Robot Controller -- Control Algorithm
and State Specifications

• Control Algorithm
1. Start;
2. Obstacle detected (x =1): turn right until no obstacle detected (z2=1);
3. Obstacle detected (x =1): turn left until no obstacle detected (z1 =1);
4. Repeat from 2.
• State specification
– State A -- no obstacle detected, last turn was left
– State B -- obstacle detected, turn right
– State C -- no obstacle detected, last turn was right
– State D -- obstacle detected, turn left
 Robot Controller Design
x x
0/00 1/01 y1y2
1/01 y1y2 0 1 0 1
A B A A /00 B /01 00 00/00 01/01
B C /00 B /01 01 11/00 01/01
0/00 X /Z 1 /Z 2 0/00
C C /00 D /10 11 11/00 10/10
D C D A /00 D /10 10 00/00 10/10
1/10 N S /z 1 z 2 Y 1 Y 2 /z 1 z 2
1/10 0/00
(a) (b) (c)

x x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1 y1y2 0 1
00 0 0 00 0 1 00 0 0 00 0 1

01 0 0 01 0 1 01 1 0 01 1 1

11 0 1 11 0 0 11 1 1 11 1 0

10 0 1 10 0 0 10 0 1 10 0 0
z1 z2 Y1 Y2
(d ) (e)

Figure 8.40 (a) -- (e)

Robot Controller Realization
x z1

z2

Q1 J1

Q1 K1

Q2 J2

Q2 K2

C lock
(f)

Figure 8.40 (f)

Candy Machine Controller Design -- Example 8.18
R R elease
N candy
C oin C ontrol
detector D un it
R elease
C change
(a)

N D /R C

00/00 00/00
10/00
0
01/00 5
10/10, 01/00
01/11
10/00
01/10
00/00 15
10
10/00
00/00

(b )

Figure 8.41
 Algorithmic State Machines (ASMs)

State_N am e
M ealy
M oore outputs 0 1 outputs
Input

(a) (b) (c)

Figure 8.42
ASM Representation of a Mealy Machine
z=0 A

1/0
0 1 A
X 0/0 B
0/1
X /Y
z=0 0/0
1/1 1/0

(b)
B z=1

1 0
X

z=0

z=0 C z=1
Figure 8.43

0 1
X
(a )
ASM Representation of a Moore Machine

A
z=0

0 1
X

1
A /0
0 1 B /1
B
z=1 0
1 0

0 1 C /0
X
(b )

C
z=0

0
X
1 Figure 8.44
(a )
Eight-Bit Two’s Complementer ASM --
Example 8.19

A
z=0 L ook for
first 1 bit

0 x
1

z=1

B
z=1 C om plem ent z=0
rem aining bits

0 1
x

Figure 8.45
 Binary Multiplier Controller -- Example 8.20
S tar t
A 0
R e g ister A R e g iste r Q 4 M M u ltip lie r
M u lip lier Q M u ltip lic a n d
CNT 0

0
2 -b it
4 cou n ter Add
4 4
C out 1
Q0 A A +M
Sum 4
0
4 P r od u c t
A d d er Q0 C0
S h ift
H a lt S h ift rig h t A : Q
C on trol CNT CNT + 1
u n it
4
M u lip lica n d H alt
R e g iste r M
0 1
S tar t A d d S h ift C0 H a lt 1
R eg iste r con trol sig n a ls
(a ) (b )

Figure 8.46
 One-Hot State Assignments

Sequential Assignment One-hot Assignment

State y1y0 y3y2 y1y0
A 00 0001
B 01 0010
C 10 0100
D 11 1000

Table 8.1
ASM Design Using One-Hot State Assignments
C lock

DA
C

QA
A
B eg in C lock S ta te A

S ta te A DA C
DB C
S ta te B
QA
QB
A B
S ta te B

...

...
...
DB C
DC C
S ta te C
QB
QC
B
C
(a) (b)

Figure 8.47 (a) -- (b)

ASM Design Using One-Hot Assignments (con’t)
C lock

S tate A DA
C

QA
M oore
A ou tp u t
0 1 x
In p u ts

z=1 M ealy
S ta te B z ou tpu t

DA DA
C C
S tate C
QB QC

(c)

Figure 8.47 (c)

One-hot Design of A Multiplier Controller --
Example 8.21
B eg in C lock

DA
C
B eg in C lock
QA
S ta rt

Q0 DA
C

QA
x
DB
C

QB
A dd z

DC
C
DB
C
QC
S h ift QB
C0 S ta r t

DD
C
(b )
QD
H a lt
(a )

Figure 8.48
Incompletely Specified Circuits -- Detonator
(Example 8.22)

1/0 1/0 1/0 1/1

x D etonator z A B C D -
0 /0
(a) (b)
x
0 1
A A /0 B /0
B -/- C /0
C -/- D /0
D -/- -/1
(c)

Figure 8.49
 Detonator Example K-maps

x y 2y x y 2y x y 2y x
y 2y 1 0 1 1 0 1 1 0 1 1 0 1
00 00 01 00 0 0 00 0 0 00 0 1

01 dd 10 01 d 0 01 d 1 01 d 1

11 dd dd 11 d 1 11 d d 11 d d

10 dd 11 10 d 0 10 d 0 10 d 1

y 2 k + 1 y 1 k+ 1 z T2 T1

Figure 8.50
 Detonator Realization

z
y1 y2
x T1 Q T2 Q
C Q C Q

C lock

Figure 8.51
State Assignments and Circuit Realization
x x
y 2y 1 0 1 y 2y 1 0 1

00 1 0 00 1 d 0 0
x
y2y1 0 1
01 0 0 01 1 0 0 0
00 0 d /1 00 /0
01 1 0 /0 00 /0 11 0 1 11 d d 1 0
11 d d /0 10 /1
10 d 1 10 d d 0 1
10 d d /d 01 /1
Y 2 Y 1 /z z D2 D1 D2 D1
(a ) (b ) (c)

x x x
y2y1 y 2y 1 y 2y 1
0 1 0 1 0 1

00 0 d 0 0 00 0 d 0 d 00 d d 0 d

01 1 1 0 1 01 1 d 0 d 01 d 1 d 1

11 d d 0 1 11 d d d 0 11 d d d 1

10 d d 1 1 10 d d d 1 10 d d 1 1

T2 T1 T2 T1 J2 K2 J2 K2 J1 K1 J1 K1
(d ) (e)

Figure 8.52
 Factors Influencing the Complexity of a
Synchronous Sequential Circuit Realization
• Number of input lines
• Number of output lines
• Number of states
• Presence of don’t care conditions
• Types of flip flop used
• State assignment
• Types of logic elements available