EE-307

FPGA BASED SYSTEM DESIGN

Spring 2015

Verilog
Combinational Logic in Verilog

Lecture # 08
2

Avoiding unwanted Latches

in Combinational Circuit
module Decoder1(
input [1:0] opcode,
output reg [1:0] decoder_op);
always @ (opcode) Good Straight Coding
begin
3
case(opcode)
2'b01 : decoder_op = 2'b01;
2'b00 : decoder_op = 2'b01;
2'b11 : decoder_op = 2'b10;
2'b10 : decoder_op = 2'b01;
endcase
end
endmodule
module Decoder1( module Decoder2(
input [1:0] opcode, input [1:0] opcode,
output reg [1:0] decoder_op); output reg [1:0] decoder_op);
always @ (opcode) always @ (opcode)
begin begin
case(opcode) case(opcode)
2'b01 : decoder_op = 2'b01; 2'b01 : decoder_op = 2'b01;
2'b00 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01;
2'b11 : decoder_op = 2'b10; 2'b11 : decoder_op = 2'b10;
2'b10 : decoder_op = 2'b01; 2'b10 : decoder_op[0] = 1'b1;
endcase endcase
end end
endmodule endmodule
module Decoder2(
input [1:0] opcode,
output reg [1:0] decoder_op);
always @ (opcode)
begin
case(opcode)
2'b01 : decoder_op = 2'b01;
Missed Assignment to one output signal:
2'b00 : decoder_op = 2'b01;
2'b11 : decoder_op = 2'b10;
2'b10 : decoder_op[0] = 1'b1; Creates -> Latch
endcase
end
endmodule

D Q

Gate
module Decoder2( Missed Assignment to one output signal
input [1:0] opcode,
output reg [1:0] decoder_op);
always @ (opcode) Decoder_op[0]
begin
6
case(opcode)
Note the overhead of a LATCH
2'b01 : decoder_op = 2'b01; • You need to generate the logic for
2'b00 : decoder_op = 2'b01; Gate/Enable Signal
2'b11 : decoder_op = 2'b10; • We NEED to use the previous value of 0
2'b10 : decoder_op[0] = 1'b1; decoder_op[1] when opcode = 2’b10
endcase
end
endmodule

D Q

LD is a transparent latch.  Its Q output

Gate follows the D input while the gate is
active.  Q remains in its last state while
gate is inactive.
module Decoder(
input [1:0] opcode,
output reg [1:0] decoder_op
);
always
7 @ (opcode)
begin
case(opcode) Missed Case
2'b01 : decoder_op = 2'b01;
2'b00 : decoder_op = 2'b01;
2'b11 : decoder_op = 2'b10;
endcase
end
endmodule
How many latches this time ?
module Decoder(
input [1:0] opcode,
output reg [1:0] decoder_op
);
always @ (opcode)
begin
8

decoder_op = 2'b01;
case(opcode) Initialize – To account for missed assignments.
2'b01 : decoder_op = 2'b01; And a way to provide default values if an
2'b00 : decoder_op = 2'b01; assignment is missed.
2'b11 : decoder_op = 2'b10; WARNING : This is not S/W initialization
endcase
end
endmodule
module Decoder(
input [1:0] opcode,
output reg [1:0] decoder_op
);
always @ (opcode)
begin
9
decoder_op = 2'b01;
case(opcode) Best Coding Practice
2'b01 : decoder_op = 2'b01;
2'b00 : decoder_op[0] = 1'b0; Initialize for Missed Assignments
2'b11 : decoder_op = 2'b10; Default for Missed Cases
default : decoder_op = 2'b01;
endcase
end
endmodule
 In summary...
10

 Initialize before the conditional construct in the always block

 This avoids latches for the situation where we are not assigning values
to a particular reg/signal for a particular condition
 Always put DEFAULT (for cases) & ELSE (for if else)
 This avoids latches that shall/may be inferred by synthesizer when we
miss/forget specifying a particular condition
 This may not be required for some synthesizers; but is a good practice.
 Though Synthesizers are getting intelligent
 Still better to follow best practices
 E.g. Some synthesizers; although they are able to extract Priority
Encoders they may not synthesize it
 Synthesis reports are good resource
 Comparison !!!
Cell Usage :
Cell Usage :
# BELS :2 Good Code # BELS :3
Not Good Code
# LUT2 :2 # LUT2 :3
# IO Buffers :4 # FlipFlops/Latches :1
# IBUF :2 # LD :1
# OBUF :2 # IO Buffers :4
# IBUF :2
===================== # OBUF :2
=====================
Slice Logic Utilization:
Number of Slice LUTs: 2 out of 19200 0% Slice Logic Utilization:
Number used as Logic: 2 out of 19200 0% Number of Slice LUTs: 3 out of 19200 0%
Number used as Logic: 3 out of 19200 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 2 Slice Logic Distribution:
Number with an unused Flip Flop: 2 out of 2 100% Number of LUT Flip Flop pairs used: 3
Number with an unused LUT: 0 out of 2 0% Number with an unused Flip Flop: 3 out of 3 100%
Number of fully used LUT-FF pairs: 0 out of 2 0% Number with an unused LUT: 0 out of 3 0%
Number of unique control sets: 0 Number of fully used LUT-FF pairs: 0 out of 3 0%
Number of unique control sets: 1
IO Utilization:
Number of IOs: 4 IO Utilization:
Number of bonded IOBs: 4 out of 220 1% Number of IOs: 4
Number of bonded IOBs: 4 out of 220 1%
IOB Flip Flops/Latches: 1
 Suggested Reading
12

 Suggested Reading
 <Samir Palnitkar> Verilog: Chapter 1-6
(Combinational circuits only)
 Verilog Tutorial
 http://www.asic-world.com/verilog/veritut.html
 HDL Coding Guidelines for Student Projects, Nestor,
J.A.; , IEEE Conference on Microelectronic Systems
Education (MSE), 2011