EE 312 :EmbeddedSystems

Assignment – 2
Devansh Singh
210108014

Design a 8 bit Arithmetic and Logic Unit in Verilog

The Arithmetic Logic Unit (ALU) serves as the foundational component of a

processor, tasked with executing arithmetic and logic functions. Comprising
combinatorial logic, it executes operations like Addition, Subtraction, and
Multiplication, as well as logic operations such as AND, OR, and NOT. Operands are
fetched from the register file or memory. The ALU reads two input operands, In A and
In B, and the desired operation is determined by the control input, Opcode.
Subsequently, the ALU performs the specified operation on In A and In B, generating
the output, Out. Importantly, the ALU updates various flag signals post-operation. It's
crucial to note that the ALU consists solely of combinatorial logic and lacks any
registers or latches.

The Arithmetic Unit encompasses three operations, namely:

1. Addition
2. Subtraction
3. Multiplication

Meanwhile, the Logical Unit comprises five functions:

1. Bitwise AND
2. Bitwise OR
3. Bitwise NAND
 4. Bitwise NOR
5. Bitwise XOR

The ALU updates conditional flags that the processor utilises for operations like
condition checking and branching. In this instance, two flags are employed:
1. Zero Flag: Set if all bits in the result data are zero.
2. Carry Out Flag: Set if the addition of the two operands results in a carry out.

Truth Table

The ALU works on 8-bit operands. It supports 8 instructions which are selected by the
3-bit Opcode.

Verilog Module :

The ALU receives a 3-bit Opcode, along with two 8-bit operands labelled Operand1
and Operand2. The outcome of the operation is conveyed through the 16-bit Result
port. Additionally, there are two flags: flagC for carry and flagZ for zero.
Verilog Code for the 8-bit ALU (ALU8bit.v) :

`timescale 1ns / 1ps

module ALU8bit( Opcode,
Operand1,
Operand2,
Result,
flagC,
flagZ
);
input [2:0] Opcode;
input [7:0] Operand1,
Operand2; output reg
[15:0] Result = 16'b0; output
reg flagC = 1'b0, flagZ = 1'b0;
parameter [2:0] ADD = 3'b000,
SUB = 3'b001,
MUL = 3'b010,
AND = 3'b011,
OR = 3'b100,
NAND = 3'b101,
NOR = 3'b110,
XOR = 3'b111; always @ (Opcode
or Operand1 or Operand2) begin
case (Opcode)
ADD: begin
 Result = Operand1 + Operand2;
flagC = Result[8]; flagZ = (Result
== 16'b0);
end
SUB: begin
Result = Operand1 - Operand2;
flagC = Result[8]; flagZ = (Result
== 16'b0);
end
MUL: begin
Result = Operand1 * Operand2;
flagZ = (Result == 16'b0);
end
AND: begin
Result = Operand1 & Operand2;
flagZ = (Result == 16'b0);
end
OR: begin
Result = Operand1 | Operand2;
flagZ = (Result == 16'b0);
end
NAND: begin
Result = ~(Operand1 & Operand2);
flagZ = (Result == 16'b0);
end
NOR: begin
Result = ~(Operand1 | Operand2);
flagZ = (Result == 16'b0);
end
XOR: begin
Result = Operand1 ^ Operand2;
flagZ = (Result == 16'b0);
end
default: begin
Result = 16'b0;
flagC = 1'b0;
flagZ = 1'b0;
 end
endcase
end
endmodule

This Verilog code defines an 8-bit Arithmetic Logic Unit (ALU) module that performs
various operations based on a 3-bit Opcode input. The module has inputs Operand1
and Operand2 (both 8 bits), and outputs Result (16 bits), flagC (carry flag), and flagZ
(zero flag).

The defined operations and their corresponding Opcode values are:

- ADD (Opcode: 000)
- SUB (Opcode: 001)
- MUL (Opcode: 010)
- AND (Opcode: 011)
- OR (Opcode: 100)
- NAND (Opcode: 101)
- NOR (Opcode: 110)
- XOR (Opcode: 111)

The `always @` block specifies that the outputs are updated whenever there is a
change in Opcode, Operand1, or Operand2. Inside the block, a `case` statement
selects the operation based on the Opcode, and the corresponding Result and flags
are computed.

Notable operations include addition (ADD), subtraction (SUB), multiplication (MUL),

bitwise AND (AND), bitwise OR (OR), bitwise NAND (NAND), bitwise NOR (NOR), and
bitwise XOR (XOR). The code also includes a default case where Result is set to zero,
and both flags are cleared if the Opcode does not match any specified operation.

Verilog Test Bench for 8-bit ALU (ALU8bit_tb.v) :

`timescale 1ns / 1ps

module ALU8bit_tb;
// Inputs reg [2:0]
Opcode; reg [7:0]
Operand1; reg
[7:0] Operand2; //
 Outputs wire [15:0]
Result; wire flagC;
wire flagZ;
//Temporary variable
reg [2:0] count = 3'd0;
// Instantiate the Unit Under Test (UUT)
ALU8bit uut (
.Opcode(Opcode),
.Operand1(Operand1),
.Operand2(Operand2),
.Result(Result),
.flagC(flagC),
.flagZ(flagZ)
);
initial begin
// Initialize Inputs
Opcode = 3'b0;
Operand1 = 8'd0;
Operand2 = 8'd0;
// Wait 100 ns for global reset to
finish
#100;
// Add stimulus here
Operand1 = 8'hAA;
Operand2 = 8'h55; for (count = 0; count < 8;
count = count + 1'b1) begin
Opcode = count;
#20;
end
end
endmodule

This Verilog test bench (ALU8bit_tb) is designed to simulate the behavior of the 8-bit
Arithmetic Logic Unit (ALU) module (ALU8bit). It provides inputs to the ALU module,
monitors its outputs, and includes a stimulus to test different operations.

Key components of the test bench:

Inputs and Outputs Declarations:

● reg [2:0] Opcode: 3-bit input for specifying the operation to be performed by the
ALU.
● reg [7:0] Operand1, Operand2: 8-bit inputs representing the operands for ALU
operations.
● wire [15:0] Result: 16-bit output for the result of ALU operations. ● wire
flagC, flagZ: Output wires for carry and zero flags.

Temporary Variable:
● reg [2:0] count: A 3-bit register used as a counter in the for loop.

Instantiation of ALU:
The ALU module (ALU8bit) is instantiated (uut) with connections to inputs and outputs.
Initialization in the initial block:
Initial values are set for Opcode, Operand1, and Operand2.
A delay of 100 ns is introduced to allow for any global reset to complete. Stimulus
Generation:

Stimulus is added to test different operations. In this case, Operand1 is set to 0xAA,
Operand2 is set to 0x55, and a loop is used to cycle through different Opcode values
from 0 to 7.

For each iteration of the loop, the Opcode is set, and a delay of 20 time units (#20) is
added to observe the output.

The test bench is designed to observe the behaviour of the ALU under different
combinations of Opcode, Operand1, and Operand2. The results can be analysed to
ensure that the ALU functions correctly for various operations.

Timing Diagram :