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Sequential Circuits
Redundant States in Sequential Circuits
(b ) (c)
In itia l In p u t S eq u en ces
S ta te 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 110 111
A 111 110 100 101 011 010 000 001
B 111 110 100 101 000 001 011 010
C 111 110 100 101 000 001 011 010
D 000 001 011 010 111 110 100 101
E 000 001 011 010 111 110 101 100
(d )
Figure 9.1
Equivalence Relations
• Inspection
• Partitioning
• Implication Tables
Finding Equivalent States By Inspection
x x
0 1 x 0 1 x
0 1 0 1
A B /0 C /1 A B /0 C /1 B/
A B /0 C /1 A
B C /0 A /1 B B /0 AB/1/ B0 / C /1
B C /0 A /1 B
C D /1 B /0 C D /1 B0 / A /1
C B /1 B /0 A0 /
D C /0 A /1 C 1 B /0
D D /0 1
(b ) (d )
(a ) (c)
x
0 1
B/
A 0 CA/1/
B D /0 B1 /
C DB/1/ A0 /
D 0 1
(e)
Figure 9.2
Finding Equivalent States by Partitioning
Partition blocks Action
Partition P0 (ABCDE)
Output for x = 0 11100 Separate (ABC) and (DE)
Output for x = 1 00011 Separate (ABC) and (DE)
Partition P1 (ABC) (DE)
Next state for x = 0 CCB DE
Next state for x = 1 BEE BA Separate (A) and (BC)
Partition P2 (A) (BC) (DE)
Next state for x = 0 C CB DE
Next state for x = 1 B EE BA Separate (D) and (E)
Partition P3 (A) (BC) (D) (E)
Next state for x = 0 C CB D E
Next state for x = 1 B EE B A
Partition P4 = P3 (A) (BC) (D) (E)
States B and C are equivalent
Figure 9.3
Example 9.2 -- Partitioning example
x
0 1
A E/0 D/0 x
0 1
B A/1 F/0
A' B'/0 A'/0
C C/0 A/1
B' A'/1 C'/0
D B/0 A/0
C' C'/0 A'/1
E D/1 C/0
D' E'/1 D'/1
F C/0 D/1
E' C'/1 B'/1
G H/1 G/1
H C/1 B/1 (b)
(a)
Figure 9.4
Example 9.3 -- Another partitioning example
x
0 1 x
A A/0 B/0 0 1
B H/1 C/0 A' A'/0 E'/0
C E/0 B/0 B' B'/1 D'/1
D C/1 D/0 C' F'/0 E'/0
E C/1 E/0 D' E'/0 B'/0
F F/1 G/1 E' E'/1 C'/0
G B/0 F/0 F' C'/1 F'/0
H H/1 C/0 (b)
(a)
Figure 9.5
Example 9.4 -- Yet another partitioning example
x1x2
00 01 11 10
A D/0 D/0 F/0 A/0 x1x2
00 01 11 10
B C/1 D/0 E/1 F/0
A' C'/0 C'/0 A'/0 A'/0
C C/1 D/0 E/1 A/0
B' B'/1 C'/0 D'/1 A'/0
D D/0 B/0 A/0 F/0
C' C'/0 B'/0 A'/0 A'/0
E C/1 F/0 E/1 A/0
D' B'/1 A'/0 D'/1 A'/0
F D/0 D/0 A/0 F/0
E' E'/0 E'/0 A'/0 A'/0
G G/0 G/0 A/0 A/0
(b)
H B/1 D/0 E/1 A/0
(a)
Figure 9.6
Finding Equivalent States by Implication Tables
x
0 1 B
B
A C /1 B /0
B C /1 E /0 C C
C B /1 E /0
D D
D D /0 B /1
E E /0 A /1
E E
(a)
A B C D A B C D
(c)
(b )
B BE BE
B
C BC
BE BC A -
C B (B C )
BE
D C -
D -
D
P K = (A )(B C )(D )(E )
E AB AB
E (f)
A B C D
(d ) A B C D
(e)
Figure 9.7
Example 9.5 -- Using implication tables to find
equivalent states
x
0 1
A E /0 D /0
B A /1 F /0
B
C C /0 A /1
D B /0 A /0 C
E D /1 C /0
F C /0 D /1 D BE
G H /1 G /1
AD
E CF
H C /1 B /1
(a)
F AD
A (A D )
B (B E ) G
C (C F )
D - CH
H
E - BG
F -
G - A B C D E F G
(b )
P K = (A D )(B E )(C F )(G )(H )
(c)
Figure 9.8
Example 9.6 -- An implication table example
x1x2
00 01 11 10
A D /0 D /0 F /0 A /0
B C /1 D /0 E /1 F /0
B
C C /1 D /0 E /1 A /0
D D /0 B /0 A /0 F /0 C AF
E C /1 F /0 E /1 A /0
BD
F D /0 D /0 A /0 F /0 D
AF
G G /0 G /0 A /0 A /0
DF DF
E
H B /1 D /0 E /1 A /0 AF
(a) BD
F
A (A F ) DG BG DG
B (B C )(B H ) G
AF AF AF
C (C H )
D - BC BC
H BC
E - AF DF
F -
G - A B C D E F G
(b )
N o te: (B C )(B H )(C H ) = (B C H )
P K = (A F )(B C H )(D )(E )(G )
(c)
Incompletely Specified Circuits
• Next states and/or outputs are not specified for all states
• Applicable input sequences: an input sequence is applicable to state, Si, of an
incompletely specified circuit if and only if when the circuit is in state Si and the
input sequence is applied, all next states are specified except for possible the last
input of the sequence.
• Compatible states: two states Si and Sj are compatible if and only if for each input
sequence applicable to both states the same output sequence will be produced
when the outputs are specified.
• Compatible states: two states Si and Sj are compatible if and only if the following
conditions are satisfied for any possible input Ip
– The outputs produced by Si and Sj are the same, when both are specified
– The next states Sk and Sl are compatible, when both are specified.
• Incompatible states: two states are said to be incompatible if they are not
compatible.
Compatibility Relations
G (G H )
F (G H )(F G )
AC E (E G )(E H )(G H )(F G )
x B E (F G )(E G H )
D (D G )(F G )(E G H )
0 1 C (C G )(C F )(C E )(C D )(D G )(F G )(E G H )
C BG C (C E G )(C D G )(C F G )(E G H )
A A /- C /1 AE B (B C )(B G )(C E G )(C D G )(C F G )(E G H )
B B /- A /- AC BC CG A (A E )(A G )(A H )(B C )(B G )(C E G )(C D G )(C F G )(E G H )
D A (A E G )(A G H )(A E H )(B C G )(C E G )(C D G )(C F G )(E G H )
C G /- E /0 AC CE A (A E G H )(B C G )(C D G )(C E G )(C F G )
D C /1 C /- AB AC
E AG (c)
E A /1 C /- AC
AD BD CD AD G -
F D /- A /- DG F (F H )
F
AC AE AC AC E (F H )(E F )
G G /- G /- D (F H )(E F )(D H )(D F )(D E )
CG AG EG CG AG DG
H H /- D /- G CG AG D (F H )(D H )(D E F )
C (C H )(F H )(D H )(D E F )
(a) AD GH CH AH DH B (B H )(B F )(B E )(B D )(C H )(F H )(D H )(D E F )
H CD DG B (B H )(B D E F )(C H )(F H )(D H )
DE CD CD AD B (B D E F )(C H )(B D F H )
A B C D E F G A (A B )(A C )(A D )(A F )(B D E F )(C H )(B D F H )
(b ) A (A B D F )(A C )(B D E F )(C H )(B D F H )
(d )
Merger diagrams
B
B C
A C
A D
(a) (b )
B C
B D
A C
A E
E D
F
(c) (d )
Figure 9.11
Example 9.10 -- Merger diagrams for example 9.8
B C B C
A D A D
H E H E
G F G F
(a) (b)
Figure 9.12
Minimization Procedure
Figure 9.13
Example 9.12 -- State reduction problem
x
0 1 B AC B
A A /- -/-
C AD
B C /1 B /0
A C
C D /0 -/1
D
D -/- B /-
E A /0 C /1 BC
E AD
E D
(a)
A B C D
(b ) (c)
B
x
0 1 x
A C 0 1
(A B D ) AC B
A' B '/1 A '/0
(A C D ) AD B
B' A '/0 B '/1
(A C E ) AD C
(f)
E D (e)
(d )
Figure 9.14
Example 9.13 -- Another state table reduction
problem
x B BD C
0 1 x
0 1
A B /1 D /0 C BD B D
(A B D ) B ABD
B -/- B /0
D AB (B C ) E BD
C E /0 D /-
(E ) - C
D B /1 A /0 CD A E
E (F ) - E
E -/- C /1
DE CE F (d )
F -/0 E /1 F
(c)
(a)
A B C D E
(b )
C
x
0 1
B D A ' A ', B '/1 A '/0
B' C '/0 A '/0
C' -/- B '/1
Figure 9.15
A E
D' -/0 C '/1
(f)
F
(e)
Example 9.14 -- Yet another state reduction problem
x B B
B DE
0 1
A D /- A /- AB
C AB DE
B E /0 A /- A C A C
C D /0 B /- AC AC
D BC
CD CE
D C /- C /-
AB
E C /1 B /- E CD BC E D E D
(a) A B C D (c) (d )
(b )
x
0 1 x x
0 1 0 1
(A B C ) DE AB
(A B C ) D E AB A' B '/0 A '/-
(A C D ) CD ABC
(D E ) C BC B' A '/1 A '/- Figure 9.16
(A D E ) CD ABC
(f) (g )
(e)
Example 9.15 -- Optimal state assignments
Present x
state 0 1
A B/0 E/0
B C/0 G/0
C D/0 F/0
D A/1 A/0
E G/0 C/0
F A/0 A/1
G F/0 D/0
Next state/output
Figure 9.17
Unique State Assignments for Four States
Present x
Assignments
state 0 1
1 2 3
A A/0 B/0
States y1 y2 y1 y2 y1 y2
B A/0 C/0
A 00 10 00
C C/0 D/0 B 01 11 10
C 11 01 11
D C/1 A/0 D 10 00 01
(a) (b)
Figure 9.18
State Assignments for a Four State Machine
x
0 1
A C/0 D/0
B C/0 A/0
C B/0 D/0
D A/1 B/1
Figure 9.19
D flip-flop realization for assignment 1
x
y2y1 0 1
0 0 1 1 /0 1 0 /0
0 1 1 1 /0 0 0 /0
1 1 0 1 /0 1 0 /0
1 0 0 0 /1 0 1 /1
Y 2 Y 1 /z
(a)
x x x x x x
y2 y1 0 1 y2 y1 0 1 y2 y1 0 1
00 0 0 00 1 1 00 1 0
01 0 0 01 1 0 01 1 0
y1 y1 y1
11 0 0 11 0 1 11 1 0
y2 y2 y2
10 1 1 10 0 0 10 0 1
z D2 D1
(b ) (c) (d )
Figure 9.20
D flip-flop realization for assignment 2
x
y2y1 0 1
0 0 0 1 /0 1 0 /0
0 1 1 1 /0 1 0 /0
1 1 0 1 /0 0 0 /0
1 0 0 0 /1 1 1 /1
Y 2 Y 1 /z
(a)
x x x x x x
y2 y1 0 1 y2 y1 0 1 y2 y1 0 1
00 0 0 00 0 1 00 1 0
01 0 0 01 1 1 01 1 0
y1 y1 y1
11 0 0 11 0 0 11 1 0
y2 y2 y2
10 1 1 10 0 1 10 0 1
z D2 D1
(b ) (c) (d )
Figure 9.21
D flip-flop realization for assignment 3
x
y2y1 0 1
0 0 0 1 /0 1 1 /0
0 1 1 0 /0 1 1 /0
1 1 0 0 /1 1 0 /1
1 0 0 1 /0 0 0 /0
Y 2 Y 1 /z
(a)
x x x x x x
y2 y1 0 1 y2 y1 0 1 y2 y1 0 1
00 0 0 00 0 1 00 1 1
01 0 0 01 1 1 01 0 1
y1 y1 y1
11 1 1 11 0 1 11 0 0
y2 y2 y2
10 0 0 10 0 0 10 1 0
z D2 D1
(b ) (c) (d )
Figure 9.22
State adjacencies for four-state assignments
y2 y2 y2
y1 0 1 y1 0 1 y1 0 1
0 A D 0 A D 0 A B
1 B C 1 C B 1 C D
Figure 9.23
Example 9.18 -- Implication Graphs
x
0 1
A B /0 C /0
B D /0 A /1
C A /1 D /0
D D /1 B /1
(a)
BD AB AC CD AD BC
(b )
Figure 9.24
Example 9.19 -- Closed subgraphs
x
0 1
A B /0 E /0
B C /1 D /1
CD AB BC AD DE
C B /0 A /0
D A /0 D /0
E B /1 A /1
(a) C lo sed su b g rap h
AC
BD
AE
C lo sed su b g rap h
(b )
Figure 9.24
Example 9.20 -- Optimal state assignment
x
y2y1 0 1
A 0 0 1 0 /0 0 1 /0
C 0 1 0 0 /1 1 1 /0
D 1 1 1 1 /1 1 0 /1
B 1 0 1 1 /0 0 0 /1
Y 2 Y 1 /z
(a)
x x x x x x
y2y1 0 1 y2y1 0 1 y2y1 0 1
00 1 0 00 0 1 00 0 0
01 0 1 01 0 1 01 1 0
y1 y1 y1
11 1 1 11 1 0 11 1 1
y2 y2 y2
10 1 0 10 1 0 10 0 1
D2 D1 z
(b )
Figure 9.26
Example 9.21 -- Another state assignment problem
BE CD AB
x
0 1
A E /0 B /0 AE
AD BC BD
B A /1 D /1
C E /0 A /0 AC
DE
D A /0 B /1
C lo sed
E D /0 C /0 su b g rap h
C lo sed su b g rap h CE
(a)
(b )
y3
y3 y2
y1 00 01 11 10
0 2 6 4
0 A D B C
1 3 7 5
y1 1 E
y2
(c)
Figure 9.27
A D flip-flop realization of the previous example
xy 3 x
x y2 y1 00 01 11 10
y3 y2 y1 0 1 0 4 12 8
A 0 0 0 0 0 1 /0 1 1 0 /0 00
B 1 1 0 0 0 0 /1 0 1 0 /1 1 5 13 9
01 d d
C 1 0 0 0 0 1 /0 0 0 0 /0
3 7 15 11 y1
D 0 1 0 0 0 0 /0 1 1 0 /1 11 d d d d
E 0 0 1 0 1 0 /0 1 0 0 /0 y2 2 6 14 10
Y 3 Y 2 Y 1 /z 10 1 1 1
(a)
y3
(b )
xy 3 x xy 3 x xy 3 x
y2 y1 y2 y1
y2 y1 00 01 11 10 00 01 11 10 00 01 11 10
0 4 12 8 0 4 12 8 0 4 12 8
00 1 00 1 00 1 1
1 5 13 9 1 5 13 9 1 5 13 9
01 d d 1 01 1 d d 01 d d
3 7 15 11 y1 3 7 15 11 y1 3 7 15 11 y1
11 d d d d 11 d d d d 11 d d d d
y2 y2 y2
2 6 14 10 2 6 14 10 2 6 14 10
10 1 10 1 1 10
y3 y3 y3
(c) (d ) (e)
Figure 9.28
Example 9.24 -- Closed partitions
x
0 1
A D /0 C /0 DF
B E /0 A /1
C F /1 B /0
AB EF BC
D A /1 F /1
DE
E C /0 E /0 AC
F B /0 D /1
(a) (b )
Figure 9.29
Example 9.25 -- Cross dependency
0 ,1
P resen t In p u t
b lo ck B 21 B 32
0 1
P 2: B 21 B 32 B 32 0 ,1 0 ,1
B 22 B 31 B 31
P 3: B 31 B 21 B 21 B 22 B 31
B 32 B 22 B 22
0 ,1
(a) (b )
Figure 9.30