TIC226 SERIES SILICON TRIACS

Copyright 1997, Power Innovations Limited, UK APRIL 1971 - REVISED MARCH 1997

q q q q

8 A RMS, 70 A Peak Glass Passivated Wafer 400 V to 800 V Off-State Voltage Max IGT of 50 mA (Quadrants 1 - 3)
MT1 MT2 G
1 2 3 TO-220 PACKAGE (TOP VIEW)

Pin 2 is in electrical contact with the mounting base.

MDC2ACA

absolute maximum ratings over operating case temperature (unless otherwise noted)
RATING TIC226D Repetitive peak off-state voltage (see Note 1) TIC226M TIC226S TIC226N Full-cycle RMS on-state current at (or below) 85C case temperature (see Note 2) Peak on-state surge current full-sine-wave (see Note 3) Peak on-state surge current half-sine-wave (see Note 4) Peak gate current Peak gate power dissipation at (or below) 85C case temperature (pulse width 200 s) Average gate power dissipation at (or below) 85C case temperature (see Note 5) Operating case temperature range Storage temperature range Lead temperature 1.6 mm from case for 10 seconds IT(RMS) ITSM ITSM IGM PGM PG(AV) TC Tstg TL VDRM SYMBOL VALUE 400 600 700 800 8 70 80 1 2.2 0.9 -40 to +110 -40 to +125 230 A A A A W W C C C V UNIT

NOTES: 1. These values apply bidirectionally for any value of resistance between the gate and Main Terminal 1. 2. This value applies for 50-Hz full-sine-wave operation with resistive load. Above 85C derate linearly to 110C case temperature at the rate of 320 mA/C. 3. This value applies for one 50-Hz full-sine-wave when the device is operating at (or below) the rated value of on-state current. Surge may be repeated after the device has returned to original thermal equilibrium. During the surge, gate control may be lost. 4. This value applies for one 50-Hz half-sine-wave when the device is operating at (or below) the rated value of on-state current. Surge may be repeated after the device has returned to original thermal equilibrium. During the surge, gate control may be lost. 5. This value applies for a maximum averaging time of 20 ms.

electrical characteristics at 25C case temperature (unless otherwise noted)

PARAMETER IDRM Repetitive peak off-state current Peak gate trigger current VD = rated VDRM Vsupply = +12 V IGTM Vsupply = +12 V Vsupply = -12 V Vsupply = -12 V Vsupply = +12 V VGTM Peak gate trigger voltage Vsupply = +12 V Vsupply = -12 V Vsupply = -12 V All voltages are with respect to Main Terminal 1. TEST CONDITIONS IG = 0 RL = 10 RL = 10 RL = 10 RL = 10 RL = 10 RL = 10 RL = 10 RL = 10 TC = 110C tp(g) > 20 s tp(g) > 20 s tp(g) > 20 s tp(g) > 20 s tp(g) > 20 s tp(g) > 20 s tp(g) > 20 s tp(g) > 20 s 2 -12 -9 20 0.7 -0.8 -0.8 0.9 2 -2 -2 2 V MIN TYP MAX 2 50 -50 -50 mA UNIT mA

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Information is current as of publication date. Products conform to specifications in accordance with the terms of Power Innovations standard warranty. Production processing does not necessarily include testing of all parameters.

TIC226 SERIES SILICON TRIACS

APRIL 1971 - REVISED MARCH 1997

electrical characteristics at 25C case temperature (unless otherwise noted) (continued)

PARAMETER VTM IH IL dv/dt dv/dt(c) Peak on-state voltage Holding current Latching current Critical rate of rise of off-state voltage Critical rise of commutation voltage ITM = 12 A Vsupply = +12 V Vsupply = -12 V Vsupply = +12 V Vsupply = -12 V VDRM = Rated VDRM VDRM = Rated VDRM TEST CONDITIONS IG = 50 mA IG = 0 IG = 0 (see Note 7) IG = 0 ITRM = 12 A TC = 110C TC = 85C 5 100 (see Note 6) Init ITM = 100 mA Init ITM = -100 mA MIN TYP 1.6 5 -9 MAX 2.1 30 -30 50 -50 UNIT V mA mA V/s V/s

All voltages are with respect to Main Terminal 1. NOTES: 6. This parameter must be measured using pulse techniques, tp = 1 ms, duty cycle 2 %. Voltage-sensing contacts separate from the current carrying contacts are located within 3.2 mm from the device body. 7. The triacs are triggered by a 15-V (open-circuit amplitude) pulse supplied by a generator with the following characteristics: RG = 100 , tp(g) = 20 s, tr = 15 ns, f = 1 kHz.

thermal characteristics
PARAMETER RJC RJA Junction to case thermal resistance Junction to free air thermal resistance MIN TYP MAX 1.8 62.5 UNIT C/W C/W

TYPICAL CHARACTERISTICS

GATE TRIGGER CURRENT vs CASE TEMPERATURE

1000 Vsupply IGTM IGT - Gate Trigger Current - mA + + + +
TC01AA

GATE TRIGGER VOLTAGE vs CASE TEMPERATURE

10 Vsupply IGTM VGT - Gate Trigger Voltage - V + + + +
TC01AB

VAA = 12 V RL = 10 tp(g) = 20 s

VAA = 12 V RL = 10 tp(g) = 20 s

100

10

01 -60

-40

-20

20

40

60

80

100

120

01 -60

-40

-20

20

40

60

80

100

120

TC - Case Temperature - C

TC - Case Temperature - C

Figure 1.

Figure 2.

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INFORMATION

TIC226 SERIES SILICON TRIACS

APRIL 1971 - REVISED MARCH 1997

TYPICAL CHARACTERISTICS

HOLDING CURRENT vs CASE TEMPERATURE

1000 Vsupply + IH - Holding Current - mA 100 VAA = 12 V VGF - Gate Forward Voltage - V IG = 0 Initiating ITM = 100 mA
TC01AD

GATE FORWARD VOLTAGE vs GATE FORWARD CURRENT

10
TC01AC

10

01

01 -60

-40

-20

20

40

60

80

100

120

QUADRANT 1 001 00001 0001

IA = 0 TC = 25 C 001 01 1

TC - Case Temperature - C

IGF - Gate Forward Current - A

Figure 3.

Figure 4.

LATCHING CURRENT vs CASE TEMPERATURE

1000 Vsupply IGTM + + 100 + +
TC01AE

SURGE ON-STATE CURRENT vs CYCLES OF CURRENT DURATION

100 ITSM - Peak Full-Sine-Wave Current - A
TI01AA

VAA = 12 V

TC 85 C

IL - Latching Current - mA

10

No Prior Device Conduction Gate Control Guaranteed

10

1 -60

-40

-20

20

40

60

80

100

120

1 1 10 100 1000 Consecutive 50-Hz Half-Sine-Wave Cycles

TC - Case Temperature - C

Figure 5.

Figure 6.

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INFORMATION

TIC226 SERIES SILICON TRIACS

APRIL 1971 - REVISED MARCH 1997

TYPICAL CHARACTERISTICS

MAX RMS ON-STATE CURRENT vs CASE TEMPERATURE

10 IT(RMS) - Maximum On-State Current - A 9 8 7 6 5 4 3 2 1 0 0 25 50 75 100 125 150 TC - Case Temperature - C
TI01AB

MAX AVERAGE POWER DISSIPATED vs RMS ON-STATE CURRENT

P(av) - Maximum Average Power Dissipated - W 32 28 24 20 16 12 8 4 0 0 2 4 6 8 10 12 14 16 IT(RMS) - RMS On-State Current - A TJ = 110 C Conduction Angle = 360 Above 8 A rms See ITSM Figure
TI01AC

Figure 7.

Figure 8.

PARAMETER MEASUREMENT INFORMATION

VAC VAC

L1

ITRM IMT2 C1 50 Hz IMT2 VMT2 DUT RG R1 IG See Note A VMT2 10% dv/dt 63% VDRM

IG NOTE A: The gate-current pulse is furnished by a trigger circuit which presents essentially an open circuit between pulses. The pulse is timed so that the off-state-voltage duration is approximately 800 s.

Figure 9.

PMC2AA

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INFORMATION

TIC226 SERIES SILICON TRIACS

APRIL 1971 - REVISED MARCH 1997

MECHANICAL DATA TO-220 3-pin plastic flange-mount package

This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly.
TO220 4,70 4,20

3,96 3,71

10,4 10,0

2,95 2,54 6,6 6,0 15,90 14,55

1,32 1,23

see Note B

see Note C

6,1 3,5

0,97 0,61 1 2 3

1,70 1,07

14,1 12,7

2,74 2,34 5,28 4,88 2,90 2,40

0,64 0,41

VERSION 1

VERSION 2

ALL LINEAR DIMENSIONS IN MILLIMETERS NOTES: A. The centre pin is in electrical contact with the mounting tab. B. Mounting tab corner profile according to package version. C. Typical fixing hole centre stand off height according to package version. Version 1, 18.0 mm. Version 2, 17.6 mm. MDXXBE

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INFORMATION

TIC226 SERIES SILICON TRIACS

APRIL 1971 - REVISED MARCH 1997

IMPORTANT NOTICE
Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the information being relied on is current. PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except as mandated by government requirements. PI accepts no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor is any license, either express or implied, granted under any patent right, copyright, design right, or other intellectual property right of PI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS.

Copyright 1997, Power Innovations Limited

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