CD4015BM CD4015BC Dual 4-Bit Static Shift Register

June 1996

CD4015BM CD4015BC Dual 4-Bit Static Shift Register

General Description
The CD4015BM CD4015BC contains two identical 4-stage serial-input parallel-output registers with independent Data Clock and Reset inputs The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition A logic high on the Reset input resets all four stages covered by that input All inputs are protected from static discharge by a series resistor and diode clamps to VDD and VSS

Features
Y Y Y

Y Y

Wide supply voltage range High noise immunity Low power TTL compatibility Medium speed operation Fully static design

3 0V to 18V 0 45 VDD (typ ) Fan out of 2 driving 74L or 1 driving 74LS 8 MHz (typ ) clock rate VDD b VSS e 10V

Applications
Y Y Y

Serial-input parallel-output data queueing Serial to parallel data conversion General purpose register

Connection Diagram and Truth Table

Dual-In-Line Package

TL F 5948 1

CL U L L K X

D 0 1 X X

R 0 0 0 1

Q1 0 1 Q1 0

Qn Qnb1 Qnb1 Qn 0

(No change)

U Level change

X e Dont care case

Order Number CD4015B

C1996 National Semiconductor Corporation

TL F 5948

RRD-B30M76 Printed in U S A

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Absolute Maximum Ratings (Notes 1

2)

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds)
b 0 5 to a 18 VDC b 0 5 to VDD a 0 5 VDC b 65 C to a 150 C

Recommended Operating Conditions

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4015BM CD4015BC
a 3 to a 15 VDC

0 to VDD VDC
b 55 C to a 125 C b 40 C to a 85 C

700 mW 500 mW 260 C

DC Electrical Characteristics CD4015BM (Note 2)

Symbol IDD Parameter Quiescent Device Current Low Level Output Voltage High Level Output Voltage Low Level Input Voltage High Level Input Voltage Low Level Output Current (Note 3) High Level Output Current (Note 3) Input Current Conditions VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V
b 55 C a 25 C a 125 C

Units mA mA mA V V V V V V

Min

Max 5 10 20 0 05 0 05 0 05

Min

Typ 0 005 0 010 0 015 0 0 0

Max 5 10 20 0 05 0 05 0 05

Min

Max 150 300 600 0 05 0 05 0 05

VOL

VOH

VIL

VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V 35 70 11 0 0 64 16 42
b 0 64 b1 6 b4 2

( (l l

lIOl k 1 mA
IO k 1 mA 4 95 9 95 14 95

4 95 9 95 14 95 15 30 40 35 70 11 0 0 51 13 34
b 0 51 b1 3 b3 4 b0 1

5 10 15 2 25 4 50 6 75 2 75 5 50 8 25 0 88 2 25 88
b 0 88 b 2 25 b8 8 b 10 b 5 b0 1

4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24
b 0 36 b0 9 b2 4 b1 0

15 30 40

V V V V V V mA mA mA mA mA mA

VIH

IOL

IOH

IIN

01

10b5

01

10

mA mA

Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The tables of Recommended Operating Conditions and Electrical Characteristics provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time

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DC Electrical Characteristics CD4015BC (Note 2)

Symbol IDD Parameter Quiescent Device Current Low Level Output Voltage High Level Output Voltage Low Level Input Voltage High Level Input Voltage Low Level Output Current (Note 3) High Level Output Current (Note 3) Input Current Conditions VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V 35 70 11 0 0 52 13 36
b 0 52 b1 3 b3 6 b0 3 b 55 C a 25 C a 125 C

Units mA mA mA V V V V V V

Min

Max 20 40 80 0 05 0 05 0 05

Min

Typ 0 005 0 010 0 015 0 0 0

Max 20 40 80 0 05 0 05 0 05

Min

Max 150 300 600 0 05 0 05 0 05

VOL

VOH

4 95 9 95 14 95 15 30 40

4 95 9 95 14 95

5 10 15 2 25 4 50 6 75 15 30 40

4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24
b 0 36 b0 9 b2 4 b0 3 b1 0

VIL

V V V V V V mA mA mA mA mA mA

VIH

35 70 11 0 0 44 11 30
b 0 44 b1 1 b3 0

2 75 5 50 8 25 0 88 2 25 88
b 0 88 b 2 25 b8 8 b 10 b 5

IOL

IOH

IIN

03

10b5

03

10

mA mA

Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The tables of Recommended Operating Conditions and Electrical Characteristics provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time

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AC Electrical Characteristics
TA e 25 C CL e 50 pF RL e 200k tr e tf e 20 ns unless otherwise specified Symbol CLOCK OPERATION tPHL tPLH Propagation Delay Time VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Clock Input Other Inputs 2 45 6 50 20 15 35 8 11 75 5 10 75 230 80 60 100 50 40 160 60 50 350 160 120 200 100 80 250 110 85 15 15 15 100 40 30 ns ns ns ns ns ns ns ns ns ms ms ms ms ms ms MHz MHz MHz pF pF Parameter Conditions Min Typ Max Units

tTHL tTLH

Transition Time

tWL tWM

Minimum Clock Pulse-Width Clock Rise and Fall Time Minimum Data Set-Up Time Maximum Clock Frequency Input Capacitance

trCL tfCL

tSU

fCL

CIN

RESET OPERATION tPHL(R) Propagation Delay Time VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V 200 100 80 135 40 30 400 200 160 250 80 60 ns ns ns ns ns ns

tWH(R)

Minimum Reset Pulse Width

AC Parameters are guaranteed by DC correlated testing

Logic Diagrams

TL F 5948 2

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Logic Diagrams (Continued)

Terminal No 16 e VDD Terminal No 8 e GND

TL F 5948 3

Physical Dimensions inches (millimeters) unless otherwise noted

Ceramic Dual-In-Line Package (J) Order Number CD4015BMJ or CD4015BCJ NS Package Number J16A

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CD4015BM CD4015BC Dual 4-Bit Static Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N) Order Number CD4015BMN or CD4015BCN NS Package Number N16E

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