PILLAI INSTITUTE OF INFORMATION TECHNOLOGY, ENGINEERING, MEDIA STUDIES & RESEARCH NEW PANVEL 410 206 CLASS TEST

T II Branch: - Electronics Date: 12/04/2013 Time: 1:30P.M to 03:00 P.M Total Marks: 50 Sem: VIII Sub: AVLSID

N.B. : (1) Question No. 1 is compulsory. (2)Attempt any four from the remaining Q1. Q2.
a) Explain the factors on which dynamic power dissipation depends?

b)

Explain the role of sense amplifier.

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What is the cell ratio and Pull-up ratio of 6T SRAM cell? How does this affect the read/write operation?

Q3. What are different clocking strategies employed in VLSI systems? Discuss H tree clock distribution in high density CMOS circuits. Q4. Draw the Analog Design Octagon and explain its significance. Q5. Explain the need of interconnect delay model .Also define cross-talk in case of VLSI design. Q6. Draw 1T DRAM cell and explain its write, read ,hold and refresh operation. Q7. Draw the Schematic of CLA. Explain how the speed can be improved?

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