Arithmetic Building Blocks: Digital Integrated Circuits © Prentice Hall 1995 Arithmetic

Digital Integrated Circuits Prentice Hall 1995 Arithmetic
Arithmetic Building
Blocks
A Generic Digital Processor
MEMORY
DATAPATH
CONTROL
I
N
P
U
T
-
O
U
T
P
U
T
Building Blocks for Digital Architectures
Arithmetic unit
- Bit-sliced datapath ( adder , multiplier,
shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
Bit-Sliced Design
Bit 3
Bit 2
Bit 1
Bit 0
R
e
g
i
s
t
e
r
A
d
d
e
r
S
h
i
f
t
e
r
M
u
l
t
i
p
l
e
x
e
r
Control
D
a
t
a
-
I
n
D
a
t
a
-
O
u
t
Tile identical processing elements
Full-Adder
A B
Cout
Sum
Cin
Full
adder
The Binary Adder
S A B C
i
=
A = BC
i
ABC
i
ABC
i
ABC
i
+ + +
C
o
AB BC
i
AC
i
+ + =
A B
Cout
Sum
Cin
Full
adder
Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A
B
Delete = A B
Can also derive expressions for S and C
o
based on D
and P
The Ripple-Carry Adder
A
0
B
0
S
0
C
o,0
C
i,0
A
1
B
1
S
1
C
o,1
A
2
B
2
S
2
C
o,2
A
3
B
3
S
3
C
o,3
(= C
i,1
)
FA
FA
FA
FA
Worst case delay linear with the number of bits
t
adder
N 1 ( )t
carry
t
sum
+ ~
t
d
= O(N)
Goal: Make the fastest possible carry path circuit
Complimentary Static CMOS Full Adder
V
DD
V
DD
V
DD
V
DD
A B
C
i
S
C
o
X
B
A
C
i A
B B A
C
i
A B C
i
C
i
B
A
C
i
A
B
B A
28 Transistors
Inversion Property
A B
S
C
o
C
i FA
A B
S
C
o
C
i
FA
S A B C
i
, , ( ) S A B C
i
, , ( ) =
C
o
A B C
i
, , ( ) C
o
A B C
i
, , ( ) =
Minimize Critical Path by Reducing Inverting Stages
A
0
B
0
S
0
C
o,0
C
i,0
A
1
B
1
S
1
C
o,1
A
2
B
2
S
2
C
o,2
C
o,3
FA FA FA FA
A
3
B
3
S
3
Odd Cell Even Cell
Exploit Inversion Property
Note: need 2 different types of cells
The better structure: the Mirror Adder
V
DD
C
i
A
B B A
B
A
A B
Kill
Generate
"1"-Propagate
"0"-Propagate
V
DD
C
i
A B C
i
C
i
B
A
C
i
A
B
B
A
V
DD
S
C
o
24 transistors
The Mirror Adder
The NMOS and PMOS chains are completely symmetrical. This guarantees
identical rising and falling transitions if the NMOS and PMOS devices are
properly sized. A maximum of two series transistors can be observed in the carry-
generation circuitry.
When laying out the cell, the most critical issue is the minimization of the
capacitance at node C
o
. The reduction of the diffusion capacitances is particularly
important.
The capacitance at node C
o
is composed of four diffusion capacitances, two
internal gate capacitances, and six gate capacitances in the connecting adder cell .
The transistors connected to C
i
are placed closest to the output.
Only the transistors in the carry stage have to be optimized for optimal speed. All
transistors in the sum stage can be minimal size.
Quasi-Clocked Adder
V
DD
A
B
B
A
P
V
DD
P
P
C
i
S
P P
V
DD
P
P
A
P
P
C
i
B B
V
DD
C
o
C
i
Signal Setup
Carry Generation
Sum Generation
NMOS-Only Pass Transistor Logic
A
A
B B
C
C
Sum Sum
A
C C
B
C
out
C
out
B
A
A
A A
Transistor count (CPL) : 28
NP-CMOS Adder
V
DD
|
|
C
i0
A
0
B
0
B
0
|
A
0
V
DD
|
B
1
|
A
1
V
DD
|
|
A
1
B
1
C
i1
C
i 2
C
i0
C
i0
B
0
A
0
B
0
S
0
A
0
V
DD
|
|
V
DD
|
V
DD
|
|
B
1
C
i1
B
1
|
A
1
A
1
V
DD
|
S
1
C
i 1
Carry Path
NP-CMOS Adder
A
0
B
0
A
1
B
1
S
0
S
1
C
o1
C
i0
Manchester Carry Chain
P
0
C
i,0
P
1
G
0
P
2
G
1
P
3
G
2
P
4
G
3
G
4
|
|
V
DD
Sizing Manchester Carry Chain
R
1
C
1
R
2
C
2
R
3
C
3
R
4
C
4
R
5
C
5
R
6
C
6
Out
M
0
M
1
M
2
M
3
M
4
M
C
Discharge Transistor
1 2 3 4 5 6
t
p
0.69 C
i
R
j
j 1 =
i
\ .
|
| |
i 1 =
N
=
1 1.5 2.0 2.5 3.0
k
5
10
15
20
25
S
p
e
e
d
1 1.5 2.0 2.5 3.0
k
0
100
200
300
400
A
r
e
a
Speed (normalized by 0.69RC) Area (in minimum size devices)
Carry-Bypass Adder
FA FA FA FA
P
0
G
1
P
0
G
1
P
2
G
2
P
3
G
3
C
o,3
C
o,2
C
o,1
C
o,0
C
i ,0
FA FA FA FA
P
0
G
1
P
0
G
1
P
2
G
2
P
3
G
3
C
o,2
C
o,1
C
o,0
C
i,0
C
o,3
M
u
l
t
i
p
l
e
x
e
r
BP=P
o
P
1
P
2
P
3
Idea: If (P0 and P1 and P2 and P3 = 1)
then C
o3
= C
0
, else kill or generate.
Manchester-Carry Implementation
P
0
C
i,0
P
1
G
0
P
2
G
1
P
3
G
2
BP
G
3
BP
C
o,3
Carry-Bypass Adder (cont.)
Setup
Carry
Propagation
Sum
Setup
Carry
Propagation
Sum
Setup
Carry
Propagation
Sum
Setup
Carry
Propagation
Sum
Bit 0-3 Bit 4-7 Bit 8-11
Bit 12-15
C
i,0
Carry Ripple versus Carry Bypass
N
t
p
ripple adder
bypass adder
4..8
Carry-Select Adder
Setup
"0" Carry Propagation
"1" Carry Propagation
Multiplexer
Sum Generation
C
o, k-1 C
o,k+3
"0"
"1"
P,G
Carry Vector
Carry Select Adder: Critical Path
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
S
0-3
S
4-7
S
8-11
S
12-15
C
o,15
C
o,11
C
o,7
C
o,3
C
i,0
Linear Carry Select
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
S
0-3
S
4-7
S
8-11
S
12-15
C
i,0
(1)
(1)
(5)
(6) (7) (8)
(9)
(10)
(5) (5) (5) (5)
Square Root Carry Select
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13
S
0-1
S
2-4
S
5-8
S
9-13
C
i, 0
(4) (5) (6) (7)
(1)
(1)
(3) (4) (5) (6)
Mux
Sum
S
14-19
(7)
(8)
Bit 14-19
(9)
(3)
Adder Delays - Comparison
0.0 20.0 40.0 60.0
N
0.0
10.0
20.0
30.0
40.0
50.0
t
p
ripple adder
linear select
square root select
LookAhead - Basic Idea
A
0
,B
0
A
1
,B
1
A
N-1
,B
N-1
...
C
i,0
P
0
C
i ,1
P
1
C
i,N-1 P
N-1
...
Look-Ahead: Topology
V
DD
P
3
P
2
P
1
P
0
G
3
G
2
G
1
G
0
C
i,0
C
o,3
Logarithmic Look-Ahead Adder
A
7
F
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
F
t
p
~ log
2
(N)
t
p
~ N
Brent-Kung Adder
(G
0
,P
0
)
(G
1
,P
1
)
(G
2
,P
2
)
(G
3
,P
3
)
(G
4
,P
4
)
(G
5
,P
5
)
(G
6
,P
6
)
(G
7
,P
7
)
C
o,0
C
o,1
C
o,2
C
o,3
C
o,4
C
o,5
C
o,6
C
o,7
t
add
~ log
2
(N)
The Binary Multiplication
Z X
Y Z
k
2
k
k 0 =
M N 1 +
= =
X
i
2
i
i 0 =
M 1
\ .
|
|
|
| |
Y
j
2
j
j 0 =
N 1
\ .
|
|
|
| |
=
X
i
Y
j
2
i j +
j 0 =
N 1
\ .
|
|
|
| |
i 0 =
M 1
=
X X
i
2
i
i 0 =
M 1
=
Y Y
j
2
j
j 0 =
N 1
=
with
The Binary Multiplication
1 0 1 1
1 0 1 0 1 0
0 0 0 0 0 0
1 0 1 0 1 0
1 0 1 0 1 0
1 0 1 0 1 0
1 1 1 0 0 1 1 1 0
+
Partial Products
AND operation
The Array Multiplier
HA FA FA HA
FA FA FA HA
FA FA FA HA
X
0
X
1
X
2
X
3
Y
1
X
0
X
1
X
2
X
3
Y
2
X
0
X
1
X
2
X
3
Y
3
Z
1
Z
2
Z
3
Z
4
Z
5
Z
6
Z
0
Z
7
The MxN Array Multiplier
Critical Path
HA FA FA HA
HA FA FA FA
FA FA FA HA
Critical Path 1
Critical Path 2
Critical Path 1 & 2
Carry-Save Multiplier
HA HA HA HA
FA FA FA HA
FA HA FA FA
FA HA FA HA
Vector Merging Adder
Adder Cells in Array Multiplier
A
B
P
C
i
V
DD
A
A A
V
DD
C
i
A
P
A
B
V
DD
V
DD
C
i
C
i
C
o
S
C
i
P
P
P
P
P
Identical Delays for Carry and Sum
Multiplier Floorplan
S C S C S C S C
S C S C S C S C
S C S C S C S C
S
C
S
C
S
C
S
C
Z
0
Z
1
Z
2
Z
3
Z
4
Z
5
Z
6
Z
7
X
0
X
1
X
2
X
3
Y
1
Y
2
Y
3
Y
0
Vector Merging Cell
HA Multiplier Cell
FA Multiplier Cell
X and Y signals are broadcasted
through the complete array.
( )
Wallace-Tree Multiplier
FA
FA
FA
FA
y
0
y
1
y
2
y
3
y
4
y
5
S
C
i-1
C
i-1
C
i-1
C
i
C
i
C
i
FA
y
0
y
1
y
2
FA
y
3
y
4
y
5
FA
FA
C
C S
C
i-1
C
i-1
C
i-1
C
i
C
i
C
i
Multipliers Summary
Optimization Goals Different Vs Binary Adder
Once Again: Identify Critical Path
Other possible techniques
- Data encoding (Booth)
- Pipelining
FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION
- Logarithmic versus Linear (Wallace Tree Mult)
Design as a Trade-Off
0 10 20
N
0.0
20.0
40.0
60.0
80.0
t
p

(
n
s
e
c
)
0 10 20
N
0.0
0.2
0.4
A
r
e
a

(
m
m
2
)
look-ahead
select
bypass
manchester
mirror
static
manchester
look-ahead
select
static
mirror
bypass
Layout Strategies for Bit-
Sliced Datapaths
Well
Control
Wires
(M1)
Well
Wires
(M1)
GND
V
DD
GND
GND
V
DD
GND
Approach I
Signal and power lines parallel
Approach II
Signal and power lines perpendicular
S
i
g
n
a
l
s

W
i
r
e
s

(
M
2
)
S
i
g
n
a
l
s

W
i
r
e
s

(
M
2
)
Layout of Bit-sliced Datapaths
Layout of Bit-sliced Datapaths
(a) Datapath without feedthroughs
and without pitch matching
(area = 4.2 mm
2
).
(b) Adding feedthroughs
(area = 3.2 mm
2
)
(c) Equalizing the cell height reduces
the area to 2.2 mm
2
.

Arithmetic Building Blocks: Digital Integrated Circuits © Prentice Hall 1995 Arithmetic

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Arithmetic Building Blocks: Digital Integrated Circuits © Prentice Hall 1995 Arithmetic

Uploaded by

Copyright:

Available Formats

Digital Integrated Circuits Prentice Hall 1995 Arithmetic

You might also like