SUBJECT: VLSI TECHNOLOGY & DESIGN PROJECT

TITLE: IMPLEMENTATION OF 4-BIT UPDOWN COUNTER

DATE :

DOC. CODE : DIET/EC/6TH-SEM REV. NO. : 2.00/JAN-2013

AIM: IMPLEMENTATION OF 4-BIT UPDOWN COUNTER BLOCK DIAGRAMS AND TRUTH TABLES: (1) D flipflop

INPUT Qn D 0 0 0 1 1 1 0 1

OUTPUT Qn+1 0 1 0 1

Darshan Institute of Engineering And Technology, Rajkot

Name&Roll No:Vanagara Bharat P (17) Makasana Dixit G (12)

SUBJECT: VLSI TECHNOLOGY & DESIGN PROJECT

TITLE: IMPLEMENTATION OF 4-BIT UPDOWN COUNTER

DATE :

DOC. CODE : DIET/EC/6TH-SEM REV. NO. : 2.00/JAN-2013

VHDL CODE: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity up_down_counter is port(clk, rst_a, mode : in std_logic; --mode=1 up counting, mode=0 down counting q : out std_logic_vector(3 downto 0)); end up_down_counter; architecture archi of up_down_counter is signal tmp: std_logic_vector(3 downto 0); begin process (clk, rst_a) begin if (rst_a='1') then tmp <= "0000"; elsif (clk'event and clk='1') then if (mode='1') then tmp <= tmp + 1; else tmp <= tmp - 1; end if; end if; end process; q <= tmp; end archi;

Darshan Institute of Engineering And Technology, Rajkot

Name&Roll No:Vanagara Bharat P (17) Makasana Dixit G (12)

SUBJECT: VLSI TECHNOLOGY & DESIGN PROJECT

TITLE: IMPLEMENTATION OF 4-BIT UPDOWN COUNTER

DATE :

DOC. CODE : DIET/EC/6TH-SEM REV. NO. : 2.00/JAN-2013

DEVICE PROPERTIES: FOR ALL LOGIC GATES:

PROJECT STATUS:

Darshan Institute of Engineering And Technology, Rajkot

Name&Roll No:Vanagara Bharat P (17) Makasana Dixit G (12)

SUBJECT: VLSI TECHNOLOGY & DESIGN PROJECT

TITLE: IMPLEMENTATION OF 4-BIT UPDOWN COUNTER

DATE :

DOC. CODE : DIET/EC/6TH-SEM REV. NO. : 2.00/JAN-2013

RTL SCHEMATIC:

Darshan Institute of Engineering And Technology, Rajkot

Name&Roll No:Vanagara Bharat P (17) Makasana Dixit G (12)

SUBJECT: VLSI TECHNOLOGY & DESIGN PROJECT

TITLE: IMPLEMENTATION OF 4-BIT UPDOWN COUNTER

DATE :

DOC. CODE : DIET/EC/6TH-SEM REV. NO. : 2.00/JAN-2013

SIMULATION WAVEFORM:

CONCLUSION:

IN CHARGE
Darshan Institute of Engineering And Technology, Rajkot

HOD
Name&Roll No:Vanagara Bharat P (17) Makasana Dixit G (12)