SPICE OPUS

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THE SLIDE RULE OF SILICON DESIGN

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Free Analog Circuit Simulation

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Device Models in Spice OPUS

MOS (M)
Level 1 2 3 4 5 6 7 44 47 53 54 55 56 57 58 Model type Mos1 Mos2 Mos3 BSIM1 BSIM2 Mos6 UFET EKV BSIM3v2 BSIM3 BSIM4 B3SOIv1 B3SOI Soi3 UFS Description MOS1, Meyer capacitance model MOS2, Meyer capacitance model MOS3, Meyer capacitance model BSIM1 Berkeley short channel IGFET model BSIM2 Berkeley short channel IGFET model MOS6, Meyer capacitance model UFET model EKV MOSFET model BSIM3v2 Berkeley short channel IGFET model BSIM3v3 Berkeley short channel IGFET model BSIM4 Berkeley short channel IGFET model BSIM3SOIv1 Berkeley SOI MOSFET model BSIM3SOIv2 Berkeley SOI MOSFET model STAG PD SOI MOSFET model UFSOI MOSFET model

JFET (J)
Level 1 2 Model type JFET JFET2 Description JFET Parker-Skellern short channel JFET model

MESFET (Z)
Level 1 2 Model type MES HFET1 Description MESFET model HFET model

Diode (D)
Level 1 3 Model type Diode Diode3 Description Nongeometric junction diode model Geometric junction diode model

http://fides.fe.uni-lj.si/spice/models.html

18-Sep-13

SPICE OPUS

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Other Devices
Device BJT (Q) Resistor (R) Capacitor (C) Inductor (L) Inductor coupling (K) Voltage controlled switch (S) Current controlled switch (W) Lossless transmission line (T) Lossy transmission line (O) Uniformly distributed RC line (U) VCVS (E) VCCS (G) CCVS (H) CCCS (F) Independent voltage source (V) Independent current source (I) Nonlinear controlled current/voltage source (B) Model type BJT Resistor Capacitor Inductor mutual Switch CSwitch Tranline LTRA URC VCVS VCCS CCVS CCCS Vsource Isource ASRC

XSPICE code models (A)

Poly source - builtin code model, used for simulation of simulator-translated polynomial sources (POLY(N)). Code models loaded from .cm library files are described in the XSPICE section of the documentation. Information about model parameters of code models are also in the .ifs files supplied with the .cm library sources. For .cm library source file location in the SPICE OPUS tree see installation instructions.

Copyright 2008 Faculty of Electrical Engineering, Ljubljana, Slovenia | All Rights Reserved Page Design G. Wolfgang | Page content EDA Group

http://fides.fe.uni-lj.si/spice/models.html

18-Sep-13