BO CO N LOGIC S

I. Nhim v v yu cu:
1. Nhim v:
Thit k v kim tra t ng b cng s thc 32 bit theo chun IEEE 754, h tr
mt kiu lm trn ti gn nht chn.
2.Yu cu:
2.1 Yu cu c bn.
Thit k m phng cv kim tra trn ModelSim vi mt s lng ln t hp
u vo nht nh. Khuyn khch kim tra t ng.
Thit k phi tng hp c trn XiLinx ISE.
2.2 Yu cu nng cao.
Kim tra thit k trn mch tht FPGA, s dng IC chc nng v cc giao tip c
sn trn mch th nghim: UART, USB/UART, PS/2, LCD1602A, 7SEG-LED
dislay, Leds, Swiths, Buttons trong phi c 1 giao tip thc hin vi my tnh.
Kho st v hiu sut lm vic ca mch bng cch thay i tn s u vo, lp
bo co v mc s dng ti nguyn hiu sut(tc lm vic ca mch).

II. Chun s thc ANSI/IEEE- 754

1. nh dng chun s thc du phy ng.

nh dng s thc du phy ng.

Gi tr ca s biu din tnh bng cng thc:
Trong :
Bt trng s cao nht S biu din du, nu S = 1 th du m, S=0 th du dng.
K bit tip theo EkEk-1E1 biu din s m (exponent), Cc bit ny biu din cc gi
tr khng du t 0 n 2k - 1. Chun s thc quy nh gi tr thc biu din thc cht
bng e = exponent (2k-1-1), gi tr (2k-1-1) gi l dch ca s m (exponent
bias) c ngha l min gi tr ca s m t -(2k-1-1) n +(2k-1-2) .
N bt cui cng dng biu din phn thp phn FRACTION vi gi tr tng
ng l m = 1, mnmn-1m0 , vi s thc chun th s 1 trong cng thc ny cng
khng c biu din trc tip m ngm nh lun lun c nn cn gi l bit n.
Trong chun s thc 32 bit c nh ngha bi IEEE 754 th k = 8, n = 22.
2. Cc trng hp c bit v cch gii quyt trong khi thc hin php cng 32 bt.
2.1. Nu exponent = 255 v fraction 0, th v l NaN(not a number : khng l s).
Khi thc hin cng vi s l NaN th kt qu c quy nh c phn nh tr
l :00000000000000000000001.
2.2. Nu exponent = 255 v fraction = 0, th v = ( -1)s.
y l trng hp ta vn thc hin cng bnh thng v kt qu u ra l +
hay - l ph thuc vo bt du trong kt qu.
s exponent-127
2.3. Nu 0 < exponent < 255, th v = (-1) 2
(1, mnmn-1m0).
y l trng hp m ta tin hnh cng bnh thng v thu c kt qu theo
ng yu cu v mc h thit k.
2.4. Nu exponent = 0 v fraction 0, th v = (-1)s2-126(0, mnmn-1m0) (s khng
chun).
Trong trng hp cng vi s khng chun ta phi lu 2 im c bn sau:
- Bt n trong phn nh tr khng phi l 1 m l khng. Tc l gi tr ca
phn thp phn s l 0,m ch khng phi 1,m nh s bnh thng. V l do
khi thc hin cng vi s khng chun th phn nh tr ca s khng
chun phi l 0,m.

- Chun IEEE-754 quy nh s m m b nht i vi s khng chun l

-126 nn khi tin hnh dch phi phn nh tr thc hin php cng ta ch
dch i s lng bt l |ea- eb| -1.
2.5. Nu exponent = 0 v fraction 0, th v= (-1)s 0 (zero)
Trong trng hp ny ta tin hnh cng bnh thng. Nu kt qu ra l 0 th
quy nh +0 hay -0 s ph thuc vo bt du.

III. S khi thit k v chc nng cc khi:

1 S khi:

2. Chc nng cc khi:

2.1. Khi separate
Khi separate thc hin chc nng tch cc bt ca 2 s u vo a v b thnh cc
phn s, e, m nh quy nh ca chun s thc.
2.2.
Khi subtract.
L khi cng thc hin chc nng tm gi tr sai lch gia gi tr m ea v eb.
Thc cht khi ny l ly ea eb, a ra gi tr ln hn v a ra gi tr cn dch cho
khi dch.
2.3. Khi mux.
L khi c nhim v chn ra s nh hn trong hai s 25 bit, a s b sang khi
dch, s ln a sang khi cng v gn gi tr e = 0 nu ma >= mb, ngc li e = 1
nu ma < mb. Trong khi Mux cn thc hin dng chun ca phn thp phn 25 bit :
nu phn m bng khng th phn thp phn vi gi tr tng ng l: m =
00,m22m21.m0 khi a vo khi dch th n dch sang phi s=|ea-eb|-1 bit ( khi ta
khai bo l 0, m22m21.m00 v dch sang phi s bit ), ngc li nu phn m khc
khng th phn thp phn c gi tr tng ng l: 01, m22m21.m0.
2.4.Khi shifter.
T hng t nh hn a t khi Mux ta dch sang phi mt lng bit bng |eaeb| v gn 3 gi tr G1, R1, S1 l cc thnh phn cung cp thng tin lm trn v cung
cp gi tr cin cho khi ADDER. Ngoi ra trong khi ny cn thc hin nhim v so
snh du 2 s thc nu s dch mang kt qu m th n thc hin dch i mt lng
|ea-eb| v ly o s .
2.5 Khi adder.
L khi c nhim v thc hin php cng hai hng t 25 bit, mt hng t ly t
khi SHIFTER, mt hng t ly t s ln ca khi Mux v c gi tr cin t khi
SHIFTER. ng thi khi ny cn xc nh du ca php cng 2 s thc 32 bit.
2.6. Khi normalize1.
L khi thc hin chc nng chun ha v gi tr thu c c dng 1,xx..xxx chnh
v vy cn phi xc nh xem s 1 nm v tr no t bn tri sang, trong trng hp
tr 2 s cho nhau m c phn m bng khng v v tr s 1 nm v tr 22(trong 25
bit kt qu u ra) th dng chun ha gi nguyn kt qu hiu m khng chuyn v

dng 1,xx..xxx. Ngoi ra khi normalize1 cn cung cp 2 gi tr R1(round),

S1(sticky) v thng tin iu chnh phn m.

Dng kt qu a vo khi lm trn.

2.7. Khi adjust.
T thng tin v tr s 1 nm v tr no bn tri m ta thc hin iu chnh s m
ca s thc. Nu v tr s 1 nm bn tri cng thi tng s m ln 1 cn nu s 1
nm v tr s 23 th s m s nguyn, cn nm vi tr 22 th s m s tr ,
2.8. Khi round.
Kt qu sau khi chun ha th chng ta cn phi lm trn, quy tc lm trn theo
tiu chun ca lm trn ti gn nht chn. Sau khi kt qu lm trn m bit nh bng 1
th chng ta cn phi chun ha 1 ln na v vy trong thit k c 2 khi chun ha
v sau khi chun ha ln th 2 khng c khi lm trn v phn pha sau n u c
kt qu bng 0. Yu cu c khi chun ha th 2 nn chng ta bt buc c bc iu
chnh s m ln th 2.
2.9. Khi normalize2.
Khi ny thc hin chun ha ln 2 v khi bt nh trong khi lm trn c th
bng 1 hoc bng 0, nu bng 1 th chng ta phi c khi normalize2.
3. Chng trnh thit k cho khi v s chn :
3.1 Chng trnh khi separate:
Chng trnh :
library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------------------entity separate is
port (
a, b
: in std_logic_vector(31 downto 0);
sa, sb : out std_logic;
ea, eb : out std_logic_vector(7 downto 0);
ma, mb : out std_logic_vector(22 downto 0)
);
end separate;
---------------------------------------------------------------architecture dataflow of separate is
begin
process (a, b)

begin
sa <= a(31);
sb <= b(31);
ea <= a(30 downto 23);
eb <= b(30 downto 23);
ma <= a(22 downto 0);
mb <= b(22 downto 0);
end process;
end dataflow;

S chn:

3.2 Chng trnh khi subtract:

Chng trnh :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;
use ieee.numeric_std.all;
---------------------------------------------------------------entity subtract is
port(
a, b
: in std_logic_vector(7 downto 0);
c
: out std_logic_vector(7 downto 0);
s
: out integer
);
end subtract;
---------------------------------------------------------------architecture subtract of subtract is

signal b_1
: std_logic_vector(8 downto 0);
signal s1
: std_logic_vector(8 downto 0);
signal a1, b1
: std_logic_vector(8 downto 0);
begin
b1 <= '0' & b;
b_1 <= not(b1) + 1;
a1 <= '0' & a;
s1 <= a1 + b_1;
process (a, b, s1(8))
begin
if (s1(8)='0') then
-- ea > eb
c <= a;
--dau ra c la so mu lon hon
elsif(s1(8)='1') then
-- ea < eb
c <= b;
end if;
end process;
s <= to_integer(signed(s1))

-- ea - eb

end subtract;

S chn:

3.3 Chng trnh khi mux:

Chng trnh :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;
use ieee.numeric_std.all;
---------------------------------------------------------------entity mux is

port (a
: in std_logic_vector(22 downto 0);
b
: in std_logic_vector(22 downto 0);
ea,eb : in std_logic_vector(7 downto 0);
s
: in integer;
c
: out std_logic_vector(24 downto 0);
d
: out std_logic_vector(24 downto 0);
e
: out std_logic
);
end mux;
--------------------------------------------------------------architecture mux of mux is
signal a1
: std_logic_vector(24 downto 0);
signal b1
: std_logic_vector(24 downto 0);
signal a2
: std_logic_vector(24 downto 0);
signal b2
: std_logic_vector(24 downto 0);
signal sum
: std_logic_vector(24 downto 0);
signal temp1
: std_logic_vector(24 downto 0);
component cla_adder is
port ( a, b
: in std_logic_vector(24 downto 0);
s
: out std_logic_vector(24 downto 0)
);
end component;
component sub_norm is
port
(
a,b
: in std_logic_vector(22 downto 0);
ea , eb
: in std_logic_vector(7 downto 0);
a_o, b_o
: out std_logic_vector(24 downto 0)
);
end component;
-----------------------------------------------------------------begin
U0: component sub_norm
port map (a,b,ea,eb,a1,b1);
temp1 <= not(b1) + 1;
------------------------------------------------------------------U1: component cla_adder
port map(a1, temp1, sum);
--tru 2 phan thap phan cho nhau (a1 - b1)
U2: process (a1, b1, s, sum)

begin
if (s > 0) then -- exp(a) > exp(b) va a1 > b1
a2 <= a1;
b2 <= b1;
e <= '0';
elsif (s = 0 and sum(24) = '0') then
a2 <= a1;
b2 <= b1;
e <= '0';
elsif (s = 0 and sum(24) = '1') then
a2 <= b1;
b2 <= a1;
e <= '1';
elsif (s < 0) then
a2 <= b1;
b2 <= a1;
e <= '1';
end if;
end process;

-- exp(a) = exp(b) va a1 >= b1

-- exp(a) = exp(b) va a1 < b1

-- exp(a) < exp(b) va a1 < b1

c <= a2;
d <= b2;
end mux;
-----------------------------------------------------------------------------------------------------

Chng trnh con:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;
use ieee.numeric_std.all;
---------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
---------------------------------------------------------------entity sub_norm is
port
(
a,b
: in std_logic_vector(22 downto 0);

ea , eb
a_o, b_o

: in std_logic_vector(7 downto 0);

: out std_logic_vector(24 downto 0)

);
end entity;
---------------------------------------------------------------architecture behav of sub_norm is
begin
process(a, b,ea,eb)
begin
if(ea="00000000" ) then
a_o <= '0' & a & '0';
else
a_o <= "01" & a;
end if;
if(eb="00000000" ) then
b_o <= '0' & b & '0';
else
b_o <= "01" & b;
end if;
end process;
end behav;
---------------------------------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------entity cla_adder is
port( a, b
: in std_logic_vector(24 downto 0);
s
: out std_logic_vector(24 downto 0)
);
end cla_adder;
---------------------------------architecture cla_adder of cla_adder is
begin
s <= a + b;
end cla_adder;

S chn:

3.4 Chng trnh khi shifter:

Chng trnh:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;
use ieee.numeric_std.all;
------------------------------------------------------------entity shifter is
port (b
: in std_logic_vector(24 downto 0);
sa, sb
: in std_logic;
s0
: in integer;
c
: out std_logic_vector(24 downto 0);
G, R, S,cin : out std_logic
);
end shifter;
---------------------------------------------------------------architecture shifter of shifter is
signal b4,b3
: std_logic_vector(24 downto 0);
signal b1,b2
: bit_vector(24 downto 0);
signal temp2
: std_logic_vector(24 downto 0):="0000000000000000000000000";
signal s_and,s_or : std_logic;
signal s3: integer;
begin
s3<= abs (s0);
U0:process(sa, sb, b,b1,b2,b4,s3)
begin
b1<= to_bitvector(b);
b2 <= b1 srl s3;
b4 <= to_stdlogicvector(b2);
if(sa = sb) then

b3 <= b4;
elsif(sa /= sb) then
b3 <= not(b4);
end if;
end process;
U1:process(s3, b3,sa,sb,b)
begin
if(s3 = 0) then
if sa=sb then
c <=b3;
G <= '0';
R <= '0';
S <= '0';
cin <= '0';
elsif sa /= sb then
c <= b3;
G <= '0';
R <= '0';
S <= '0';
cin <= '1';
end if;
elsif(s3 = 1) then
if sa=sb then
c <=b3;
G <= b(0);
R <= '0';
S <= '0';
cin <= '0';
elsif sa /= sb then
if b(0)='0' then
c <=b3;
G <='0';
R <= '0';
S<= '0';
cin <= '1';
elsif b(0)='1' then
c <=b3;
G <='1';
R <= '0';
S <= '0';

cin <= '0';

end if;
end if;
elsif(s3 = 2) then
s_or <= b(1) or b(0);
s_and <= b(1) and b(0);
if sa=sb then
if s_or ='0' then
c <=b3;
G <= b(1);
R <= b(0);
S <= '0';
cin <= '0';
else
if (b(1)='0' and b(0)='1') then
c <=b3;
G <='1';
R <='0';
S <='0';
cin <= '0';
elsif (b(1)='1' and b(0)='0' ) then
c <=b3;
G <='1';
R <='1';
S <='0';
cin <= '0';
else
c <=b3;
G <= '0';
R <= '0';
S <= '0';
cin <= '1';
end if;
end if;
elsif sa /=sb then
if s_or ='0' then
c <=b3;
G <= '0';
R <= '0';
S <= '0';

cin <= '1';

else
if (b(1)='1' and b(0)='0') then
c <=b3;
G <='1';
R <='0';
S <='0';
cin <= '0';
elsif (b(1)='0' and b(0)='1') then
c <=b3;
G <='1';
R <='1';
S <='0';
cin <= '0';
else
c <=b3;
G <='0';
R <='1';
S <='0';
end if;
end if;
end if;
elsif(s3 > 2 and s3 < 24) then
if sa=sb then
c <=b3;
G <= b(s3-1);
R <= b(s3-2);
if b(s3-3 downto 0) = temp2(s3-3 downto 0) then
S <='0' ;
else
s <='1';
end if;
cin <= '0';
elsif sa/=sb then
if b(s3-3 downto 0) = temp2(s3-3 downto 0) then
if (b(s3-1)='1' and b(s3-2)='1') then
c <=b3;
G <='0';
R <='1';
S <='0';

cin <= '0';

elsif (b(s3-1)='1' and b(s3-2)='0') then
c <=b3;
G <='1';
R <='0';
S <='0';
cin <= '0';
elsif (b(s3-1)='0' and b(s3-2)='1') then
c <=b3;
G <='1';
R <='1';
S <='0';
cin <= '0';
elsif (b(s3-1)='0' and b(s3-2)='0') then
c <=b3;
G <='0';
R <='0';
S <='0';
cin <= '1';
end if;
else
c <=b3;
G <= not(b(s3-1));
R <= not(b(s3-2));
S <='1';
cin <= '0';
end if;
end if;
elsif s3=24 then
if sa=sb then
c <=b3;
G <=b(23);
R <=b(22);
if b(21 downto 0) = temp2(21 downto 0) then
S <='0';
else
S <='1';
end if;
cin <= '0';
elsif sa/=sb then

if b(21 downto 0) = temp2(21 downto 0)then

if (b(23)='1' and b(22)='1') then
c <=b3;
G <='0';
R <='1';
S <='0';
cin <= '0';
elsif (b(23)='1' and b(22)='0') then
c <=b3;
G <='1';
R <='0';
S <='0';
cin <= '0';
elsif (b(23)='0' and b(22)='1') then
c <=b3;
G <='1';
R <='1';
S <='0';
cin <= '0';
elsif (b(24)='0' and b(23)='0') then
c <=b3;
G <='0';
R <='0';
S <='0';
cin <= '1';
end if;
else
c <=b3;
G <= not(b(23));
R <= not(b(22));
S <='1';
cin <= '0';
end if;
end if;
elsif s3=25 then
if sa=sb then
c <=b3;
G <=b(24);
R <=b(23);
if b(22 downto 0) = temp2(22 downto 0) then

S <='0';
else
S <='1';
end if;
cin <= '0';
elsif sa/=sb then
if b(22 downto 0) = temp2(22 downto 0)then
if (b(24)='1' and b(23)='1') then
c <=b3;
G <='0';
R <='1';
S <='0';
cin <= '0';
elsif (b(24)='1' and b(23)='0') then
c <=b3;
G <='1';
R <='0';
S <='0';
cin <= '0';
elsif (b(24)='0' and b(23)='1') then
c <=b3;
G <='1';
R <='1';
S <='0';
cin <= '0';
elsif (b(24)='0' and b(23)='0') then
c <=b3;
G <='0';
R <='0';
S <='0';
cin <= '1';
end if;
else
c <=b3;
G <= not(b(24));
R <= not(b(23));
S <='1';
cin <= '0';
end if;
end if;

elsif s3=26 then

if sa=sb then
c <=b3;
G <='0';
R <=b(24);
if b(23 downto 0)= temp2(23 downto 0) then
S <='0';
else
S <='1';
end if;
cin <= '0';
elsif sa/=sb then
if b(23 downto 0) = temp2(23 downto 0)then
if b(24)='1' then
c <=b3;
G <='1';
R <='1';
S <='0';
cin <= '0';
elsif b(24)='0' then
c <=b3;
G <='0';
R <='0';
S <='0';
cin <= '1';
end if;
else
c <=b3;
G <= '1';
R <= not b(24);
S <='1';
cin <= '0';
end if;
end if;
end if;
if s3>=27 then
if sa=sb then
c<=b3;
G<='0';

R<='0';
S<='0';
cin <= '0';
elsif sa/=sb then
c<=b3;
G<='1';
R<='1';
S<='0';
cin <= '0';
end if;
end if;
end process;
end shifter;
S chn:

3.5 Chng trnh khi adder:

Chng trnh :
------------khoi cong phan thap phan va xet dau-------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee_stdlogic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------entity add_sub is
port(
a, b : in std_logic_vector(24 downto 0); --a >= b
e,cin: in std_logic;
sa : in std_logic;

sb
: in std_logic;
s_out : out std_logic_vector(24 downto 0); -sign : out std_logic
cung
);
end add_sub;
---------------------------------architecture add_sub of add_sub is
signal s : std_logic_vector (24 downto 0);
component cla_adder1 is
port(
a, b
: in std_logic_vector(24 downto 0);
cin
: in std_logic;
s
: out std_logic_vector(24 downto 0)
);
end component;
begin
U1: component cla_adder1
port map (a, b,cin, s);
U2:
process(sa, sb, e)
begin
if (sa = '0' and sb = '0') then
sign <= '0';
elsif (sa = '1' and sb = '1') then
sign <= '1';
elsif (sa = '0' and sb = '1' and e = '0') then
sign <= '0';
elsif (sa = '0' and sb = '1' and e = '1') then
sign <= '1';
elsif (sa = '1' and sb = '0' and e = '0') then
sign <= '1';
elsif (sa = '1' and sb = '0' and e = '1') then
sign <= '0';
end if;
end process;
s_out <= s;

-- dau cua ket qua cuoi

end add_sub;
--------------------------------------------------------------------------------------------------------------

Chng trnh con:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------entity cla_adder is
port(
a, b : in std_logic_vector(24 downto 0);
s : out std_logic_vector(24 downto 0)
);
end cla_adder;
---------------------------------architecture cla_adder of cla_adder is
begin
s <= a + b;
end cla_adder;

S chn:

3.6 Chng trnh khi normalize1:

Chng trnh :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
---------------------------------------------------------------entity normalize is

port (

sa,sb :in std_logic;

ea,eb : in std_logic_vector(7 downto 0);
s_i
: in std_logic_vector(24 downto 0);
G, R, S : in std_logic;
s_a
: out std_logic_vector(24 downto 0);
shv
: out signed(4 downto 0);
R1, S1 : out std_logic
);
end normalize;
----------------------------------------------------------------architecture normalize of normalize is
signal s_temp
: std_logic_vector(24 downto 0);
signal temp1
: bit_vector(24 downto 0);
signal temp2
: bit_vector(24 downto 0);
signal shv1
: signed(4 downto 0);
signal temp3
: integer;
----------------------------------------------------------------component priority_encoder is
port(
a
: in std_logic_vector(24 downto 0);
shv : out signed(4 downto 0)
);
end component;
-----------------------------------------------------------------begin
U0: component priority_encoder
port map (s_i, shv1);
U1:process (s_i, shv1)
begin
temp1 <= to_bitvector(s_i);
temp3 <= to_integer(unsigned(shv1));
end process;
U2:process (s_i, shv1, temp1, temp3, G, R, S)
begin
if(shv1 = "11111") then
R1 <= s_i(0);
S1 <= G or R or S;
temp2 <= temp1 srl 1;

elsif(shv1 = "00000") then

R1 <= G;
S1 <= R or S;
temp2 <= temp1 sll temp3;
elsif(shv1 = "00001") then
if (sa/=sb and ea="00000000" ) then
R1 <= R;
S1 <= S;
temp2 <= temp1 ;
elsif (sa/=sb and eb="00000000" ) then
R1 <= R;
S1 <= S;
temp2 <= temp1 ;
else
R1 <= R;
S1 <= S;
temp2 <= temp1 sll temp3;
end if;
elsif(shv1 /= "11111" and shv1 /= "00000" and shv1 /= "00001") then
R1 <= '0';
S1 <= '0';
temp2 <= temp1 sll 1;
end if;
end process;
U3:process(temp2, temp3, shv1, G)
variable s_temp, s_temp1 : bit_vector(24 downto 0);
begin
s_temp := temp2;
if(shv1 = "00001") then
s_temp(0) := to_bit(G);
s_a <= to_stdlogicvector(s_temp);
elsif(shv1 /= "11111" and shv1 /= "00000" and shv1 /= "00001") then
s_temp(0) := to_bit(G);
s_temp1 := s_temp sll temp3-1;
s_a <= to_stdlogicvector(s_temp1);
else
s_a <= to_stdlogicvector(temp2);
end if;
end process;

shv <= shv1;

end normalize;
---------------------------------------------------------------------------------------------------------------

Chng trnh con:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
---------------------------------------------------------------entity priority_encoder is
port(
a
: in std_logic_vector(24 downto 0);
shv : out signed(4 downto 0)
);
end priority_encoder;
---------------------------------------------------------------architecture dataflow of priority_encoder is
begin
process(a)
begin
if (a(24) = '1') then shv <= "11111";
elsif (a(23) = '1') then shv <= "00000";
elsif (a(22) = '1') then shv <= "00001";
elsif (a(21) = '1') then shv <= "00010";
elsif (a(20) = '1') then shv <= "00011";
elsif (a(19) = '1') then shv <= "00100";
elsif (a(18) = '1') then shv <= "00101";
elsif (a(17) = '1') then shv <= "00110";
elsif (a(16) = '1') then shv <= "00111";
elsif (a(15) = '1') then shv <= "01000";
elsif (a(14) = '1') then shv <= "01001";
elsif (a(13) = '1') then shv <= "01010";
elsif (a(12) = '1') then shv <= "01011";
elsif (a(11) = '1') then shv <= "01100";
elsif (a(10) = '1') then shv <= "01101";
elsif (a(9) = '1') then shv <= "01110";
elsif (a(8) = '1') then shv <= "01111";
elsif (a(7) = '1') then shv <= "10000";
elsif (a(6) = '1') then shv <= "10001";

elsif (a(5) = '1')

elsif (a(4) = '1')
elsif (a(3) = '1')
elsif (a(2) = '1')
elsif (a(1) = '1')
elsif (a(0) = '1')
end if;
end process;
end dataflow;

then shv <= "10010";

then shv <= "10011";
then shv <= "10100";
then shv <= "10101";
then shv <= "10110";
then shv <= "10111";

S chn:

3.7 Chng trnh khi adjust:

Chng trnh:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
---------------------------------------------------------------entity adjust is
port ( exp_in : in std_logic_vector(7 downto 0);
shv
: in signed(4 downto 0);
exp_out : out std_logic_vector(7 downto 0)
);
end adjust;
----------------------------------------------------------------architecture adjust of adjust is
signal temp1, temp2, temp3 : integer;
begin
U0:process(shv, exp_in)

begin
temp3 <= to_integer(unsigned(shv));
temp1 <= to_integer(unsigned(exp_in));
end process;
U1:process (exp_in, shv, temp1, temp3)
begin
if(shv = "11111") then
temp2 <= temp1 + 1;
else
temp2 <= temp1 - temp3;
end if;
end process;
exp_out <= std_logic_vector(to_unsigned(temp2, 8));
end adjust;

S chn:

3.8 Chng trnh khi round:

Chng trnh :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------entity round is
port (
a
: in std_logic_vector(24 downto 0);
R, S : in std_logic;
b
: out std_logic_vector(24 downto 0)
);
end round;
---------------------------------------------------------------architecture round of round is
component cla_adder is

port( a, b
: in std_logic_vector(24 downto 0);
s
: out std_logic_vector(24 downto 0)
);
end component;
signal b1 : std_logic_vector(24 downto 0);
signal s1 : std_logic;
begin
U0:cla_adder port map (a, "0000000000000000000000001", b1);
U1:process (R, S, a, b1)
begin
if (R = '0') then b <= a;
elsif (R = '1' and S = '1') then b <= b1;
elsif (R = '1' and S = '0' and a(0) = '1') then b <= b1;
elsif (R = '1' and S = '0' and a(0) = '0') then b <= a;
end if;
end process;
end round;
-------------------------------------------------------------------------------------------------------

Chng trnh con:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------entity cla_adder is
port(
a, b : in std_logic_vector(24 downto 0);
s : out std_logic_vector(24 downto 0)
);
end cla_adder;
---------------------------------architecture cla_adder of cla_adder is
begin
s <= a + b;
end cla_adder;

S chn:

3.9 Chng trnh khi normalize2:

Chng trnh :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
---------------------------------------------------------------entity normalize2 is
port (
s
: in std_logic_vector(24 downto 0);
s_out : out std_logic_vector(24 downto 0);
shv
: out signed(4 downto 0)
);
end normalize2;
----------------------------------------------------------------architecture normalize2 of normalize2 is
signal temp1, temp2 : bit_vector(24 downto 0);
begin
temp1 <= to_bitvector(s);
U0:process(s, temp1)
begin
if(s(24) = '1') then
temp2 <= temp1 srl 1;
shv <= "11111";
else
temp2 <= temp1;
shv <= "00000";
end if;

end process;
s_out <= to_stdlogicvector(temp2);
end normalize2;

S chn:

3.10 Chng trnh chnh:

--************************************************************************
-- BO MON
: KY THUAT VI XU LI
-- TEN DO AN : THIET KE BO CONG SO THUC 32 BIT THEO CHUAN ANSI/IEEE-754
-- GIAO VIEN HUONG DAN:1. TRINH QUANG KIEN
-2. DAO VAN LAN
-- NHOM HOC VIEN
: 1. BUI VAN CHAU
-2. NGYEN VAN DUNG
-3. LE MINH DUONG
-4. NGUYEN TIEN GIANG
-5. DOI SY HOA
-- LOP
:
PHAO TAU- C145
--NGAY BAO CAO
:
26/11/2012
--************************************************************************
--************************************************************************
--*****************FLOATING POINT ADDER ************************----------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;
--------------------------------------------------------entity adder_fp is
port( a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0)
);
end adder_fp;
---------------------------------------------------------architecture structure of adder_fp is
signal ma1, mb1, mb2, mc1, mc2, mc3, mc : std_logic_vector(24 downto 0);
signal ma, mb: std_logic_vector(22 downto 0);
signal ea, eb, ec1, ec2, ec : std_logic_vector(7 downto 0);
signal e, sign, sa, sb, G1, R1, S1, R2, S2,cin,cin1 : std_logic;
signal shv1, shv2 : signed(4 downto 0);
signal s : integer;
component separate is
port ( a, b
: in std_logic_vector(31 downto 0);
sa, sb : out std_logic;
ea, eb : out std_logic_vector(7 downto 0);
ma, mb : out std_logic_vector(22 downto 0)
);
end component;
component subtract is
port( a, b
: in std_logic_vector(7 downto 0); --a>b
c
: out std_logic_vector(7 downto 0);
s
: out integer
);
end component;
component mux is
port (a
: in std_logic_vector(22 downto 0);
b
: in std_logic_vector(22 downto 0);
ea,eb : in std_logic_vector(7 downto 0);
s
: in integer;
c
: out std_logic_vector(24 downto 0);
d
: out std_logic_vector(24 downto 0);

: out std_logic
);
end component;
component shifter is
port (b
sa, sb
s0
c
G, R, S,cin
);
end component;

: in std_logic_vector(24 downto 0);

: in std_logic;
: in integer;
: out std_logic_vector(24 downto 0);
: out std_logic

component add_sub is
port( a, b
: in std_logic_vector(24 downto 0);
e,cin : in std_logic;
sa
: in std_logic;
sb
: in std_logic;
s_out : out std_logic_vector(24 downto 0);
sign : out std_logic
);
end component;
component normalize is
port ( sa,sb :in std_logic;
ea,eb : in std_logic_vector(7 downto 0);
s_i
: in std_logic_vector(24 downto 0);
G, R, S : in std_logic;
s_a
: out std_logic_vector(24 downto 0);
shv
: out signed(4 downto 0);
R1, S1 : out std_logic
);
end component;
component round is
port ( a
: in std_logic_vector(24 downto 0);
R, S : in std_logic;
b
: out std_logic_vector(24 downto 0)
);
end component;

component normalize2 is
port ( s
: in std_logic_vector(24 downto 0);
s_out : out std_logic_vector(24 downto 0);
shv
: out signed(4 downto 0)
);
end component;
component adjust is
port ( exp_in : in std_logic_vector(7 downto 0);
shv
: in signed(4 downto 0);
exp_out : out std_logic_vector(7 downto 0)
);
end component;
begin
U0: separate port map (a, b, sa, sb, ea, eb, ma, mb);
U1: subtract port map (ea, eb, ec1, s);
U2: mux
port map (ma, mb,ea,eb, s, ma1, mb1, e);
U3: shifter
port map (mb1, sa, sb, s, mb2, G1, R1, S1,cin1);
U4: add_sub
port map (ma1, mb2, e,cin1, sa, sb, mc1, sign);
U5: normalize port map (sa,sb,ea,eb,mc1, G1, R1, S1, mc2, shv1, R2, S2);
U6: adjust
port map (ec1, shv1, ec2);
U7: round
port map (mc2, R2, S2, mc3);
U8: normalize2 port map (mc3, mc, shv2);
U9: adjust
port map (ec2, shv2, ec);
-----------------------------------------------------------------process(a,b,mc,ec,sign)
begin
c <= sign & ec & mc(22 downto 0);
if(a(31)/= b(31) and a(30 downto 0)=b(30 downto 0)) then
c<=x"00000000";
end if;
if a(30 downto 23)="11111111" then
c(22 downto 0) <= "00000000000000000000001";
elsif b(30 downto 23)="11111111" then
c(22 downto 0) <= "00000000000000000000001";
--TH VO CUNG
--elsif a(30 downto 23)="11111111" and a(22 downto 0) = "0" then
-c(22 downto 0) <= "00000000000000000000001";

--elsif b(30 downto 23)="11111111" and b(22 downto 0) = "0" then

--c(22 downto 0) <= "00000000000000000000001";
end if;
end process;
end structure;

S chn ca b cng cn thit k:

IV . Kt qu m phng trong ModelSim v s dng ti nguyn trn Xilinx

ISE:
4.1 Kt qu m phng:

4.2.Kt qu tng hp mch trn ISE c tm tt bn di:

1. Ti nguyn s dng
=============================================================
*
Partition Report
*
=========================================================================
Partition Implementation Status
------------------------------No Partitions were found in this design.
------------------------------=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name
: adder_fp.ngr
Top Level Output File Name
: adder_fp
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 96
Cell Usage :
# BELS
: 2210

#
GND
: 1
#
INV
: 38
#
LUT1
: 1
#
LUT2
: 121
#
LUT3
: 196
#
LUT4
: 1158
#
MULT_AND
: 1
#
MUXCY
: 513
#
MUXF5
: 72
#
VCC
: 1
#
XORCY
: 108
# FlipFlops/Latches
: 84
#
LD
: 29
#
LDCP
: 54
#
LDE
: 1
# Clock Buffers
: 2
#
BUFG
: 2
# IO Buffers
: 96
#
IBUF
: 64
#
OBUF
: 32
=========================================================================
Device utilization summary:
--------------------------Selected Device : 3s500epq208-5
Number of Slices:
831 out of
4656
17%
Number of Slice Flip Flops:
84 out of
9312
0%
Number of 4 input LUTs:
1514 out of
9312
16%
Number of IOs:
96
Number of bonded IOBs:
96 out of
158
60%
Number of GCLKs:
2 out of
24
8%

2. Khng gian nh v thng tin v qu trnh bin dch

Total REAL time to Xst completion: 25.00 secs
Total CPU time to Xst completion: 25.10 secs
-->
Total memory usage
Number of errors
Number of warnings
Number of infos

is 219452 kilobytes
:
0 (
0 filtered)
:
53 (
0 filtered)
:
12 (
0 filtered)

V. Tng kt
Bi ton thit k b cng s thc c nhm chng em hon thnh, n
gii quyt tt c cc trng hp c th xy ra li, cc trng hp c bit. Tuy nhin,
bn cnh n ca chng em cn mt s hn ch l cha chy c trn mch
FPGA, cha ti u mt cch tt nht v ngn gn nht code VHDL.

Trong qu trnh lm n chng em xin c gi li cm n chn thnh nht n

cc thy Trnh Quang Kin v thy o Vn Ln tn tnh hng dn, gip
chng em c th hon thnh c d n ca mnh!
VI. Ti liu tham kho
1. Gio trnh Thit k logic s ca ThS. Trnh Quang Kin- Ths. L Xun Bng
2. IEEE 754.Standard for binary floating-point arithmetic.1985
3. 32 Bit Floating Point Adder