N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

ALU
1. Gii thiu : - Trong lab 2 ny chng ta xy dng khi ALU 32 bits vi nhim v thc hin cc lnh s hc n gin nh ADD, SUB , XOR , SLT . - ALU 32 bits c xy dng t 32 b alu 1 bit - y l khi x l mi cng vic tnh ton ca b vi x l . 2. Mc ch thit k: Thc hin thit k mt khi ALU n gin. Hai ng vo 32 bit, tn hiu iu khin 2 bt dng la chn mt trong bn php ton: add,sub,xor v slt. Ng ra c di 32 bit,ngoi ra cn c cc c bo hiu: overflow, zero, carryout, negative.

3. S khi :

Bus A

32

32 32 bit ALU Bus B 32 Zero Overflow CarryOut

Output

ALU Control

SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

Nguyn l hot ng ca khi ALU: Khi ALU c 2 u vo A,B mi u vo 32 bits. Khi ALU s da vo 2 bits ALU Control m s xc nh php ton cn x l Vd: ALU Control = 00 th s thc hin php A + B Kt qu cc php ton s c a ra Output 32 bits Ngoi ra cn c cc bits c : + Zero : s bng 1 khi kt qu u ra Output = 0 v bng 0 khi Output khc 0 + Overflow : s c set bng 1 khi thc hin cc php ton ADD , SUB c xy ra trn. + Carryout : s c set bng 1 trong cc php ton ADD, SUB khi xy ra c nh bits 31 + Negative : s c set bng 1 khi kt qu sau khi tnh ton l mt s m . - V tn hiu vo c 32 bit . Do ta ch cn gi 32 ln modul Calc_bit ( xy dng phn trn) thc hin ADD, SUB , XOR 32 bit theo th t t bit 0 n bit 31. Cch xc nh c Overflow nh sau:
CinAdd-cinSub

a 0 0 1 1 0 0 1 1

b 0 1 0 1 0 1 0 1

CAdd 0 0 0 1 0 1 1 1

outAdd 0 1 1 0 1 0 0 1

CSub 0 1 0 0 1 1 0 1

outSub 0 1 1 0 1 0 0 1

0 0 0 0 1 1 1 1

+ i vi php cng: 2 s hng ca php cng cng du nhng kt qu khc du vi 2 s hng . T bng, suy ra cch nhn bit thng qua bit nh: overflow xy ra khi bit nh cinAdd v CAdd ca MSB khc nhau.
SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

+ i vi php tr: s b tr l s dng v s tr l s m, kt qu l s m hoc s b tr l s m v s tr l s dng, kt qu l s dng. T bng, suy ra cch nhn bit thng qua bit mn: overflow xy ra khi bit mn cinSub v CSub ca MSB khc nhau. - Sau khi thc hin tnh ton, ta c c kt qu ca 4 php ton ADD, SUB, XOR v SLT. Cn c vo 2 bit iu khin port ALU control xc nh kt qu no s c a ra output port theo nh bng sau: ALUCONTROLLINES 00 01 10 11 FUNCTION Add XOR Sub SLT

Do , cn c khi chn knh MultiplexorOut 4) Thit k khi ALU 4.1) Thit k khi ADD, SUB v XOR a) Php Add Code: module add(a,b,s,cin,cout); input a,b,cin; wire c1,c2,c3; output cout,s; xor (s,a,b,cin); and (c1,a,b); or (c2,a,b); and (c3,c2,cin); or (cout,c1,c3); endmodule
SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

M phng:

b) Php Sub Code: module sub(a,b,d,bin,bout); input a,b,bin; output d,bout; not(b1,b); add add10(a,b1,d,bin,bout); endmodule

SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

M phng:

4.2)Khi chn knh MultiplexorOut 4.2.1) B MUX 2 TO 1: Code: module mux21(O,S,A,B); output O; input A,B,S; wire O1,O2,S0; not (S0,S); and (O1,A,S0); and (O2,B,S); or (O,O1,O2); endmodule

SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

M phng:

4.2.2) B MUX 4 TO 1 : Code: module mux412(x1,x2,x3,x5,c1,c2,y); input x1,x2,x3,x5,c1,c2; output y; wire a1,a2,a3,a4,a5,a6; not(a5,c1); not(a6,c2); and(a1,a5,x1,a6); and(a2,a5,x2,c2); and(a3,c1,x3,a6); and(a4,c1,c2,x5); or(y,a1,a2,a3,a4); endmodule
SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

M phng:

4.2.3) KHI MODULE ALU 0 BIT : Code: module alu0bit(a,b,carryout,result,ALUControl,less); input a,b,less; output carryout,result; input [0:1] ALUControl; assign carryinadd=0; assign carryinsub=1; wire carryout1,carryout2,addout,subout,xorout; add add1(a,b,addout,carryinadd,carryout1); sub sub1(a,b,subout,carryinsub,carryout2);
SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

xor(xorout,a,b); mux412 mux1(addout,xorout,subout,less,ALUControl[0],ALUControl[1],result); mux21 mux2(carryout,ALUControl[0],carryout1,carryout2); endmodule M phng:

SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

4.2.4)KHI MODULE ALU 1 BIT: Code: module alu1bit(a,b,carryin,carryout,result,ALUControl,less); input a,b,carryin,less; output carryout,result; input [0:1] ALUControl; wire carryout1,carryout2,addout,subout,xorout; add add1(a,b,addout,carryin,carryout1); sub sub1(a,b,subout,carryin,carryout2); xor(xorout,a,b); mux412 mux1(addout,xorout,subout,less,ALUControl[0],ALUControl[1],result); mux21 mux2(carryout,ALUControl[0],carryout1,carryout2); endmodule M phng:

SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

4.2.5) KHI MODULE ALU BIT 31: Code: module aluend1(a,b,carryin,carryout,result,set,ALUControl,overflow,negative,less); input a,b,carryin,less; output carryout,result,set,overflow,negative; input [0:1] ALUControl; wire carryout1,carryout2,addout,subout,xorout,x; add add1(a,b,addout,carryin,carryout1); sub sub1(a,b,subout,carryin,x); not(carryout2,x); xor(xorout,a,b); mux412 mux1(addout,xorout,subout,less,ALUControl[0],ALUControl[1],result); mux21 mux2(carryout,ALUControl[0],carryout1,carryout2); xor(overflow2,carryin,x); xor(overflow1,carryin,carryout); mux21 mux3(overflow,ALUControl[0],overflow1,overflow2); buf(negative,result); xor(set,subout,overflow); endmodule M phng:

SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

4.2.6) CODE KHI ALU TNG: Code: module alu(Output, CarryOut, zero, overflow, negative, BussA, BussB, ALUControl); input [0:31] BussA,BussB; output CarryOut,overflow,negative,zero; output [0:31] Output; assign less=0; input [0:1] ALUControl; wire set; wire carryout0,carryout1,carryout2,carryout3,carryout4,carryout5,carryout6,carryout7, carryout8,carryout9,carryout10,carryout11,carryout12,carryout13,carryout14,carryout15, carryout16,carryout17,carryout18,carryout19,carryout20,carryout21,carryout22,carryout23, carryout24,carryout25,carryout26,carryout27,carryout28,carryout29,carryout30; alu0bit alu0(BussA[31],BussB[31],carryout31,Output[31],ALUControl,set); alu1bit alu1(BussA[30],BussB[30],carryout31,carryout30,Output[30],ALUControl,less); alu1bit alu2(BussA[29],BussB[29],carryout30,carryout29,Output[29],ALUControl,less); alu1bit alu3(BussA[28],BussB[28],carryout29,carryout28,Output[28],ALUControl,less); alu1bit alu4(BussA[27],BussB[27],carryout28,carryout27,Output[27],ALUControl,less); alu1bit alu5(BussA[26],BussB[26],carryout27,carryout26,Output[26],ALUControl,less); alu1bit alu6(BussA[25],BussB[25],carryout26,carryout25,Output[25],ALUControl,less); alu1bit alu7(BussA[24],BussB[24],carryout25,carryout24,Output[24],ALUControl,less); alu1bit alu8(BussA[23],BussB[23],carryout24,carryout23,Output[23],ALUControl,less); alu1bit alu9(BussA[22],BussB[22],carryout23,carryout22,Output[22],ALUControl,less); alu1bit alu10(BussA[21],BussB[21],carryout22,carryout21,Output[21],ALUControl,less); alu1bit alu11(BussA[20],BussB[20],carryout21,carryout20,Output[20],ALUControl,less); alu1bit alu12(BussA[19],BussB[19],carryout20,carryout19,Output[19],ALUControl,less);
SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

alu1bit alu13(BussA[18],BussB[18],carryout19,carryout18,Output[18],ALUControl,less); alu1bit alu14(BussA[17],BussB[17],carryout18,carryout17,Output[17],ALUControl,less); alu1bit alu15(BussA[16],BussB[16],carryout17,carryout16,Output[16],ALUControl,less); alu1bit alu16(BussA[15],BussB[15],carryout16,carryout15,Output[15],ALUControl,less); alu1bit alu17(BussA[14],BussB[14],carryout15,carryout14,Output[14],ALUControl,less); alu1bit alu18(BussA[13],BussB[13],carryout14,carryout13,Output[13],ALUControl,less); alu1bit alu19(BussA[12],BussB[12],carryout13,carryout12,Output[12],ALUControl,less); alu1bit alu20(BussA[11],BussB[11],carryout12,carryout11,Output[11],ALUControl,less); alu1bit alu21(BussA[10],BussB[10],carryout11,carryout10,Output[10],ALUControl,less); alu1bit alu22(BussA[9],BussB[9],carryout10,carryout9,Output[9],ALUControl,less); alu1bit alu23(BussA[8],BussB[8],carryout9,carryout8,Output[8],ALUControl,less); alu1bit alu24(BussA[7],BussB[7],carryout8,carryout7,Output[7],ALUControl,less); alu1bit alu25(BussA[6],BussB[6],carryout7,carryout6,Output[6],ALUControl,less); alu1bit alu26(BussA[5],BussB[5],carryout6,carryout5,Output[5],ALUControl,less); alu1bit alu27(BussA[4],BussB[4],carryout5,carryout4,Output[4],ALUControl,less); alu1bit alu28(BussA[3],BussB[3],carryout4,carryout3,Output[3],ALUControl,less); alu1bit alu29(BussA[2],BussB[2],carryout3,carryout2,Output[2],ALUControl,less); alu1bit alu30(BussA[1],BussB[1],carryout2,carryout1,Output[1],ALUControl,less); aluend1 aluend11(BussA[0],BussB[0],carryout1,CarryOut,Output[0],set,ALUControl,overflow,negative, less); not(zero,Output[0]|Output[1]|Output[2]|Output[3]|Output[4]|Output[5]|Output[6]|Output[6]|O utput[7]|Output[8]| Output[9]|Output[10]|Output[11]|Output[12]|Output[13]|Output[14]|Output[15]|Output[16]| Output[17]|Output[18]|Output[19]|Output[20]|Output[21]|Output[22]|Output[23]|Output[24]| Output[25]|Output[26]| Output[27]|Output[28]|Output[29]|Output[30]|Output[31]);
SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

endmodule /*module alu bit thu 31*/ module aluend1(a,b,carryin,carryout,result,set,ALUControl,overflow,negative,less); input a,b,carryin,less; output carryout,result,set,overflow,negative; input [0:1] ALUControl; wire carryout1,carryout2,addout,subout,xorout,x; add add1(a,b,addout,carryin,carryout1); sub sub1(a,b,subout,carryin,x); not(carryout2,x); xor(xorout,a,b); mux412 mux1(addout,xorout,subout,less,ALUControl[0],ALUControl[1],result); mux21 mux2(carryout,ALUControl[0],carryout1,carryout2); xor(overflow2,carryin,x); xor(overflow1,carryin,carryout); mux21 mux3(overflow,ALUControl[0],overflow1,overflow2); buf(negative,result); xor(set,subout,overflow); endmodule /*module alu 1 bit */ module alu1bit(a,b,carryin,carryout,result,ALUControl,less); input a,b,carryin,less; output carryout,result; input [0:1] ALUControl; wire carryout1,carryout2,addout,subout,xorout;
SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

add add1(a,b,addout,carryin,carryout1); sub sub1(a,b,subout,carryin,carryout2); xor(xorout,a,b); mux412 mux1(addout,xorout,subout,less,ALUControl[0],ALUControl[1],result); mux21 mux2(carryout,ALUControl[0],carryout1,carryout2); endmodule /*bo chon 4 to 1 */ module mux412(x1,x2,x3,x5,c1,c2,y); input x1,x2,x3,x5,c1,c2; output y; wire a1,a2,a3,a4,a5,a6; not(a5,c1); not(a6,c2); and(a1,a5,x1,a6); and(a2,a5,x2,c2); and(a3,c1,x3,a6); and(a4,c1,c2,x5); or(y,a1,a2,a3,a4); endmodule /*phep cong */ module add(a,b,s,cin,cout); input a,b,cin; wire c1,c2,c3; output cout,s; xor (s,a,b,cin); and (c1,a,b);
SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

or (c2,a,b); and (c3,c2,cin); or (cout,c1,c3); endmodule /*phep tru */ module sub(a,b,d,bin,bout); input a,b,bin; output d,bout; not(b1,b); add add10(a,b1,d,bin,bout); endmodule /*bo chon 2 to 1 */ module mux21(O,S,A,B); output O; input A,B,S; wire O1,O2,S0; not (S0,S); and (O1,A,S0); and (O2,B,S); or (O,O1,O2); endmodule //===================== module alu0bit(a,b,carryout,result,ALUControl,less); input a,b,less; output carryout,result; input [0:1] ALUControl;
SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

assign carryinadd=0; assign carryinsub=1; wire carryout1,carryout2,addout,subout,xorout; add add1(a,b,addout,carryinadd,carryout1); sub sub1(a,b,subout,carryinsub,carryout2); xor(xorout,a,b); mux412 mux1(addout,xorout,subout,less,ALUControl[0],ALUControl[1],result); mux21 mux2(carryout,ALUControl[0],carryout1,carryout2); endmodule

M phng bng QUARTUS

alu0bit:alu0 BussA[0. 31] BussB[0. 31] ALUControl[0. 1]
a b less ALUControl[0. 1] carryout result

comb~31 zero

alu1bit:alu1
a a b b carryout carryin result 0 less ALUControl[0. 1] ALUControl[0. 1] 0 less carryin

alu1bit:alu2
a b

alu1bit:alu3
a b

alu1bit:alu4
a b

alu1bit:alu5
a b

alu1bit:alu6
a b

alu1bit:alu7
a b

alu1bit:alu8
a b

alu1bit:alu9
a b

alu1bit:alu10
a b

alu1bit:alu11
a b

alu1bit:alu12
a b

alu1bit:alu13
a b

alu1bit:alu14
a b

alu1bit:alu15
a b

alu1bit:alu16
a b

alu1bit:alu17
a b

alu1bit:alu18
a b

alu1bit:alu19
a b

alu1bit:alu20
a b

alu1bit:alu21
a b

alu1bit:alu22
a b

alu1bit:alu23
a b

alu1bit:alu24
a b

alu1bit:alu25
a b

alu1bit:alu26
a b

alu1bit:alu27
a b

alu1bit:alu28
a b

alu1bit:alu29
a b

alu1bit:alu30
a b carryout carryout carryin result result 0 less ALUControl[0. 1] 0 less carryin

aluend1:aluend11
carryout result set overflow negative

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

overflow negative CarryOut

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout carryout carryin result result 0 less ALUControl[0. 1]

carryin 0 less ALUControl[0. 1]

carryout result

carryin 0 less ALUControl[0. 1]

Output[0. 31]

SVTH: CN BNH TUN

 N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

M phng bng ModelSim

SVTH: CN BNH TUN