Bao Cao Lab 3

N VI X L & CU TRC MY TNH
GVHD: TR N TH MINH HNH
MIPS SINGLE-CYCLE CPU I.Gii thiu tng quan: - Bi lab ny chng ta s thit k mt CPU single cycle MIPS 32bit. Cc lnh CPU thc thi c l LW, SW, J, JR, BNE, XORI, ADD, SUB v SLT vi cc cu trc lnh nh sau: ADD rd, rs, rt: Reg[rd] = Reg[rs] + Reg[rt]. BNE rs, rt, imm16: if (Reg[rs] != Reg[rt]) PC = PC + 4 + Sign_ext(Imm16)<<2 else PC = PC + 4. J target: PC = { PC[31:28], target, 00 }. JR rs: PC = Reg[rs]. LW rt, imm16(rs): Reg[rt] = Mem[Reg[rs] + Sign_ext(Imm16)]. SLT rd, rs, rt: If (Reg[rs] < Reg[rt]) Reg[rd] = 0000000116 else Reg[rd] = 0000000016. SUB rd, rs, rt: Reg[rd] = Reg[rs] Reg[rt]. SW rt, imm16(rs): Mem[Reg[rs] + Sign_ext(Imm16)] = Reg[rt]. XORI rt, rs, imm16: Reg[rt] = Reg[rs] XOR Zero_ext(Imm16). - Datapath ca mt CPU single cycle MIPS 32bit bao gm cc khi cn thit sau: Khi PC 32-bit Instruction memory 32 bit Khi thanh ghi MIPS Register 32 bit ALU Data memory 32 bit Control Unit ALU Control Unit Add Shift left 2 Extender Mt s MUX 5 bit v 32 bit. - Cc khi MIPS Register 32 bit v ALU thc hin cc bi lab trc.
SVTH: CN _ BNH _ TUN
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II.Trnh t thc hin: 1. Khi PC 32-bit: - PC dng tm lnh cho vi x l. - Gi tr ra ca PC chnh l a ch lnh cho instruction memory. - Cp nht gi tr cho PC: Cc lnh lin tc: PC <- PC + 4 Cc lnh nhy, r nhnh: PC <- something else - Do , thc cht PC ng vai tr nh mt thanh ghi n gin, c nhim v m gi tr u vo. Code: module PC_bit(PCout,PCin); input PCin; output PCout; reg PCout;
SVTH: CN _ BNH _ TUN Page 2
initial begin PCout=1'b0; end always #14000 begin PCout=PCin; end //always @(PCin) //PCout=PCin; endmodule module PC(PCout,PCin); input [31:0] PCin; output [31:0] PCout; //reg [31:0] PCout; //PCout = {PCin}; PC_bit Buf0 (PCout[0],PCin[0]); PC_bit Buf1 (PCout[1],PCin[1]); PC_bit Buf2 (PCout[2],PCin[2]); PC_bit Buf3 (PCout[3],PCin[3]); PC_bit Buf4 (PCout[4],PCin[4]); PC_bit Buf5 (PCout[5],PCin[5]); PC_bit Buf6 (PCout[6],PCin[6]); PC_bit Buf7 (PCout[7],PCin[7]); PC_bit Buf8 (PCout[8],PCin[8]); PC_bit Buf9 (PCout[9],PCin[9]); PC_bit Buf10(PCout[10],PCin[10]); PC_bit Buf11(PCout[11],PCin[11]); PC_bit Buf12(PCout[12],PCin[12]); PC_bit Buf13(PCout[13],PCin[13]); PC_bit Buf14(PCout[14],PCin[14]); PC_bit Buf15(PCout[15],PCin[15]); PC_bit Buf16(PCout[16],PCin[16]); PC_bit Buf17(PCout[17],PCin[17]); PC_bit Buf18(PCout[18],PCin[18]); PC_bit Buf19(PCout[19],PCin[19]); PC_bit Buf20(PCout[20],PCin[20]); PC_bit Buf21(PCout[21],PCin[21]); PC_bit Buf22(PCout[22],PCin[22]); PC_bit Buf23(PCout[23],PCin[23]); PC_bit Buf24(PCout[24],PCin[24]);
PC_bit PC_bit PC_bit PC_bit PC_bit PC_bit PC_bit endmodule
Buf25(PCout[25],PCin[25]); Buf26(PCout[26],PCin[26]); Buf27(PCout[27],PCin[27]); Buf28(PCout[28],PCin[28]); Buf29(PCout[29],PCin[29]); Buf30(PCout[30],PCin[30]); Buf31(PCout[31],PCin[31]);
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PC_bit:Buf31 PCin[31..0]
PCin
PCout
PC_bit:Buf30
PCin
PCout
PC_bit:Buf29
PCin
PCout
PC_bit:Buf28
PCin
PCout
PC_bit:Buf27
PCin
PCout
PC_bit:Buf26
PCin
PCout
PC_bit:Buf25
PCin
PCout
PC_bit:Buf24
PCin
PCout
PC_bit:Buf23
PCin
PCout
PC_bit:Buf22
PCin
PCout
PC_bit:Buf21
PCin
PCout
PC_bit:Buf20
PCin
PCout
PC_bit:Buf19
PCin
PCout
PC_bit:Buf18
PCin
PCout
PC_bit:Buf17
PCin
PCout
PC_bit:Buf16
PCin
PCout
PC_bit:Buf15 PCout[31..0]
PCin
PCout
PC_bit:Buf14
PCin
PCout
PC_bit:Buf13
PCin
PCout
PC_bit:Buf12
PCin
PCout
PC_bit:Buf11
PCin
PCout
PC_bit:Buf10
PCin
PCout
PC_bit:Buf9
PCin
PCout
PC_bit:Buf8
PCin
PCout
PC_bit:Buf7
PCin
PCout
PC_bit:Buf6
PCin
PCout
PC_bit:Buf5
PCin
PCout
PC_bit:Buf4
PCin
PCout
PC_bit:Buf3
PCin
PCout
PC_bit:Buf2
PCin
PCout
PC_bit:Buf1
PCin
PCout
PC_bit:Buf0
PCin
PCout
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2. Instruction memory 32 bit: - Cha cc gi tr lnh ca CPU di dng nh phn 32 bit. - u vo ca Instruction Mem chnh l a ch lnh 32 bit. - a ch lnh ca MIPS c nh a ch theo byte u tin trong mt word. Do cc a ch ca word l bi ca 4. Code: module InstructionMem(instruction, address); input [31:0] address; output [31:0] instruction; reg [31:0]instrmem[1023:0]; reg [31:0] temp; buf #150 buf0(instruction[0],temp[0]), buf1(instruction[1],temp[1]), buf2(instruction[2],temp[2]), buf3(instruction[3],temp[3]), buf4(instruction[4],temp[4]), buf5(instruction[5],temp[5]), buf6(instruction[6],temp[6]), buf7(instruction[7],temp[7]), buf8(instruction[8],temp[8]), buf9(instruction[9],temp[9]), buf10(instruction[10],temp[10]), buf11(instruction[11],temp[11]), buf12(instruction[12],temp[12]), buf13(instruction[13],temp[13]), buf14(instruction[14],temp[14]), buf15(instruction[15],temp[15]), buf16(instruction[16],temp[16]), buf17(instruction[17],temp[17]), buf18(instruction[18],temp[18]), buf19(instruction[19],temp[19]), buf20(instruction[20],temp[20]), buf21(instruction[21],temp[21]), buf22(instruction[22],temp[22]), buf23(instruction[23],temp[23]), buf24(instruction[24],temp[24]), buf25(instruction[25],temp[25]), buf26(instruction[26],temp[26]), buf27(instruction[27],temp[27]), buf28(instruction[28],temp[28]), buf29(instruction[29],temp[29]),
buf30(instruction[30],temp[30]), buf31(instruction[31],temp[31]); always @(address) begin temp=instrmem[address/4]; end initial begin $readmemh("instr.dat", instrmem); end endmodule
instrmem
0 WE 32' h00000000 -10' h000 -DATAIN[31..0] DATAOUT[31..0] WADDR[9..0] RADDR[9..0] SYNC_RAM BUF (SOFT)
buf[31..0] instruction[31..0]
address[31..0]
3.Data Memory: - C th thao tc c v ghi c iu khin bi cc tn hiu: MemRead. MemWrite. - u vo ca Datamem l a ch d liu, c nh a ch theo byte ging nh a ch lnh v gi tr cn ghi Write Data nu MemWrite =1. - u ra l gi tr c c t b nh khi MemRead = 1. Code: module datamem(data, address, writedata, writeenable,readenable, clk); input [31:0] address, writedata; input writeenable, readenable, clk; output [31:0] data; reg [7:0] datamem[1023:0]; reg [31:0] temp;
buf #1000 buf0(data[0],temp[0]), buf1(data[1],temp[1]), buf2(data[2],temp[2]), buf3(data[3],temp[3]), buf4(data[4],temp[4]), buf5(data[5],temp[5]), buf6(data[6],temp[6]), buf7(data[7],temp[7]), buf8(data[8],temp[8]), buf9(data[9],temp[9]), buf10(data[10],temp[10]), buf11(data[11],temp[11]), buf12(data[12],temp[12]), buf13(data[13],temp[13]), buf14(data[14],temp[14]), buf15(data[15],temp[15]), buf16(data[16],temp[16]), buf17(data[17],temp[17]), buf18(data[18],temp[18]), buf19(data[19],temp[19]), buf20(data[20],temp[20]), buf21(data[21],temp[21]), buf22(data[22],temp[22]), buf23(data[23],temp[23]), buf24(data[24],temp[24]), buf25(data[25],temp[25]), buf26(data[26],temp[26]), buf27(data[27],temp[27]), buf28(data[28],temp[28]), buf29(data[29],temp[29]), buf30(data[30],temp[30]), buf31(data[31],temp[31]); always @(posedge clk) if (writeenable) begin
datamem[address]=writedata[31:24]; datamem[address+1]=writedata[23:16]; datamem[address+2]=writedata[15:8]; datamem[address+3]=writedata[7:0]; $writememh("data.dat",datamem); end always @(address or datamem[address] or datamem[address+1] or datamem[address+2] or datamem[address+3]) begin temp={datamem[address],datamem[address+1],datamem[ad dress+2],datamem[address+3]}; end initial begin $readmemh("data.dat", datamem); end endmodule
4. Add: -Dng to ra gi tr PC+4 hoc a ch ca lnh r nhnh. Code: module add(Add_In1,Add_In2,out_Add); input [31:0] Add_In1; input [31:0] Add_In2; output [31:0] out_Add; wire [31:0] Cout; add_bit bit0(Add_In1[0],Add_In2[0], 1'b0, out_Add[0], Cout[0]) ; add_bit bit1(Add_In1[1],Add_In2[1], Cout[0], out_Add[1], Cout[1]) ; add_bit bit2(Add_In1[2],Add_In2[2], Cout[1], out_Add[2], Cout[2]) ;
add_bit bit3(Add_In1[3],Add_In2[3], Cout[2], out_Add[3], Cout[3]); add_bit bit4(Add_In1[4],Add_In2[4], Cout[3], out_Add[4], Cout[4]); add_bit bit5(Add_In1[5],Add_In2[5], Cout[4], out_Add[5], Cout[5]); add_bit bit6(Add_In1[6],Add_In2[6], Cout[5], out_Add[6], Cout[6]); add_bit bit7(Add_In1[7],Add_In2[7], Cout[6], out_Add[7], Cout[7]); add_bit bit8(Add_In1[8],Add_In2[8], Cout[7], out_Add[8], Cout[8]); add_bit bit9(Add_In1[9],Add_In2[9], Cout[8], out_Add[9], Cout[9]); add_bit bit10(Add_In1[10],Add_In2[10], Cout[9], out_Add[10], Cout[10]); add_bit bit11(Add_In1[11],Add_In2[11], Cout[10], out_Add[11], Cout[11]); add_bit bit12(Add_In1[12],Add_In2[12], Cout[11], out_Add[12], Cout[12]); add_bit bit13(Add_In1[13],Add_In2[13], Cout[12], out_Add[13], Cout[13]); add_bit bit14(Add_In1[14],Add_In2[14], Cout[13], out_Add[14], Cout[14]); add_bit bit15(Add_In1[15],Add_In2[15], Cout[14], out_Add[15], Cout[15]); add_bit bit16(Add_In1[16],Add_In2[16], Cout[15], out_Add[16], Cout[16]); add_bit bit17(Add_In1[17],Add_In2[17], Cout[16], out_Add[17], Cout[17]); add_bit bit18(Add_In1[18],Add_In2[17], Cout[17], out_Add[18], Cout[18]); add_bit bit19(Add_In1[19],Add_In2[19], Cout[18], out_Add[19], Cout[19]); add_bit bit20(Add_In1[20],Add_In2[20], Cout[19], out_Add[20], Cout[20]); add_bit bit21(Add_In1[21],Add_In2[21], Cout[20], out_Add[21], Cout[21]); add_bit bit22(Add_In1[22],Add_In2[22], Cout[21], out_Add[22], Cout[22]); add_bit bit23(Add_In1[23],Add_In2[23], Cout[22], out_Add[23], Cout[23]); add_bit bit24(Add_In1[24],Add_In2[24], Cout[23], out_Add[24], Cout[24]);
add_bit bit25(Add_In1[25],Add_In2[25], Cout[24], out_Add[25], Cout[25]); add_bit bit26(Add_In1[26],Add_In2[26], Cout[25], out_Add[26], Cout[26]); add_bit bit27(Add_In1[27],Add_In2[27], Cout[26], out_Add[27], Cout[27]); add_bit bit28(Add_In1[28],Add_In2[28], Cout[27], out_Add[28], Cout[28]); add_bit bit29(Add_In1[29],Add_In2[29], Cout[28], out_Add[29], Cout[29]); add_bit bit30(Add_In1[30],Add_In2[30], Cout[29], out_Add[30], Cout[30]); add_bit bit31(Add_In1[31],Add_In2[31], Cout[30], out_Add[31], Cout[31]); endmodule module add_bit(a, b, cin_Add, out_Add, Cout_Add); input a, b, cin_Add; output out_Add, Cout_Add; wire a_xor_b; xor #(50) U1(a_xor_b, a, b); xor #(50) U2(out_Add, a_xor_b, cin_Add); or #(50) U5(Cout_Add, a_xor_b & cin_Add, a & b); endmodule
add_bit:bit24
a a a a a a a a a a a a a a a a a a a a a a a a a a out_Add b Cout_Add 0 cin_Add cin_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add out_Add b Cout_Add cin_Add
add_bit:bit25
a
add_bit:bit26
a out_Add b
add_bit:bit27
a out_Add Cout_Add b
add_bit:bit28
a out_Add Cout_Add cin_Add b
add_bit:bit29
a out_Add Cout_Add cin_Add b
add_bit:bit30
a out_Add Cout_Add cin_Add b cin_Add
add_bit:bit31
out_Add
add_bit:bit0 Add_In1[31..0] Add_In2[31..0]
add_bit:bit1
add_bit:bit2
add_bit:bit3
add_bit:bit4
add_bit:bit5
add_bit:bit6
add_bit:bit7
add_bit:bit8
add_bit:bit9
add_bit:bit10
add_bit:bit11
add_bit:bit12
add_bit:bit13
add_bit:bit14
add_bit:bit15
add_bit:bit16
add_bit:bit17
add_bit:bit18
add_bit:bit19
add_bit:bit20
add_bit:bit21
add_bit:bit22
add_bit:bit23
out_Add[31..0]
5. MODULE EXTEND : - C nhim v m rng gi tr ng vo 16 bit thnh 32 bit. - Ty thuc vo gi tr ca tn hiu iu khin ex_control m Extend s m rng du hoc m rng 0 + ex_control =1: m rng du, dng cho lnh LW,SW,BNE.
+ ex_control =0: m rng 0, dng cho lnh XORI.
Code: module sign_extend(In16, ex_control,Out32); input [15:0] In16; output [31:0] Out32; input ex_control; assign Out32[15:0]=In16; and #(50) and1(Out32[16],ex_control,In16[15]); and #(50) and2(Out32[17],ex_control,In16[15]); and #(50) and3(Out32[18],ex_control,In16[15]); and #(50) and4(Out32[19],ex_control,In16[15]); and #(50) and5(Out32[20],ex_control,In16[15]); and #(50) and6(Out32[21],ex_control,In16[15]); and #(50) and7(Out32[22],ex_control,In16[15]); and #(50) and8(Out32[23],ex_control,In16[15]); and #(50) and9(Out32[24],ex_control,In16[15]); and #(50) and10(Out32[25],ex_control,In16[15]); and #(50) and11(Out32[26],ex_control,In16[15]); and #(50) and12(Out32[27],ex_control,In16[15]); and #(50) and13(Out32[28],ex_control,In16[15]); and #(50) and14(Out32[29],ex_control,In16[15]); and #(50) and15(Out32[30],ex_control,In16[15]); and #(50) and16(Out32[31],ex_control,In16[15]); endmodule Kt qu:
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and16 In16[15..0] ex_control and15
and14 Out32[31..0] and13
and12
and11
and10
and9
and8
and7
and6
and5
and4
and3
and2
and1
6. Shift left 2: - C nhim v dch tri 2 bt phc v cho lnh BNE khi a ch r nhnh ti l gi tr 16 bt (15:0) v cho vic r nhnh ca lnh J: Code: module shift_left2(In32, Out32); input [31:0] In32; output [31:0] Out32; assign Out32 = {In32[29:0],2'b00}; endmodule Kt qu:
In32[31..0]
2' h0 --
Out32[31..0]
7.Khi ALU Control: iu khin cho ALU thc hin ng chc nng tng ng nh trong bi lab2, ta cn to ra tn hiu iu khin t cc bit Function v bit iu khin ALUOp theo bng sau:
ALUop 00 01 11 10 10 10 10 10 Code:
op xxxxxx xxxxxx xxxxxx 100000 100110 100010 101010 001000
ALUcontrol 00 10 01 00 01 10 11 00
Jr_control 0 0 0 0 0 0 0 1
module ALU_control(ALUcontrol,jr_control, ALUop, Instr); output [1:0] ALUcontrol; output jr_control; input [1:0] ALUop; input [5:0] Instr; wire [2:0] and_funct; wire [2:0] and_aluct; and #(50) and1(and_funct[0],(~Instr[4]),(~Instr[2]),(~Instr[0])); and #(50) and2(and_aluct[0],ALUop[1],(~ALUop[0])); and #(50) and3(and_aluct[1],(~ALUop[1]),ALUop[0]); and #(50) and4(and_aluct[2],ALUop[1],ALUop[0]); and #(50) and5(and_funct[1],and_aluct[0],and_funct[0],Instr[1]); and #(50) and6(and_funct[2],and_funct[1],Instr[3]); and #(50) and_jr(jr_control,and_aluct[0],(~Instr[5]),Instr[3],(~Instr[1]),and_fu nct[0]); or #(50) or_alu1(ALUcontrol[1],and_aluct[1],and_funct[1]); or #(50) or_alu2(ALUcontrol[0],and_aluct[2],and_funct[2]);
endmodule
Instr[5..0] and1 and5 and6 or_alu2
and2 ALUop[1..0] and_jr jr_control and4
and3
or_alu1 ALUcontrol[1..0]
8. Control Unit: Control unit to ra cc tn hiu iu khin cho cc khi trong datapath t 6 bit Opcode theo bng sau:
Code: module Control(Opcode, ex_control, RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite); input [31:26] Opcode;
output ex_control,RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite; reg ex_control,RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite; output [1:0] ALUOp; reg [1:0] ALUOp; always #200 casex (Opcode) 6'b000000 : begin : Rtype ex_control=1'bX; RegDst = 1'b1; Jump = 1'b0; Branch = 1'b0; MemRead = 1'b0; MemtoReg = 1'b0; ALUOp = 2'b10; MemWrite = 1'b0; ALUSrc = 1'b0; RegWrite = 1'b1; end 6'b100011 : begin : lw ex_control=1'b1; RegDst = 1'b0; Jump = 1'b0; Branch = 1'b0; MemRead = 1'b1; MemtoReg = 1'b1; ALUOp = 2'b00; MemWrite = 1'b0; ALUSrc = 1'b1; RegWrite = 1'b1; end 6'b101011 : begin : sw ex_control=1'b1;
RegDst = 1'bx; Jump = 1'b0; Branch = 1'b0; MemRead = 1'b0; MemtoReg = 1'bx; ALUOp = 2'b00; MemWrite = 1'b1; ALUSrc = 1'b1; RegWrite = 1'b0; end 6'b000101 : begin : bne ex_control=1'b1; RegDst = 1'bx; Jump = 1'b0; Branch = 1'b1; MemRead = 1'b0; MemtoReg = 1'bx; ALUOp = 2'b01; MemWrite = 1'b0; ALUSrc = 1'b0; RegWrite = 1'b0; end 6'b000010 : begin : j ex_control=1'bx; RegDst = 1'bx; Jump = 1'b1; Branch = 1'b0; MemRead = 1'b0; MemtoReg = 1'bx; ALUOp = 2'bxx; MemWrite = 1'b0; ALUSrc = 1'bx; RegWrite = 1'b0;
end 6'b001110 : begin : xori ex_control=1'b0; RegDst = 1'b0; Jump = 1'b0; Branch = 1'b0; MemRead = 1'b0; MemtoReg = 1'b0; ALUOp = 2'b11; MemWrite = 1'b0; ALUSrc = 1'b1; RegWrite = 1'b1; end endcase endmodule
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Decoder0 Mem toReg~0 Opcode[31..26]

IN[5..0] OUT[63..0] D ENA CLR DECODER
ALUOp[1]$latch
PRE Q
ALUOp[0]$latch
PRE D ENA CLR Q
ALUOp[1..0]
ex_control$latch
PRE D ENA CLR Q
ex_control
RegDs t$latch
PRE D ENA CLR Q
RegDs t
Jum p$latch
PRE D ENA CLR Q
Jum p
Branch$latch
PRE D ENA CLR Q
Branch
WideOr0 Mem Read$latch

PRE D ENA CLR Q
Mem Read
Mem toReg$latch
PRE D ENA CLR Q
Mem toReg
WideOr6
Mem Write$latch
PRE D ENA CLR Q
Mem Write
ALUSrc~0
ALUSrc$latch
PRE D ENA CLR Q
ALUSrc
WideOr9
RegWrite$latch
PRE D ENA CLR Q
RegWrite
ALUOp~0
Page 19
9. Cc khi Mux: a. Mux chn u ra 1 bt vi 2 u vo 1 bt v bt iu khin: Mux ny c nhim v to hm con thc hin b Mux chn u ra 5 bt vi 2 u vo 5 bt v bt iu khin: CODE: module mux2to1(DataIn0, DataIn1, Sel, DataOut); input DataIn0, DataIn1, Sel; output DataOut; wire Data0, Data1; and #(50) Sel0(Data0, DataIn0, (~Sel)); and #(50) Sel1(Data1, DataIn1, Sel ); or #(50) Out0(DataOut, Data0, Data1); endmodule
Sel0 Sel DataIn0 Sel1 DataIn1 Out0 DataOut
b.Mux chn u ra 5 bt vi 2 u vo 5 bt v bt iu khin: module mux2x5to5(AddressIn0, AddressIn1, Sel, AddressOut); input [4:0] AddressIn0, AddressIn1; input Sel; output [4:0] AddressOut; mux2to1 SelAddress0(AddressIn0[0], AddressIn1[0], Sel, AddressOut[0]); mux2to1 SelAddress1(AddressIn0[1], AddressIn1[1], Sel, AddressOut[1]); mux2to1 SelAddress2(AddressIn0[2], AddressIn1[2], Sel, AddressOut[2]); mux2to1 SelAddress3(AddressIn0[3], AddressIn1[3], Sel, AddressOut[3]);
mux2to1 SelAddress4(AddressIn0[4], AddressIn1[4], Sel, AddressOut[4]); endmodule
mux2to1:SelAddres s 4 Addres s In0[4..0] Addres s In1[4..0] Sel

DataIn0 DataIn1 Sel DataOut
mux2to1:SelAddres s 3
Addres s Out[4..0]
c.Mux chn u ra 32 bt t 2 u vo 32 bt v mt u vo iu khin 1 bt: module mux2x32to32(DataIn0, DataIn1, Sel, DataOut); input [31:0] DataIn0, DataIn1; input Sel; output [31:0] DataOut; mux2to1 mux0 (DataIn0[0 ], DataIn1[0 ], Sel, DataOut[0 ]); mux2to1 mux1 (DataIn0[1 ], DataIn1[1 ], Sel, DataOut[1 ]); mux2to1 mux2 (DataIn0[2 ], DataIn1[2 ], Sel, DataOut[2 ]); mux2to1 mux3 (DataIn0[3 ], DataIn1[3 ], Sel, DataOut[3 ]);
mux2to1 mux4 (DataIn0[4 ], DataIn1[4 ], Sel, DataOut[4 ]); mux2to1 mux5 (DataIn0[5 ], DataIn1[5 ], Sel, DataOut[5 ]); mux2to1 mux6 (DataIn0[6 ], DataIn1[6 ], Sel, DataOut[6 ]); mux2to1 mux7 (DataIn0[7 ], DataIn1[7 ], Sel, DataOut[7 ]); mux2to1 mux8 (DataIn0[8 ], DataIn1[8 ], Sel, DataOut[8 ]); mux2to1 mux9 (DataIn0[9 ], DataIn1[9 ], Sel, DataOut[9 ]); mux2to1 mux10(DataIn0[10], DataIn1[10], Sel, DataOut[10]); mux2to1 mux11(DataIn0[11], DataIn1[11], Sel, DataOut[11]); mux2to1 mux12(DataIn0[12], DataIn1[12], Sel, DataOut[12]); mux2to1 mux13(DataIn0[13], DataIn1[13], Sel, DataOut[13]); mux2to1 mux14(DataIn0[14], DataIn1[14], Sel, DataOut[14]); mux2to1 mux15(DataIn0[15], DataIn1[15], Sel, DataOut[15]); mux2to1 mux16(DataIn0[16], DataIn1[16], Sel, DataOut[16]); mux2to1 mux17(DataIn0[17], DataIn1[17], Sel, DataOut[17]); mux2to1 mux18(DataIn0[18], DataIn1[18], Sel, DataOut[18]); mux2to1 mux19(DataIn0[19], DataIn1[19], Sel, DataOut[19]); mux2to1 mux20(DataIn0[20], DataIn1[20], Sel, DataOut[20]); mux2to1 mux21(DataIn0[21], DataIn1[21], Sel, DataOut[21]); mux2to1 mux22(DataIn0[22], DataIn1[22], Sel, DataOut[22]); mux2to1 mux23(DataIn0[23], DataIn1[23], Sel, DataOut[23]); mux2to1 mux24(DataIn0[24], DataIn1[24], Sel, DataOut[24]); mux2to1 mux25(DataIn0[25], DataIn1[25], Sel, DataOut[25]); mux2to1 mux26(DataIn0[26], DataIn1[26], Sel, DataOut[26]); mux2to1 mux27(DataIn0[27], DataIn1[27], Sel, DataOut[27]); mux2to1 mux28(DataIn0[28], DataIn1[28], Sel, DataOut[28]); mux2to1 mux29(DataIn0[29], DataIn1[29], Sel, DataOut[29]); mux2to1 mux30(DataIn0[30], DataIn1[30], Sel, DataOut[30]); mux2to1 mux31(DataIn0[31], DataIn1[31], Sel, DataOut[31]); endmodule
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m ux 2to1:m ux 31 DataIn0[31..0] DataIn1[31..0] Sel

m ux 2to1:m ux 30
m ux 2to1:m ux 29
m ux 2to1:m ux 28
m ux 2to1:m ux 27
m ux 2to1:m ux 26
m ux 2to1:m ux 25
m ux 2to1:m ux 24
m ux 2to1:m ux 23
m ux 2to1:m ux 22
m ux 2to1:m ux 21
m ux 2to1:m ux 20
m ux 2to1:m ux 19
m ux 2to1:m ux 18
m ux 2to1:m ux 17
m ux 2to1:m ux 16
m ux 2to1:m ux 15
DataOut[31..0]
m ux 2to1:m ux 14
m ux 2to1:m ux 13
m ux 2to1:m ux 12
m ux 2to1:m ux 11
m ux 2to1:m ux 10
m ux 2to1:m ux 9
m ux 2to1:m ux 8
m ux 2to1:m ux 7
m ux 2to1:m ux 6
m ux 2to1:m ux 5
m ux 2to1:m ux 4
m ux 2to1:m ux 3
m ux 2to1:m ux 2
m ux 2to1:m ux 1
m ux 2to1:m ux 0
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Kt hp cc module li v s dng cc module c thit k trc l Control, Regfile, Alu, AluControl, Datamemory, Instruction. CODE: module MIPS(clk); input clk; wire ZeroFlag, OverflowFlag, CarryFlag, NegativeFlag; // PC and Instruction Memory wire [31:0] PC, PCin; wire [31:0] PC4; // PC4 = PC+4 wire [31:0] instruction; // Main Control wire ex_control,RegDst,Jump,Branch,MemRead,MemtoReg,MemWrite,ALUSrc,Re gWrite; wire jr_control; wire [1:0] ALUOp; // regfile wire [4:0] WriteRegister; wire [31:0] WriteData, ReadData1, ReadData2; // sign_extend wire [31:0] Sign_extend_Out; // ALU wire [31:0] ALU_In2; wire [1:0] ALUcontrol;
wire [31:0] ALUresult; // Data Memory wire [31:0] Data_Mem; // Branch wire [31:0] Branch_Address; wire Branch_Select;//quyet dinh co thuc hien lenh nhay wire [31:0] BranchAdd_In2; wire [31:0] muxBranchOut; wire [31:0] muxJumpOut; // Jump wire [31:0] JumpAddress; // 28-bit after shifting left 2 bits from 26-bit offset of jump instruction // InstructionMem InstructionMem InstructionMem1(instruction, PC); // Main Control Control Control1(instruction[31:26],ex_control,RegDst,Jump,Branch,MemRead,Mem toReg,ALUOp,MemWrite,ALUSrc,RegWrite); // Select WriteRegister mux2x5to5 mux2x5to5_wrireg_sel(instruction[20:16], instruction[15:11], RegDst, WriteRegister); // Regfile regfile regfile1(ReadData1,ReadData2,WriteData,instruction[25:21],instruction[20: 16],WriteRegister,RegWrite,clk);
// Sign-extend sign_extend SignExtendBlock(instruction[15:0],ex_control, Sign_extend_Out); // Select Bus B for ALU mux2x32to32 mux2x32to32_AluIn2_sel (ReadData2,Sign_extend_Out, ALUSrc, ALU_In2); // ALU control ALU_control ALU_control1(ALUcontrol,jr_control, ALUOp, instruction[5:0]); // ALU Block alu ALU1(ReadData1,ALU_In2,ALUcontrol,ALUresult,ZeroFlag,OverflowFlag, CarryFlag,NegativeFlag); // Data Memory datamem datamem1(Data_Mem,ALUresult,ReadData2,MemWrite,MemRead,clk);
// Select Data to WriteData for regfile mux2x32to32 mux2x32to32_wridata_sel(ALUresult,Data_Mem,MemtoReg,WriteData); // PC4 = PC + 4 add Add_PC4(PC,{29'b0,3'b100},PC4); // Branch shift_left2 shift_left_2_branch(Sign_extend_Out,BranchAdd_In2); add BranchAdd(PC4,BranchAdd_In2,Branch_Address); and #(50) Branch_Sel(Branch_Select, Branch, (~ZeroFlag));
mux2x32to32 muxBranch(PC4,Branch_Address,Branch_Select,muxBranchOut);
// Jump shift_left2 shift_left2_jump({6'b0,instruction[25:0]},JumpAddress);mux2x32to32 muxJump(muxBranchOut,{PC4[31:28],JumpAddress[27:0]},Jump,muxJump Out); //jump register mux2x32to32 muxJr(muxJumpOut,ReadData1,jr_control,PCin); // PC Block PC PC_Block1(PC,PCin); endmodule Kt qu m phng bng QUATUS:
Page 27
M phng bng Icarus: Module testbench: `timescale 1 ps / 100 fs `include "MIPS.v" module mipsstimulous(); wire [31:0] PCin,PC; reg clk; always #2100 begin clk = ~clk; end MIPS MIPS1(clk); initial begin
$dumpvars(-1, MIPS1); //dump all variables in module dut $dumpfile("single.vcd"); clk = 0; #1000000 $finish; end endmodule
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Bao Cao Lab 3

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N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

SVTH: CN _ BNH _ TUN

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

PC_bit PC_bit PC_bit PC_bit PC_bit PC_bit PC_bit endmodule

Buf25(PCout[25],PCin[25]); Buf26(PCout[26],PCin[26]); Buf27(PCout[27],PCin[27]); Buf28(PCout[28],PCin[28]); Buf29(PCout[29],PCin[29]); Buf30(PCout[30],PCin[30]); Buf31(PCout[31],PCin[31]);

SVTH: CN _ BNH _ TUN

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

SVTH: CN _ BNH _ TUN

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

add_bit:bit0 Add_In1[31..0] Add_In2[31..0]

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

+ ex_control =0: m rng 0, dng cho lnh XORI.

SVTH: CN _ BNH _ TUN

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

and16 In16[15..0] ex_control and15

and14 Out32[31..0] and13

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

op xxxxxx xxxxxx xxxxxx 100000 100110 100010 101010 001000

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

and2 ALUop[1..0] and_jr jr_control and4

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

SVTH: CN _ BNH _ TUN

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

Decoder0 Mem toReg~0 Opcode[31..26]

WideOr0 Mem Read$latch

SVTH: CN _ BNH _ TUN

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

mux2to1 SelAddress4(AddressIn0[4], AddressIn1[4], Sel, AddressOut[4]); endmodule

mux2to1:SelAddres s 4 Addres s In0[4..0] Addres s In1[4..0] Sel

N VI X L & CU TRC MY TNH

GVHD: TR N TH MINH HNH

SVTH: CN _ BNH _ TUN