Figure 7.6. Gated SR latch.

Figure 7.8. Gated D latch.

Master D Clock D Q Qm

Slave D Q Qs Q Q

Clk Q

Clk Q

(a) Circuit

Clock D Qm Q = Qs

(b) Timing diagram

Q Q

(c) Graphical symbol

Figure 7.10. Master-slave D flip-flop.

D Clock

Qa Qa

Clk Q

Q Q

Qb Qb

Q Q

Qc Qc

(a) Circuit
Clock D Qa Qb Qc

(b) Timing diagram

Figure 7.12. Comparison of level-sensitive and edge-triggered D storage elements.

Figure 7.14. Positive-edge-triggered D flip-flop with Clear and Preset.

D T

Q Q

Q Q

Clock

(a) Circuit

T 0 1

Q( t + 1 ) Q( t ) Q( t )

Q Q

(b) Truth table

(c) Graphical symbol

Clock T Q

(d) Timing diagram

Figure 7.16. T flip-flop.

Enable

Q Q

Q0

Q Q

Q1

Q Q

Q2

Q Q

Q3

Clock

Output carry

Figure 7.24. A four-bit counter with D flip-flops.

Enable D0

0 1

Q Q

Q0

D1

Q Q

Q1

D2

Q Q

Q2

D3

Q Q

Q3

Output carry Load Clock

Figure 7.25. A counter with parallel-load capability.

Figure 7.29. Ring counter.

Figure 7.33. Implementation of the schematic in Figure 7.31 in a CPLD.

Figure 7.76. A reaction-timer circuit.

Figure 7.86. Circuit for Example 7.16.