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  • 9D06106c Low Power VLSI Design PDF

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    Vijay Kshatriya HR
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    The document contains questions from an exam on low power VLSI design. It asks students to explain comparisons between CMOS, bipolar and BICMOS technologies, threshold voltage limitations in low power designs, advantages of BICMOS technology and its classifications. Other questions address limitations of deep submicron technology, SOICMOS and lateral BJT on SOI, the Philips MOS 9 model and power dissipation in CMOS. It also asks students to draw and explain conventional CMOS logic gates, define ESD and draw an ESD free BICMOS digital circuit, discuss the need for low power latches and flip flops, quality measures, clocking networks used in IC technology, and skew effects on clocked

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    The document contains questions from an exam on low power VLSI design. It asks students to explain comparisons between CMOS, bipolar and BICMOS technologies, threshold voltage limitations in low power designs, advantages of BICMOS technology and its classifications. Other questions address limitations of deep submicron technology, SOICMOS and lateral BJT on SOI, the Philips MOS 9 model and power dissipation in CMOS. It also asks students to draw and explain conventional CMOS logic gates, define ESD and draw an ESD free BICMOS digital circuit, discuss the need for low power latches and flip flops, quality measures, clocking networks used in IC technology, and skew effects on clocked

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    Download as PDF, TXT or read online from Scribd
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    68 views1 page

    9D06106c Low Power VLSI Design PDF

    Uploaded by

    Vijay Kshatriya HR
    The document contains questions from an exam on low power VLSI design. It asks students to explain comparisons between CMOS, bipolar and BICMOS technologies, threshold voltage limitations in low power designs, advantages of BICMOS technology and its classifications. Other questions address limitations of deep submicron technology, SOICMOS and lateral BJT on SOI, the Philips MOS 9 model and power dissipation in CMOS. It also asks students to draw and explain conventional CMOS logic gates, define ESD and draw an ESD free BICMOS digital circuit, discuss the need for low power latches and flip flops, quality measures, clocking networks used in IC technology, and skew effects on clocked

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    Code: 9D06106c M.Tech - I Semester Regular and Supplementary Examinations, April/May 2012 LOW POWER VLSI DESIGN (Common to DSCE and DECS) Time: 3 hours Max Marks: 60 Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) 2 (a) (b) 3 (a) (b) 4 5 (a) (b) 6 (a) (b) (c) Explain clearly a comparison of CMOS, bipolar and BICMOS technologies in terms of speed and power. Explain in detail the V T limitations (threshold voltage limitations) of low power designs. What are the main advantages of BICMOS technology? Mention the classification of BICMOS technology and explain clears about any one. Discuss about the limitations of DSM technology. Explain briefly about: (i) SOICMOS (ii) Lateral BJT on SOI.

    Explain about the Philips MOS 9 model of a MOSFET and its limitations. Write short notes on power dissipation in CMOS technology. Draw different conventional CMOS logic gates and explain about them.

    What is ESD? Draw the ESD free BICMOS digital circuit. Explain clearly about it and draw the performance graphs of ESD free circuit in terms of parameters. What is the need of low power latches and flip flops? Mention the 4 kinds of quality measures and explain them. Discuss about the clocking networks used in IC technology. What is skew? How does it effect the performance of clocked flip flop design? *****

    7 (a) (b) 8 (a) (b)

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