74VHC112 Dual J-K Flip-Flops with Preset and Clear

May 2007

74VHC112 Dual J-K Flip-Flops with Preset and Clear

Features
High speed: fMAX = 200MHz (Typ.) at VCC = 5.0V Low power dissipation: ICC = 2A (Max.) at TA = 25C High noise immunity: VNIH = VNIL = 28% VCC (Min.) Power down protection is provided on all inputs Pin and function compatible with 74HC112

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General Description
The VHC112 is an advanced high speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The LOW signal on PR or CLR prevents clocking and forces Q and Q HIGH, respectively. Simultaneous LOW signals on PR and CLR force both Q and Q HIGH. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.

Ordering Information
Order Number
74VHC112M 74VHC112SJ 74VHC112MTC

Package Number
M16A M16D MTC16

Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter X to the ordering number.

1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2

www.fairchildsemi.com

74VHC112 Dual J-K Flip-Flops with Preset and Clear

Connection Diagram

Truth Table
Inputs PR
L H L H H H H

Outputs J
X X X h l h l

CLR
H L L H H H H

CP
X X X

K
X X X h h l l

Q
H L H Q0 L H Q0

Q
L H H Q0 H L Q0

H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.

Pin Description
Pin Names
J1, J2, K1, K2 CLK1, CLK2 CLR1, CLR2 PR1, PR2 Q1, Q2, Q1, Q2

Description
Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active LOW) Direct Preset Inputs (Active LOW) Outputs

Logic Diagram
(One Half Shown)

1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2

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74VHC112 Dual J-K Flip-Flops with Preset and Clear

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol
VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC / GND Current Storage Temperature

Parameter

Rating
0.5V to +7.0V 0.5V to +7.0V 0.5V to VCC + 0.5V 20mA 20mA 25mA 50mA 65C to +150C 260C

Lead Temperature (Soldering, 10 seconds)

Recommended Operating Conditions(1)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol
VCC VIN VOUT TOPR tr , tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time, VCC = 3.3V 0.3V VCC = 5.0V 0.5V

Parameter

Rating
2.0V to +5.5V 0V to +5.5V 0V to VCC 40C to +85C 0ns/V 100ns/V 0ns/V 20ns/V

Note: 1. Unused inputs must be held HIGH or LOW. They may not float.

1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2

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74VHC112 Dual J-K Flip-Flops with Preset and Clear

DC Electrical Characteristics
TA = 25C Symbol
VIH VIL VOH

TA = 40C to +85C Max. Min.

1.50 0.7 x VCC 0.50 0.3 x VCC 0.50 0.3 x VCC 1.9 2.9 4.4 2.48 3.80 V V

Parameter
HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage

VCC (V)
2.0 3.05.5 2.0 3.05.5 2.0 3.0 4.5 3.0 4.5

Conditions

Min.
1.50 0.7 x VCC

Typ.

Max.

Units
V

VIN = VIH or VIL

IOH = 50A

1.9 2.9 4.4

2.0 3.0 4.5

IOH = 4mA IOH = 8mA VIN = VIH or VIL IOL = 50A

2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 2.0

VOL

LOW Level Output Voltage

2.0 3.0 4.5 3.0 4.5

0.1 0.1 0.1 0.44 0.44 1.0 20.0

IOL = 4mA IOL = 8mA VIN = 5.5V or GND VIN = VCC or GND

IIN ICC

Input Leakage Current Quiescent Supply Current

05.5 5.5

A A

1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2

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74VHC112 Dual J-K Flip-Flops with Preset and Clear

AC Electrical Characteristics
TA = 25C Symbol
fMAX

TA = 40C to +85C Min.

100 80 135 110 11.0 15.0 7.3 10.5 10.2 13.5 6.7 9.5 10 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 13.4 16.5 8.8 12.0 11.7 15.0 8.0 11.0 10 pF pF ns ns ns ns MHz

Parameter
Maximum Clock Frequency

VCC (V)
3.3 0.3 5.0 0.5

Conditions
CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF VCC (2) = Open

Min.
110 90 150 120

Typ.
150 120 200 185 8.5 10.0 5.1 6.3 6.7 9.7 4.6 6.4 4 18

Max.

Max. Units
MHz

tPLH, tPHL

Propagation Delay Time (CP to Qn or Qn)

3.3 0.3 5.0 0.5

tPLH, tPHL

Propagation Delay Time (PR or CLR to Qn or Qn)

3.3 0.3 5.0 0.5

CIN CPD

Input Capacitance Power Dissipation Capacitance

Note: 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD VCC fIN + ICC / 4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated by the following equation: CPD (total) = 30 + 14 n

AC Operating Requirements
TA = 25C Symbol
tW tS tH tREC

TA = 40C to +85C Guaranteed Minimum Units

ns ns ns ns 5.0 5.0 5.0 4.0 1.0 1.0 6.0 5.0

Parameter
Minimum Pulse Width (CP or CLR or PR) Minimum Setup Time (Jn or Kn to CPn) Minimum Hold Time (Jn or Kn to CPn) Minimum Recovery Time (CLR or PR to CP)

VCC

(V)(3)

Typ.

3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0

5.0 5.0 5.0 4.0 1.0 1.0 6.0 5.0

Note: 3. VCC is 3.3 0.3V or 5.0 0.5V.

1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2

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74VHC112 Dual J-K Flip-Flops with Preset and Clear

Physical Dimensions
Dimensions are in millimeters unless otherwise noted.

Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A

1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2

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74VHC112 Dual J-K Flip-Flops with Preset and Clear

Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted.

Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2

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74VHC112 Dual J-K Flip-Flops with Preset and Clear

Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted.

5.000.10 4.55 5.90 4.45 7.35

0.65

4.40.1

1.45

5.00 0.11

12

MTC16rev4

Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16

1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2

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74VHC112 Dual J-K Flip-Flops with Preset and Clear

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Rev. I26

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

No Identification Needed

Full Production

Obsolete

Not In Production

1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2

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