Circular Buffer & FIFO

Digital Circuits Design with HDL Course
CE Undergraduate 1st, 2010-2011
Circular Buffer & FIFO

Pham Quoc Cuong http://www.cse.hcmut.edu.vn
Circular Buffer
oldest sample newest sample
x[k]
N-samples
Moving window of N samples
Two options: (1) Shift the register contents concurrently at every clock (2) Shift the address pointer
Sample n
Sample n-N+1 Sample n-N Sample n-1 Sample n-2 Sample n-3
N-cells
9/12/2010
Pham Quoc Cuong 2
Data Movement
Data samples: 0110, 1010, 1111, ... Method #1: Shift Register
0110 1010 0110 1111 1010 0110 ...
Method #2: Address Managed

0110 0110 1010 0110 1010 1111 ...
9/12/2010
Pham Quoc Cuong 3
Circular Buffer#1: Shift Operation

module Circular_Buffer_1 (cell_3, cell_2, cell_1, cell_0, Data_in, clock, reset); parameter buff_size = 4; parameter word_size = 8; output [word_size -1: 0] cell_3, cell_2, cell_1, cell_0; input [word_size -1: 0] Data_in; input clock, reset; reg [word_size -1: 0] Buff_Array [buff_size -1: 0]; assign cell_3 = Buff_Array[3], cell_2 = Buff_Array[2]; assign cell_1 = Buff_Array[1], cell_0 = Buff_Array[0]; integer k; always @ (posedge clock) begin if (reset == 1) for (k = 0; k <= buff_size -1; k = k+1) Buff_Array[k] <= 0; else for (k = 1; k <= buff_size -1; k = k+1) begin Buff_Array[k] <= Buff_Array[k-1]; end Buff_Array[0] <= Data_in; end endmodule
Circular Buffer & FIFO 9/12/2010 Pham Quoc Cuong 4
Circular Buffer#2: Addess managed

module Circular_Buffer_2 (cell_3, cell_2, cell_1, cell_0, Data_in, clock, reset); parameter buff_size = 4, word_size = 8; output [word_size -1: 0] cell_3, cell_2, cell_1, cell_0; input [word_size -1: 0] Data_in; input clock, reset; reg [word_size -1: 0] Buff_Array [buff_size -1: 0]; assign cell_3 = Buff_Array[3], cell_2 = Buff_Array[2]; assign cell_1 = Buff_Array[1], cell_0 = Buff_Array[0]; integer k; parameter write_ptr_width = 2; // Width of write pointer parameter max_write_ptr = 3; reg [write_ptr_width -1 : 0] write_ptr; // Pointer for writing always @ (posedge clock) if (reset == 1 ) begin write_ptr <= 0; for (k = 0; k <= buff_size -1; k = k+1) Buff_Array[k] <= 0; end else begin Buff_Array[write_ptr] <= Data_in; if (write_ptr < max_write_ptr) write_ptr <= write_ptr + 1; else write_ptr <= 0; end endmodule
Simulation result
0 reset clock Data_in[7:0] cell_0_1[7:0] cell_1_1[7:0] cell_2_1[7:0] cell_3_1[7:0] xx 02 00 00 00 00 03 03 04 04 03 05 05 04 03 06 06 05 04 03 07 07 06 05 04 08 08 07 06 05 09 09 08 07 06 0a 0a 09 08 07 0b 0b 0a 09 08 0c 40 80 120
cell_0_2[7:0] cell_1_2[7:0] cell_2_2[7:0] cell_3_2[7:0]
00 00 00 00
03 04 05 06
07 08 09 0a
0b
write_ptr[1:0] x
9/12/2010
Pham Quoc Cuong 6
Synthesized Circuits (1)

Circular#1
Synthesized by Xilinx ISE 10.1

Synthesized Circuits (2)
Synthesized by Xilinx ISE 10.1

FIFO: Pointer Configuration

Cell 7 Cell 6 write_ptr Cell 7 Cell 6 Cell 7 Cell 6 Cell 5
Cell 5
Cell 4 Cell 3 Cell 2 Cell 1 write_ptr Cell 0 Empty FIFO read_ptr
Cell 5
Cell 4 Cell 3 Cell 2 Cell 1 Cell 0 read_ptr
Cell 4
Cell 3 Cell 2 Cell 1 Cell 0 write_ptr
After seven writes FIFO
Full FIFO
9/12/2010
Pham Quoc Cuong 9
Module declaration
module FIFO_Buffer (Data_out, stack_full, stack_almost_full, stack_half_full, stack_almost_empty, stack_empty, Data_in, write_to_stack, read_from_stack, clk, rst);
parameter stack_width = 32; parameter stack_height = 8; parameter stack_ptr_width = 3; parameter AE_level = 2; parameter AF_level = 6; parameter HF_level = 4; output [stack_width -1: 0] output output input [stack_width -1: 0] input input
// Width of stack and data paths // Height of stack (in # of words) // Width of pointer to address stack // almost empty level // Almost full level // Half full level Data_out; stack_full, stack_almost_full, stack_half_full; stack_almost_empty, stack_empty; Data_in; write_to_stack, read_from_stack; clk, rst;
9/12/2010 Pham Quoc Cuong 10
FIFO Signals
reg reg reg reg [ stack_ptr_width -1: 0] [ stack_ptr_width: 0] [stack_width -1: 0] [stack_width -1: 0] read_ptr, write_ptr; // Addresses for // reading and writing ptr_gap; // Gap between ptrs Data_out; stack [stack_height -1 : 0]; // memory array
// Stack status signals assign stack_full = (ptr_gap == stack_height); assign stack_almost_full = (ptr_gap == AF_level); assign stack_half_full = (ptr_gap == HF_level); assign stack_almost_empty = (ptr_gap == AE_level); assign stack_empty = (ptr_gap == 0);
9/12/2010
Pham Quoc Cuong 11
FIFO Datapath (1)

always @ (posedge clk or posedge rst) if (rst) begin Data_out <= 0; read_ptr <= 0; write_ptr <= 0; ptr_gap <= 0; end else if (write_to_stack && (!stack_full) && (!read_from_stack)) begin stack [write_ptr] <= Data_in; write_ptr <= write_ptr + 1; ptr_gap <= ptr_gap + 1; end else if ((!write_to_stack) && (!stack_empty) && read_from_stack) begin Data_out <= stack [read_ptr]; read_ptr <= read_ptr + 1; ptr_gap <= ptr_gap - 1; end To be continued
FIFO Datapath (2)

else if (write_to_stack && read_from_stack && stack_empty) begin stack [write_ptr] <= Data_in; write_ptr <= write_ptr + 1; ptr_gap <= ptr_gap + 1; end else if (write_to_stack && read_from_stack && stack_full) begin Data_out <= stack [read_ptr]; read_ptr <= read_ptr + 1; ptr_gap <= ptr_gap - 1; end else if (write_to_stack && read_from_stack && (!stack_full) && (!stack_empty)) begin Data_out <= stack [read_ptr]; stack [write_ptr] <= Data_in; read_ptr <= read_ptr + 1; write_ptr <= write_ptr + 1; end endmodule
Simulation Result
9/12/2010
Pham Quoc Cuong 14
Synthesized Circuit
9/12/2010
Pham Quoc Cuong 15

Circular Buffer &amp; FIFO

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Circular Buffer &amp; FIFO

Uploaded by

Copyright:

Available Formats

Digital Circuits Design with HDL Course

CE Undergraduate 1st, 2010-2011