I/O and Interrupts

There is more variety between CPUs in the way they handle Input and Output (I/O) than in any other type of instruction. I/O processin can be either! "emory#mapped The I/O re isters in the device controllers form part of re ular address space$ and are read and written usin normal %O&' and (TO)*#type instructions +on#memory#mapped (pecial instructions (e. . I+ OUT) are used to read and write I/O re isters In various combinations with the above there are four different I/O schemes in eneral use! Pro rammed I/O with busy waitin Interrupt#driven I/O '"& I/O I/O usin data Channels

Programmed I/O with Busy Waiting

Used in some low#end microcomputers (in le input and sin le output instruction *ach instructions selects one I/O device (by number) and transfers a sin le character (byte) *,ample! microprocessor# controlled video terminal -our re isters! input status and character$ output status and character

Programmed I/O with Busy Waiting

/henever a character arrives from the 0eyboard bit 1 of the 0eyboard status re ister is set by the hardware. Input routine loops until 2 is set /henever a character is to be displayed output routine loops until bit 1 of display status re ister is set to 2 by the hardware
def OutputBuffer (buffer, count): # # Output block of count bytes to the terminal screen # i = 0 while i <= count: # for each char: # wait until ready then output while (in (DisplayStatusReg) & 0x80) == 0: pass out (buffer[i]) i += 1

Interrupt-driven I/O

Primary disadvanta e of pro rammed I/O is that CPU spends most of its time in a ti ht loop waitin for the device to become ready. This is called busy waiting /ith interrupt-driven I/O$ the CPU starts the device and tells it to enerate an interrupt when it is finished 'one by settin interrupt-enable bit in status re ister (till re3uires an interrupt for every character read or written Interruptin a runnin process is an e,pensive business (re3uires savin context)

Direct Memory Access (DMA) I/O

)e3uires e,tra hardware ('"& controller chip) Chip contains (at least) four re isters$ all CPU (software) accessible "emory address to be read or written Count of bytes (or words) to read or write 'evice number or I/O address to use )ead/write indicator (direction)

(ystem with '"& controller

Direct Memory Access (DMA) I/O

To write bloc0 of 45 bytes from memory address 266 to device 7 2. CPU writes 45$ 266$ 7 into the first three '"& re isters (memory address$ count$ device number) 5. CPU puts code for /)IT* (say 2) into fourth (direction) '"& re ister$ which si nals '"& controller to be in operation 4. Controller reads (via bus re3uest as CPU would) byte 266 from memory 7. Controller ma0es I/O re3uest to write to device 7 8. Controller increments memory address re ister and decrements count re ister 9. Controller continues this loop until count decrements to 6 1. /hen count becomes 6 I/O is complete and controller asserts interrupt line on bus /ith '"& the CPU only has to start the I/O and respond to the final interrupt There is only one interrupt per block of bytes input or output (ome '"& controllers can do two or more simultaneous I/O operations '"& process is not free when controller wants to read/write via the bus it must ma0e the CPU wait ('"& controller always has hi her priority on bus). This process is called cycle stealing '"& I/O is used on PCs and minicomputers

I/O

sing Data !hanne"s

"ainframes do enormous amounts of I/O Overhead of cycle stealin would be intolerable (olution! use special purpose I/O processors called data channels 'ata channel is loaded with (or pointed at) a special pro ram and sent a start si nal by the CPU /hen channel has completed I/O it enerates an interrupt Channel has separate path to memory (memory is multi# ported) and therefore there is no re3uirement for cycle stealin Channel pro rams can be comple, and involve transferrin multiple bloc0s of data$ therefore fewer interrupts are enerated :enerally two types of channel (elector channels sin le transfer at a time$ very hi h speed throu hput (e. . lar e dis0 arrays) "ultiple,or channels multiple low#speed devices (e. . printers$ terminals) can be handled simultaneously

I/O usin data channels consists of 9 steps

I/O

sing Data !hanne"s

2. User pro ram re3uests O( to perform I/O on its behalf 5. O( builds channel program in its memory to perform the I/O 4. O( e,ecutes StartIO instruction! specifies channel and device number. (&fter this instruction the O( can carry on with other productive wor0) 7. Channel fetches address of channel pro ram 8. *ach channel has a dedicated main memory address which holds this pointer 9. Channel e,ecutes channel pro ram # this may consist of numerous instructions. 1. Channel instruction has an opcode (write$ read$ control$ sense$ jump$ etc.) address of main memory buffer for data$ miscellaneous bits and a byte count for the I/O ;. /hen I/O has completed$ channel asserts the interrupt line to notify the CPU

I/O# $wo %&amp"es

&bove is a typical '*C P'P#; mincomputer confi uration from the late 2<96s =elow an I=" 416 mainframe from the early 2<16s. +ote the dualported memory and data channels

:eneral principles for interrupt handlin are applicable to every method of I/O e,cept pro rammed with busy waitin It is important that interrupts are handled transparently$ i.e. pro rams which are interrupted by (another pro ram>s) I/O termination carry on after the interrupt as if nothin had happened There are two sides to interrupt handlin ! hardware and software ?ardware 2. 'evice controller asserts interrupt line on the bus 5. /hen the CPU is ready for interrupt (it cannot pause durin an instruction) it asserts interrupt acknowledge on the bus 4. /hen the device controller sees the ac0nowled ement$ it puts an interrupt number on the bus to identify itself 7. CPU removes the interrupt number from the bus and stores it in a temporary re ister 8. CPU pushes PC and PS onto stac0 in order to save return address to pro ram bein interrupted PC! pro ram counter (a0a Instruction Counter or # to Intel # Instruction Pointer P(/! (Pro ram (tatus /ord # essentially the fla s re ister$ althou h some manufacturers include the PC in the P(/) 9. CPU locates Interrupt Service !outine (IS!) by inde,in into Interrupt "ectors an array held at the bottom of main memory. This is done by multiplyin the interrupt number$ n$ by the si@e of a procedure pointer (i.e. address in main memory of an instruction) (oftware I() saves all re isters. (This is called savin the context of the interrupted pro ram) I() determines which device caused the interrupt. (This is usually done by readin a specific re ister in the device controller # dis0 controllers often have more than one dis0 attached$ for e,ample) I() handles any error which may have occurred I() updates pro ram#accessible information about the I/O which has Aust terminated (character count read$ for e,ample) If necessary I() asserts an interrupt handling completed si nal (the ;88<& chip used on PCs re3uires this) I() restores saved re isters I() e,ecutes !#$%!& '!O( I&$#!!%P$ instruction$ passin control bac0 to the interrupted pro ram

Interrupts and 'au"ts

(ested Interrupts

It is 3uite possible$ even li0ely$ that on a multi#user or multi# device machine an interrupt will occur while a previous interrupt is bein handled Two possible approaches Postpone servicin of new interrupt until old I() has finished &chieved by disablin interrupts for the duration of the I() &dvanta e! simpler code 'isadvanta e! some devices simply cannot be made to wait. & serial line runnin at <966bps will deliver a character every 2675 usec$ if the I() disables interrupts for lon er than this period$ then characters can be lost &llow I()>s to be interrupted$ but only by interrupts of a hi her priority &chieved by mas0in off interrupts of a lower priority than the current one$ and allowin for I()>s to be suspended$ i.e. have their conte,ts saved &dvanta e! no data loss 'isadvanta e! more comple, code In eneral (with the e,ception of low#end machines) the latter approach is ta0en

(ested Interrupts

2. 5. 4. 7. 8.

User pro ram runnin when printer interrupt (priority level 5) occurs User conte,t saved onto stac0$ printer I() runs )(545C interrupt (priority level 8) occurs Printer I() conte,t saved onto stac0$ )(545C I() runs 'is0 interrupt (priority level 7) occurs current I() priority hi her$ so interrupt held pendin 9. )(545C I() terminates$ printer I() resumes but dis0 interrupt is immediately allowed$ printer conte,t resaved$ and dis0 I() runs 1. 'is0 I() terminates$ allowin printer I() to resume ;. Printer I() terminates$ user pro ram resumes

'aults (or traps) are caused by a pro ram attemptin to do somethin which it either cannot or may not! the impossible or the illegal. *,amples! Impossible *,ecute somethin which is not an instruction (ille al opcode)$ divide by @ero$ reference non#e,istent memory Ille al *,ecute a privile ed instruction (I&$ O%$$ StartIO$ load alarm clock register)$ reference memory outside the pro ram>s limits (ome of these will be reco nised durin the decode sta e$ some in the operand fetch sta e$ some in the e,ecute sta e The cpu>s response is the same! each fault has a )ault number associated with it and this number is used to inde, into into the )ault vectors and transfer control to a )ault handing routine. Unli0e interrupts # which are outside the pro ram>s control and caused by other pro rams # faults are events which usually cause the pro ram to be terminated and thus the fault service routine will not$ unli0e the I()$ return control the the faultin pro ram One e,ception to this is instructions which use the faultin mechanism to re3uest services from the operatin system$ 0nown as system calls. These instructions ive controlled access to system functionality and will (with the e,ception of a pro ram termination function) always return control to the user pro ram$ unless the instruction has been used incorrectly It is perhaps unfortunate that some CPU manufacturers have combined the interrupt and fault vectors and called them all interrupts # includin $ in the case of Intel$ the system call instruction (I&$) itself. This # li0e Intel>s bi@arre use of se mentation in the ,;9 # has caused serious confusion of terminolo y.

'au"ts