Experiment 1

Object: Using Verilog HDL, verify the working of the following gates:i. ii. iii. iv. v. vi. vii. AND Gate OR Gate NOT Gate XOR Gate NAND Gate NOR Gate EX-NOR Gate
XILINX ISE 8.2i

Software Used: Theory:

Verilog Code :module a(input_1, input_2, and_out, or_out, not_out, nand_out, nor_out, xor_out, xnor_out); input input_1; input input_2; output and_out; output or_out; output not_out; output nand_out; output nor_out; output xor_out; output xnor_out; not(not_out,input_1); and(and_out,input_1,input_2); or(or_out,input_1,input_2); nand(nand_out,input_1,input_2); xor(xor_out,input_1,input_2); nor(nor_out,input_1,input_2); xnor(xnor_out,input_1,input_2); endmodule

RTL Schematic:-

Simulation Waveforms:-

Conclusion: All the gates were designed using Verilog HDL and verified using ISE Simulator.