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  • Ramniwas 4 Bit Parity Generator&checkor

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    Subhash Chandra Sahu
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    The document describes an experiment to verify the operation of a 4-bit parity generator and checker circuit. The circuit uses IC 7486 and IC 7404 to generate even and odd parity bits based on the input bits and check the output parity to detect errors. The experiment used truth tables and K-maps to design the circuit and successfully tested the generation and checking of parity bits.

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    The document describes an experiment to verify the operation of a 4-bit parity generator and checker circuit. The circuit uses IC 7486 and IC 7404 to generate even and odd parity bits based on the input bits and check the output parity to detect errors. The experiment used truth tables and K-maps to design the circuit and successfully tested the generation and checking of parity bits.

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    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
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    6 views4 pages

    Ramniwas 4 Bit Parity Generator&checkor

    Uploaded by

    Subhash Chandra Sahu
    The document describes an experiment to verify the operation of a 4-bit parity generator and checker circuit. The circuit uses IC 7486 and IC 7404 to generate even and odd parity bits based on the input bits and check the output parity to detect errors. The experiment used truth tables and K-maps to design the circuit and successfully tested the generation and checking of parity bits.

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    Download as DOCX, PDF, TXT or read online from Scribd
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    of 4

    EXPERIMENT NO :-5 Ramniwas 2012uec1459 1. Aim:To verify the operation of full 4 bit parity generator and checker.

    Date:-21/10/2013 Batch:-EC-3

    2. Boolean Experation:Input parity bit

    Output parity bit

    3. Circuit Diagram:-

    To generate input parity

    To check output parity

    4. Truth Table:-

    5. K Map:For input ODD parity bit

    For input EVEN parity bit

    6. IC used:IC 7486

    IC 7404

    7. Result :performed the operation of 4 bit parity generator and checker using truth table.

    8. Conclusion:In a digital data transfer system to detect error a parity bit is employed using parity generator. Parity generator generate even and odd parity bit. Even parity bit makes no of ones even and odd parity bit makes no of ones odd. Input odd parity bit is compliment of input even parity bit. If output parity is 0 than there is no error otherwise error is present.

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