EXPERIMENT NUMBER:-5

Subhash Chandra 2012uec1507 Date:-21/10/2013 Batch:-EC-3

1. Aim:To study the operation and tables of 4 bit parity generator and checker.

2. Equipment Required: Digital trainer kit wires IC used:- IC 7486 ,IC 7404

3. Boolean Expression:Input parity bit Output parity bit

4. Circuit Diagram:To generate input parity

To check output parity

5. Truth Table:-

6. K Map:For input odd parity bit

For input EVEN parity bit

7. Result:The circuits for the design of four bit parity generator and checker were simplified using K-MAP and then verified experimentally. When the number of high input are Odd than the parity generated is Even .and vice versa

8. Conclusion:In a digital data transfer system to detect error a parity bit is employed using parity generator. Parity generator generate even and odd parity bit. Even parity bit makes no of ones even and odd parity bit makes no of ones odd. Input odd parity bit is compliment of input even parity bit. If output parity is 0 than there is no error otherwise error is present.