XXXII NATIONAL SYSTEMS CONFERENCE, NSC 2008, December 17-19, 2008

STATIC SYNCHRONOUS SERIES COMPENSATOR USING A 3-LEVEL INVERTER TO IMPROVE TORSIONAL DAMPING
C. D.Kotwal, Dr. G.N.Pillai and Dr. H.O.Gupta, senior member, IEEE

Abstract-- This paper investigates the possibility of using the diode clamped three level multi level inverter (MLI) to build static synchronous series compensator (SSSC).This SSSC is embedded in IEEE FBM model for SSR studies in place of series capacitor. The IEEE FBM with above SSSC model is designed and nonlinear simulation is carried out with the help of PSCAD. The PI (Proportional Integral) controller is used to balance the voltage across dc link capacitors. Using the phase angle controller the torsional damping control is achieved. The nonlinear simulation of the compensated system shows that the proper parameters of controller improve the torsional performance of the compensated system. By using suitable values of PI controller parameters a balance is achieved in voltage across dc link capacitors.

Index TermsMulti level inverter, PI Controller, Sub synchronous resonance, Static synchronous series compensator, IEEE First benchmark model for Sub synchronous resonance, Torsional interaction

I. INTRODUCTION

N recent years, FACTS devices have received wide spread interest for high voltage power systems control. Compared with mechanically switched control of the transmission system, power electronics-based FACTS devices are faster and more flexible [1].Series capacitor as a series compensation has been widely used to enhance the power transfer capability. However series capacitor compensation gives rise to dynamic instability and Subsynchronous resonance (SSR).Many preventive measures to cope with this problem is reported in literature [2].Among these the application of static var system has gained in recent years. The SSSC is a series FACTS device that produces, with appropriate control system, a balanced set of three-phase controllable voltages which are in quadrature with the transmission line current. The SSSC has two mode of operation. If SSSC voltage is function of the transmission line current the SSSC operates in constant reactance mode and when the SSSC voltage is independent of the line current, the SSSC operates in constant quadrature voltage mode [3].
C. D.Kotwal is a Research Scholar in Electrical Engineering, Indian Institute of Roorkee, India(email: apc67dee@iitr.ernet.in) G.N.Pillai is with the Department of Electrical Engineering, Indian Institute of Roorkee, India H.O.Gupta is with the Department of Electrical Engineering, Indian Institute of Roorkee, India

Considerable research has been done on SSSC with a 2level VSI [4]. In a high voltage application however, a 2-level VSI will increase the cost of the SSSC due to the high voltage rating requirement for the switches. Serial connection of the switches in the 2-level VSI can solve this problem. Effective use of this structure, however, requires a simultaneous switching technique. Multilevel power conversion has been receiving increasing attention in the past few years for high power applications [5]. In this paper an SSSC composed of three-level multilevel inverter is proposed. The results for the simulation of FBM model with SSSC for 0.6 pu power transfer is obtained. With diode clamped multi level inverter, the main problem is that of the voltage balancing across the dc link capacitors. In general for m levels, m-1 will be the number of capacitors required to get the desired output level. In [6] a PI controller based Voltage balance controller is discussed for statcom application. In remaining part the paper is organized as follows. In Part II sub synchronous resonance is discussed, in part III types of multi level Inverters are discussed ,in part IV, a design of phase angle controller is given, in part V, a PI Controller based voltage balancing across dc link capacitor described, finally the time domain analysis of the system with the help of PSCAD- EMTDC is covered. II. SUB SYNCHRONOS RESONANCE SSR is a resonant condition with frequency below the fundamental frequency, which is related to an energy exchange between the electrical and mechanical system, coupled through the generator. SSR can be divided in two main parts [7].steady state SSR (induction generator effect (IGE), and torsional interaction (TI) and transient torque or amplification (TA). SSR due to TI and TA are dangerous conditions that can lead to shaft damage [8] and therefore must be avoided. In [9] authors have discussed about torsional interaction studies on a power system compensated by SSSC and series capacitor. In this paper a 48 pulse SSSC model is used. The IEEE FBM for SSR studies with capacitor as series compensating device [10] is shown in Fig 1a. In this model a series capacitor as a compensating device is used, the system is a single machine infinite bus system. Fig.1b a voltage source inverter (VSI) based SSSC is shown. This VSI is a three level diode clamped multi level voltage source inverter. The turbine generator is a six mass model which consists of

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LPA, LPB, HP, and IP four parts of turbine, generator and exciter.

Fig.1 (a) IEEE FBM for SSR studies with fixed capacitor
I lo a d

L in e

V pq

I n s e r t io n T r a n s fo r m e r T e r m in a l

V o lta g e s o u rc e In v e r t e r V dc

Fig. 2a Three level multi level inverter (MLI)

Fig.1 (b) VSI based SSSC inserted in place of series capacitor of model shown in Fig. 1(a)

III MULTI LEVEL INVERTERS The multilevel voltage source inverters unique structure allows them to reach high voltages with low harmonics without the use of transformers or series connected synchronized switching devices, a benefit that many contributors have been trying to appropriate for high voltage, high power applications. There are roughly three main types of transform less multilevel inverter topologies, which have been studied and received considerable interest from high power inverter system manufacturers: the flying capacitor inverter, the diode clamped inverter and the cascaded H-bridge inverter. The voltage between two switches is clamped through the diodes in the middle of the structure, called clamping diodes. In Fig. 2a a diode clamped three level inverter is shown. It consists of four GTOs along with antiparallel diodes. Diode D1 and D2 are clamping the voltage between two switches.C1 and C2 are dc link capacitors.C1=C2 .The output voltage with suitable switching logic is as shown in Fig. 2b.As shown the voltage is varying its level between +Vdc,0 and -Vdc. The main advantage is its simple switching logic. With higher number of levels, harmonics in the output voltage is low and can be filtered easily. The problem of this topology is the balancing of the capacitors in the dc-link, and as levels increases the number of diodes increases.

Fig. 2b Three level MLI output waveform

IV DESIGN OF PHASE ANGLE CONTROLLER As can be seen from block diagram shown in Fig.3 the main function of the power controller is to respond to any change in the power demand and to adjust the actual power transmitted through the line such as to make these two variables equal at any moment in time. A compensating voltage with certain amplitude and in quadrature with line current is to be injected by SSSC at the point of connection. The magnitude of the injected voltage is controlled by the power controller in closed loop until the power request is met. The power flow desired is per unitized and it is taken as reference value of power flow. The actual power flow is compared with reference or desired power and it is fed to PI controller. Output of this PI controller is modulation index or magnitude of injected voltage. Fig.3 illustrates the phase angle controller used for generating a voltage signal in quadrature with the line current of one phase. The controller calculates the line current angle () with reference to the receiving-end voltage (VR) considered as the reference phasor (=0).The phase angle of the generated signal is -90 or +90o for capacitive or inductive mode respectively.

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A phase shift of 30o is added to compensate for stardelta connection of transformer. The angle obtained from capacitor voltage controller is added or subtracted from depending on whether the capacitor voltages are above or below the normalized levels.

This deviation from 90(d) is calculated from the outputs of four PI controllers. One error signal passing through the first controller is the difference between the average of the dc voltages normalized for each level and a Vdcref of 1 pu. The output of the other two controllers is proportional to the difference between the average dc voltage in pu on all the dc sources, and each individual. Capacitor voltage is measured and normalized to its reference value, producing some small angle d VI PSCAD SIMULATION OF SYSTEM A nonlinear simulation of the IEEE FBM for SSR studies with three level VSI is carried out for torsional interaction. Control logic for the switching of GTO is designed for the above system. A digital logic gate based GTO firing circuit gives a three level in terms of one level each on positive and negative cycle side and one zero level of voltage output of one phase. For line voltage it gives a five level output. The PI controller parameters for voltage balance controller of dc link capacitor are set as given below for the 0.6 pu real power flow. For improvement in torsional damping by using trial and error method the following set of PI controller parameters are obtained. The PI controller parameters for total dc voltage control Kpi=0.8, Ti=125; For voltage control across capacitor C1 Kp1=0.12, Ti1=13.33; For voltage control across capacitor C2 Kp2=1, Ti2=111.11; C1=C2=3000 mfd. For turbine generator mass, it consists of six mass systems. Turbine with four masses (LPA, LPB, HP and IP), the generator and exciter. The mutual damping between these masses is taken as zero. After performing the time domain simulation of nonlinear system the results obtained are shown in terms of Fig.5a, Fig. 5b and Fig. 6a to Fig 6d.
SSSC Voltage per phase in per unit 0.2

Fig.3 Phase angle controller

The frequency is held constant at 60 Hz. magnitude of the output voltage is controlled by the modulation index through the PI controller depending upon the desired level of compensation. V DESIGN OF CAPACITOR VOLTAGE BALANCE CONTROLLER Basically, the charge and therefore the voltage across each capacitor is maintained by prolonging or shortening the duration of the current flowing through it. For this a PI controller based voltage balance controller is designed. More charging of the capacitor can raise its falling voltage when the inverter is producing leading var or absorbing lagging vars. Also, a discharge of the capacitors is necessary when the dc source voltages are jumping up while trying to support a var request (in case a fault occurring in the line during the capacitive compensation mode). This can be done by deviating from the phase quadrature of the compensating voltage with respect to the line current with a small angle; a few degrees can cause a small real power exchange between the SSSC and the system for charging or discharging the dc side capacitors.
VC1/Vdc

+ 1/2
VCavg

S S S C ins erted v oltage in pu

VC2/Vdc
0.1 0

Vdcref

-0.1

+ +

VCavg

Kpi+1/STi Kp1+1/STi1

-0.2 3

3.005

3.01 3.015 t in seconds

3.02

3.025

VC1/Vdc

VCavg

(a)

(b)

Fig. 5(a) Three level VSI SSSC output voltage, (b) Harmonic spectrum of injected voltage of SSSC

VC2/Vdc

Kp2+1/STi2

Fig.4 DC link capacitors voltage balance controller

In Fig.5 (a) the output voltage or injected voltage of SSSC in the system is shown. The line to line voltage shows that it is five level output and phase voltage is three level. The wave shape of the output voltage of SSSC is quite satisfactory. 382

In Fig 5(b) the harmonic spectrum of injected voltage by SSSC is shown. From the harmonic spectrum we can see that the even harmonics are missing in the output waveform Due to perfectly balanced voltage across the dc link capacitors only odd harmonics are appearing .The minimum harmonic is fifth harmonic with three level inverter. A three phase fault is created for three cycle period. After fault also the system does not lose its stability. A fault is created after 2.5 seconds for three cycles of period.
DC Voltage across Capacitors in pu D C v o lt a g e a c ro s s c a p a c it o rs in p u 1 0.5 0 -0.5
0.8 0.6 Real P ower in p u Real Power in Per unit

minimum harmonic order can be increased by using higher no. of voltage levels of MLI and using some harmonic reduction technique. The problem of voltage balance across dc link capacitors can be dealt with development of suitable controller with optimization technique. VIII REFERENCES
[1] Ying Cheng, Mariesa Crow A diode clamped Multi-level Inverter for the statcom/BSES Power engineering society winter meeting 2002, IEEE Vol.1, pp 470-475 [2] S.K.Gupta, Narendra kumar et.al. Damping Subsynchronous Resonance in power system, IEE Proceedings on Gener. Trans. Distrib. Vol.149, No.6, pp 679-688 [3] Fawzi Al-Jowder Influence of Mode of Operation of the SSSC on the Small Disturbance and Transient Stability of a Radial Power System, IEEE transaction on Power System, Vol.20, No.2,pp 935-942, May 2005 [4] N. G. Hingorani and L. Gyugyi, Understanding FACTS, New York: IEEE Press, 2000 [5] R. W. Menzis and Yiping Zhuang, Advanced static compensation using a multilevel GTO thyristor inverter, IEEE Transactions on Power Delivery. Vol. IO, No.2, pp April 1995. [6] Rajiv Verma, R.N.Mathur, Thyristors based FACTS controllers for transmission line Wiley 2002 [7] P.Anderson, B Agrawal, and J.V. Ness, Subsynchronous resonance in power systems IEEE press, 1989 [8] K.Padiyar, Analysis of Subsynchronous resonance in power systems Kluwer academic publishers, 1999 [9] G.N, Pillai, A. Ghosh, A. Joshi, Torsional interaction studies on a power system compensated by SSSC and fixed capacitor IEEE, transactions on power delivery, Vol. 18, No. 3 pp.988-993, 2003. [10] IEEE SSR Task Force, First Benchmark Model for Computer Simulation of Subsynchronous Resonance, IEEE Trans. Power App, & System. Vol. PAS-96, No. 5, pp. 1565-1571, 1977 Chetan Kotwal received his M.E. degree from M.S.University of Baroda, Baroda, India in 1997.From 1999 he has been a faculty member of Electrical Engineering in Sardar Vallabhbhai Patel Institute of Technology, Vasad, Gujarat, India. Currently he is working toward his PhD in IIT Roorkee, India. His areas of interests are in Power Electronics applications to Power System, FACTS controllers and Power System Dynamics. G. N. Pillai is working as an Assistant professor in the Electrical Engineering Department of Indian Institute of Technology Roorkee, India. He received his Ph.D. degree from Indian Institute of Technology, Kanpur in the year 2001.He worked as research officer at the University of Ulster, Newtownabbey U.K. and he has published many papers in reputed international journals/conferences. His main research interest is in the area of power system operation and control. H. O. Gupta obtained his B.E. in Electrical Engineering from Government Engineering College, Jabalpur. He received ME in system Engineering and operation Research, and Ph.D from University of Roorkee, Roorkee, in 1975 and 1980 respectively. He visited McMaster University, Hamilton, Canada, from 1981 to 1983 as a post doctorate fellow. At present he is working as a Professor in the Department of Electrical Engineering, IITR. His research interests are in the area of computer-aided design, control systems, reliability engineering, power transformers and power network optimization.

0.4 0.2

4 6 t in seconds

10

4 6 t in seconds

10

(a)
Gen-Exc Torque in per unit 0.2

(b)
LPB-Gen Torque in per unit 3

G en-E x c Torque in pu

0.1 0 -0.1 -0.2

LPB-Gen torque in pu

2 1 0 -1 4 6 t in seconds 8 10

6 7 t in seconds

10

(c) (d) Fig. 6(a) DC link voltage across capacitors,(b) Real power in per unit, (c) Gen-Exc torque in per unit, (d )LPB-Gen torque in per unit

In Fig.6 (a) the voltage across two capacitors in per unit is shown. From the figure we can see that by using voltage balance controller the voltage across two capacitors are exactly balanced. In Fig. 6(b) the real power flow in per unit is shown. The value of real power flow is 0.6 pu. After fault the system does not loses stability and it continues to deliver the desired power at o.6 pu level. In Fig. 6(c) the torque between generator and exciter mass in per unit is shown. After applying fault the system does not lose its stability, it remains stable. The generator-exciter torque shows that after some time the system will attains its stable mode. In Fig.6 (d) the torque between LPB turbine and generator mass in per unit is shown. After applying fault the system does not lose its stability, it remains stable. The LPB-generator torque shows that after some time the system will attains its stable mode. VII CONCLUSION

In this paper the working of a three level fundamental switching frequency GTO based SSSC has been presented. The IEEE FBM for SSR studies is modeled with three level diode clamped multi level inverter based SSSC. A phase angle controller is designed for real power flow control. The voltage balance controller, for obtaining the voltage balance across dc link capacitors is developed. The result of the time domain analysis with the use of PSCAD-EMTDC shows that with balanced voltage across dc link capacitors improves a torsional damping. The minimum harmonic in the SSSC inserted voltage is fifth harmonic for three level inverter. The

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