Advanced VLSI Design

CMOS Basics

CMPE 640

MOS: Metal Oxide Semiconductor Transistors are built on a Silicon (semiconductor) substrate. Pure silicon has no free carriers and conducts poorly. Dopants are added to increase conductivity: extra electrons (n-type) or extra holes (p-type) MOS structure created by superimposing several layers of conducting, insulating and transistor-forming materials. Metal gate has been replaced by polysilicon or poly in modern technologies. There are two types of MOS transistors: nMOS pMOS : Negatively doped silicon, rich in electrons. : Positively doped silicon, rich in holes.

CMOS: Both type of transistors are used to construct any gate.

Advanced VLSI Design

CMOS Basics

CMPE 640

nMOS and pMOS Four terminal devices: Source, Gate, Drain, body (substrate, bulk).

Source

Gate

Drain Polysilicon SiO2

Source

Gate L

W Drain

Thin Oxide nMOS

n+ p

n+ bulk Si

n+

p substrate

n+

Source Polysilicon SiO2

Gate

Drain

pMOS
p+ n p+ bulk Si

Advanced VLSI Design

CMOS Basics

CMPE 640

CMOS Inverter Cross-Section Cadence Layer's for AMI 0.6mm technology

p-substrate contact (cc)

m1-m2 contact (via)

metal2

n-diffusion contact (cc) (Out) (source) glass(insulator) GND

p-diffusion contact (cc) (source) metal1 n-substrate contact (cc) VDD layer #3 layer #2

(pactive) (nactive)

p+

n+

n+ (drains)

p+

p+

n+

layer #1

n-well (nwell)

p substrate (black background) n-transistor polysilicon gate (poly ) p-transistor

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Advanced VLSI Design

CMOS Basics

CMPE 640

CMOS Cadence Layout Cadence Layout for the inverter on previous slide

Advanced VLSI Design

CMOS Basics

CMPE 640

MOS Transistor Switches We can treat MOS transistors as simple on-off switches with a source (S), gate (G) (controls the state of the switch) and drain (D). 1 represents high voltage, VDD (5V, 3.3V, 1.8V, 1.2V, <=1.0V today, .....) 0 represent low voltage - GND or VSS. (0V for digital circuits)

g=0 d nMOS g s d pMOS g s s s d ON d OFF

g=1 d ON s d OFF s

Advanced VLSI Design

CMOS Basics

CMPE 640

Signal Strengths Signals such as 1 and 0 have strengths, measures ability to sink or source current VDD and GND Rails are the strongest 1 and 0 Under the switch abstraction, G has complete control and S and D have no effect. In reality, the gate can turn the switch on only if a potential difference of at least Vt exists between the G and S. We will look at Vt in detail later on in the course. Thus signal strengths are related to Vt and therefore p and n transistors produce signals with different strengths Strong 1: VDD, Strong 0: GND, Weak 1 :(~VDD -Vt) and Weak 0 :(~GND + Vt). G 1 S D

nMOS 1

1
S

G 0 D

pMOS

0 1
*** Strong 1***
6

0
*** Strong 0***

0
Weak 0

Weak 1

Advanced VLSI Design

CMOS Basics

CMPE 640

CMOS Inverter

Vdd P1 A N1
CMOS Inverter

Out

A 0 1

O 1 0

THE CONFIGURATION BELOW FOR A BUFFER IS NOT A GOOD IDEA. WHY?

A P1 Out N1

Vdd

BAD IDEA

Advanced VLSI Design

CMOS Basics

CMPE 640

NAND and NOR CMOS Gates

Vdd A P1 N2 N1 P2 B Out
A B C

A 0 0 1 1

B 0 1 0 1

C 1 1 1 0

Vdd A P1 P2 N1 N2
1 1 0
A B

A
C

B 0 1 0

C 1 0 0

B Out

0 0 1

Advanced VLSI Design

CMOS Basics

CMPE 640

Pass Transistor The off-state of a transistor creates a high impedance condition Z at the drain. No current flows from source to drain. So transistors can be used as switches.

g s d s

g=0 d g=1 s d g=0 s d g=1 s d d

Input g = 1 Output 0 strong 0 g=1 1 Input 0 g=0 g=0 degraded 1 Output degraded 0 strong 1

g s

However, as we previously discussed this will produce degraded outputs, if only one transistor is used as a switch.
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Advanced VLSI Design

CMOS Basics

CMPE 640

Transmission Gates

In

A P1 N1 A

One pMOS and one nMOS in parallel. Note that neither transistor is connected to VDD or GND.

Out

A and A control the transmission of a signal on In to Out. Transmission gates act as tristate buffers.

Input g a gb g a gb b a gb g b a gb b g = 0, gb = 1 a b g = 1, gb = 0 a b

Output

g = 1, gb = 0 0 strong 0 g = 1, gb = 0 strong 1 1

g b

10

Advanced VLSI Design

CMOS Basics

CMPE 640

Transmission Gate Application: Select Mux Transmission Gate

Select A In Out Select B VDD Select Out

2-to-1 MUX

Select

Truth Table for 2-to-1 MUX

Select 0 1 Out B A

Out = A.S + B.S How many transistors are required to implement this using CMOS gates?
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Advanced VLSI Design

CMOS Basics

CMPE 640

D Latch Positive level-sensitive latch

CLK D Latch Q

CLK D Q

CLK D 1 0 CLK
If CLK is unavailable one extra inverter needed to generate it using CLK

Q Q D

CLK

Q Q CLK

CLK
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Advanced VLSI Design

CMOS Basics

CMPE 640

D Flip-Flop Positive edge-triggered flip-flop a.k.a master-slave flip-flop

CLK

CLK
D

Flop

Q
Q

CLK CLK D CLK Latch QM Latch CLK CLK Master Q CLK QM

CLK Q CLK CLK Slave

Master

Slave

CLK

If CLK is unavailable one extra inverter needed to generate it using CLK

13

Advanced VLSI Design

CMOS Basics

CMPE 640

D Flip-Flop Operation
D QM Q

QM follows D, Q is latched
CLK = 0

QM

QM transferred to Q, QM latched
CLK = 1

CLK

Positive edge-triggered flip-flop

D Q

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Advanced VLSI Design

CMOS Basics

CMPE 640

More CMOS Gates

Vdd B P1 Vdd A P2 N2 Out

N1

15

Advanced VLSI Design

CMOS Basics

CMPE 640

And More CMOS Gates

A B

Out

16

Advanced VLSI Design

CMOS Basics

CMPE 640

And More CMOS Gates

Vdd P2 P1 P3 P4 OAI A B C D N1 N2 N3 N4

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