CAJan2014 4s

Bi ging Kin trc my tnh Jan2014
Nguyn Kim Khnh DCE-HUST 1

TR!"NG #$I H%C BCH KHOA H N&I
Hanoi University of Science and Technology
KI!N TRC MY TNH
Computer Architecture
Nguy!n Kim Khnh
B mn K thut my tnh
Vin Cng ngh thng tin v Truyn thng
Department of Computer Engineering (DCE)
School of Information and Communication Technology (SoICT)

Version: Jan 2014

NKK-HUST
Contact Information
! Address: 502-B1
! Mobile: 091-358-5533
! e-mail: khanhnk@soict.hust.edu.vn
khanh.nguyenkim@hust.edu.vn
Jan2014 Computer Architecture 2
NKK-HUST
Muc tiu hoc phn
! Sinh vin duoc trang bj cc kin thc co s v
kin trc tp lnh v t chc ca my tnh, cng
nhu nhng vn d co bn trong thit k my
tnh.
! Sau khi hoc xong hoc phn ny, sinh vin c
kh nng:
! Tm hiu kin trc tp lnh ca cc b x l cu th
! Lp trnh hop ng trn mt s kin trc
! nh gi hiu nng ca cc ho my tnh
! Khai thc v qun trj hiu qu cc h thng my tnh
! Phn tch v thit k my tnh
NKK-HUST
Ti liu tham kho chnh
[1] William Stallings - Computer Organization and
Architecture Designing for Performance 2013 (9
th

edition)

[2] David A. Patterson & John L. Hennessy - Computer
Organization and Design: The Hardware/Software Interface
2012 (revised 4
th
edition)

[3] David Money Harris and Sarah L. Harris, Digital
Design and Computer Architecture, 2007

[4] Andrew S. Tanenbaum - Structured Computer
Organization 2012 (6
th
edition)
NKK-HUST
Ni dung hoc phn
Chuong 1. Gii thiu chung
Chuong 2. Co bn v logic s
Chuong 3. H thng my tnh
Chuong 4. S hoc my tnh
Chuong 5. Kin trc tp lnh
Chuong 6. B x l
Chuong 7. B nh my tnh
Chuong 8. H thng vo-ra
Chuong 9. Cc kin trc song song

NKK-HUST
Ch : Bi ging mi nht Jan 2014

ftp://dce.hust.edu.vn/khanhnk/CA

NKK-HUST
Kin trc my tnh
Ch!"ng 1
GI#I THI$U CHUNG
Nguy!n Kim Khnh
Tr"#ng $%i h&c Bch khoa H N'i
NKK-HUST
1.1. My tnh v phn loai
1.2. Khi nim kin trc my tnh
1.3. Su tin ha ca my tnh
1.4. Hiu nng my tnh
Ni dung
NKK-HUST
! My tnh (Computer) l thit bj din t thuc
hin cc cng vic sau:
! Nhn thng tin vo,
! X l thng tin theo dy cc lnh duoc nh sn bn
trong,
! ua thng tin ra.
! Dy cc lnh nm trong b nh d yu cu
my tnh thuc hin cng vic cu th goi l
chuong trnh (program)
" My tnh hoat dng theo chuong trnh.
1.1. My tnh v phn loai my tnh
1. My tnh
NKK-HUST
My tnh ....

Cc
thi!t b" vo
(Input Devices)
B# nh$ chnh
(Main Memory)
Cc
thi!t b" ra
(Output
Devices)
B# x% l&
trung tm
(Central
Processing Unit)
NKK-HUST
! Phn loai truyn thng:
! My vi tnh (Microcomputers)
! My tnh nh (Minicomputers)
! My tnh ln (Mainframe Computers)
! Siu my tnh (Supercomputers)
2. Phn loai my tnh
NKK-HUST
! Thit bj di dng c nhn (Personal Mobile Devices):
! Smartphones, Tablet
! My tnh c nhn (Personal Computers)
! Desktop computers, Laptop computers
! My ch (Servers)
! Thuc cht l My phuc vu
! Dng trong mang theo m hnh Client/Server
! My tnh cum/my tnh qui m ln (Clusters/Warehouse
Scale Computers):
! S dung tai cc trung tm tnh ton, trung tm d liu
! Supercomputers
! My tnh nhng (Embedded Computers)
! t n trong thit bj khc
! uoc thit k chuyn dung
Phn loai my tnh hin dai [P&H]
NKK-HUST
1.2. Khi nim kin trc my tnh
! jnh ngha truc dy v kin trc my
tnh:
! L thit k kin trc tp lnh (Instruction Set
Architecture ISA)
! Cc thuc tnh ca my tnh theo cch nhn
ngui lp trnh (hardware/software interface)
! L djnh ngha hep

NKK-HUST
jnh ngha ca Hennessy/ Patterson
! Kin trc my tnh bao gm:
! Kin trc tp lnh (Instruction Set Architecture):
nghin cu my tnh theo cch nhn ca ngui lp
trnh (hardware/software interface).
! T chc my tnh (Computer Organization) hay Vi
kin trc (Microarchitecture): nghin cu thit k my
tnh mc cao, chng han nhu h thng nh, cu
trc bus, thit k bn trong CPU.
! Phn cng (Hardware): nghin cu thit k logic chi
tit v cng ngh dng gi ca my tnh.
! Kin trc tp lnh thay di chm, t chc v
phn cng my tnh thay di rt nhanh.
NKK-HUST
Kin trc tp lnh
Kin trc tp lnh ca my tnh bao gm:
! Tp lnh: tp hop cc chui s nhj phn
m ho cho cc thao tc m my tnh
c th thuc hin
! Cc kiu d liu: cc kiu d liu m
my tnh c th x l
NKK-HUST
Cu trc co bn ca my tnh
CPU B! nh" chnh
Bus lin k#t h$ th%ng
H$ th%ng vo-ra
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! B x l trung tm (Central Processing Unit):
iu khin hoat dng ca my tnh v x l d
liu.
! B nh chnh (Main Memory): Cha cc
chuong trnh v d liu dang duoc s dung.
! H thng vo-ra (Input/Output System): Trao
di thng tin gia my tnh vi bn ngoi.
! Bus lin kt h thng (System Interconnection
Bus): Kt ni v vn chuyn thng tin gia cc
thnh phn vi nhau.
Cc thnh phn co bn ca my tnh
NKK-HUST
M hnh phn lp ca my tnh

! Phn cng (Hardware): h thng vt l ca my tnh.
! Phn mm (Software): cc chuong trnh v d liu.
Cc ph!n m"m #ng d$ng
Cc ph!n m"m trung gian
H% &i"u hnh
Ph!n c#ng
Ng'(i s)
d$ng
Ng'(i l*p
trnh
Ng'(i
thi+t k+
H,H
Ph!n m"m
#ng d$ng
Ph!n m"m
trung gian
H% &i"u hnh
Ki'n trc
t(p lnh
Vi ki'n trc
Logic-s)
M*ch &i%n t+
NKK-HUST
1.3. Su tin ha ca my tnh
Cc th h my tnh
! Th h th nht: My tnh dng dn din t
chn khng (1950s)
! Th h th hai: My tnh dng transistor
(1960s)
! Th h th ba: My tnh dng vi mach SSI,
MSI v LSI (1970s)
! Th h th tu: My tnh dng vi mach VLSI
(1980s)
! Th h th nm: My tnh dng vi mach
ULSI, SoC (1990s-nay)
NKK-HUST
! Electronic Numerical Intergator and
Computer
! Du n ca B Quc phng M
! Do John Mauchly v John Presper
Eckert ai hoc Pennsylvania thit k.
! Bt du t 1943, hon thnh 1946
! Nng 30 tn
! 18000 dn din t v 1500 role
! 5000 php cng/giy
! X l theo s thp phn
! B nh chi luu tr d liu
! Lp trnh bng cch thit lp vj tr ca
cc chuyn mach v cc cp ni.
ENIAC My tnh din t du tin
NKK-HUST
My tnh von Neumann
! Chnh l my tnh IAS (thuc
hin tai Princeton Institute for
Advanced Studies)
! Bt du 1947, hon thnh 1952
! Do John von Neumann thit k
! uoc xy dung theo tung
chuong trnh duoc luu tr -
(stored-program concept) ca
von Neumann/Turing (1945)
! Tr thnh m hnh co bn ca
my tnh
NKK-HUST
! Vi mach hay l mach tch hop (Integrated Circuit
- IC): mach din t gm nhiu transistors v cc
linh kin khc duoc tch hop trn mt chip bn
dn.
! Phn loai vi mach theo qui m tch hop:
! SSI - Small Scale Integration
! MSI - Medium Scale Integration
! LSI - Large Scale Integration
! VLSI - Very Large Scale Integration
! ULSI - Ultra Large Scale Integration
Vi mach
NKK-HUST
! B vi x l (Microprocessors): CPU duoc ch
tao trn mt chip.
! Vi mach diu khin tng hop (Chipset): mt
hoc mt vi vi mach thuc hin duoc nhiu
chc nng diu khin v ni ghp.
! B nh bn dn (Semiconductor Memory):
ROM, RAM, Flash
! H thng trn chip (SoC System on Chip)
! Cc b vi diu khin (Microcontrollers)
Mt s vi mach s din hnh
NKK-HUST
Lut Moore
! Gordon Moore ngui dng sng lp Intel
! S transistors trn chip s gp di sau 18 thng
! Gi thnh ca chip hu nhu khng thay di
! Mt d cao hon, do vy dung dn ngn hon
! Kch thuc nh hon dn ti d phc tap tng ln
! in nng tiu thu t hon
! H thng c t cc chip lin kt vi nhau, do d tng d tin
cy
2.1 / A BRIEF HISTORY OF COMPUTERS 31
9The term mainframe is used for the larger, most powerful computers other than supercomputers. Typical
characteristics of a mainframe are that it supports a large database, has elaborate I/O hardware, and is
used in a central data processing facility.
IBM SYSTEM/360 By 1964, IBM had a firm grip on the computer market with
its 7000 series of machines. In that year, IBM announced the System/360, a new
family of computer products. Although the announcement itself was no surprise, it
contained some unpleasant news for current IBM customers: the 360 product line
was incompatible with older IBMmachines. Thus, the transition to the 360 would be
difficult for the current customer base. This was a bold step by IBM, but one IBMfelt
was necessary to break out of some of the constraints of the 7000 architecture and
to produce a system capable of evolving with the new integrated circuit technology
[PADE81, GIFF87]. The strategy paid off both financially and technically. The 360
was the success of the decade and cemented IBMas the overwhelmingly dominant
computer vendor, with a market share above 70%. And, with some modifications
and extensions, the architecture of the 360 remains to this day the architecture
of IBMs mainframe
9
computers. Examples using this architecture can be found
throughout this text.
The System/360 was the industrys first planned family of computers. The
family covered a wide range of performance and cost. Table 2.4 indicates some of
the key characteristics of the various models in 1965 (each member of the family is
distinguished by a model number). The models were compatible in the sense that
a program written for one model should be capable of being executed by another
model in the series, with only a difference in the time it takes to execute.
The concept of a family of compatible computers was both novel and
extremely successful. A customer with modest requirements and a budget to match
could start with the relatively inexpensive Model 30. Later, if the customers needs
grew, it was possible to upgrade to a faster machine with more memory without
1
1947
First w
orking
transistor
M
oores law
prom
ulgated
Invention of
integrated circuit
50 55 60 65 70 75 80 85 90 95 2000 05 11
10
100
1000
10,000
100,000
10 m
100 m
1 bn
10 bn
100 bn
Figure 2.8 Growth in Transistor Count on Integrated Circuits
NKK-HUST
Su pht trin ca vi x l
! 1971: b vi x l 4-bit Intel 4004
! 1972: cc b x l 8-bit
! 1978: cc b x l 16-bit
! 1985: cc b x l 32-bit
! 2001: cc b x l 64-bit
! 2006: cc b x l da li (multicores)

NKK-HUST
My tnh ngy nay
Clusters
Massive Cluster
Gigabit Ethernet
Robots
Routers
Cars
Sensor
Nets
R
e
f
r
i
g
e
r
a
t
o
r
s

Robots
Routers
NKK-HUST
1.4. Hiu nng my tnh
! jnh ngha hiu nng P(Performance):
P = 1/ t
trong d: t l thi gian thuc hin
! My tnh A nhanh hon my B n ln
P
A
/ P
B
= t
B
/ t
A
= n
! V du: Thi gian chay chuong trnh:
! 10s trn my A, 15s trn my B
! t
B
/ t
A
= 15s / 10s = 1.5
! Vy my A nhanh hon my B 1.5 ln

NKK-HUST
Xung nhjp ca CPU
! Hoat dng ca CPU duoc diu khin bi xung
nhjp c tn s xc djnh
! Chu ky xung nhjp T
0
(Clock period): thi gian ca
mt chu ky
! Tn s xung nhjp f
0
(Clock rate): s chu ky trong 1
giy.
! f
0
= 1/T
0

! VD: B x l c f
0
= 4GHz = 4000MHz = 410
9
Hz
T
0
= 1/(4x10
9
)

=

0.25x10
9
s = 0.25ns
T
0
NKK-HUST
Thi gian CPU (t
CPU
)
! trong d: n l s chu ky xung nhjp
! Hiu nng duoc tng ln bng cch:
! Gim s chu ky xung nhjp n
! Tng tn s xung nhjp f
0

0
0
f
n
T n t
CPU
= ! =
NKK-HUST
V du
! My tnh A:
! Tn s xung nhjp: f
A
= 2GHz
! Thi gian ca CPU: t
A
= 10s
! My tnh B
B
= 6s
! S chu ky xung nhjp ca B = 1.2 x S chu ky xung nhjp ca A
! Xc djnh tn s xung nhjp ca my B (f
B
)?
NKK-HUST
V du
! My tnh A:
! Tn s xung nhjp: f
A
= 2GHz
A
= 10s
! My tnh B
B
= 6s
! S chu ky xung nhjp ca B = 1.2 x S chu ky xung nhjp ca A
! Xc djnh tn s xung nhjp ca my B (f
B
)?
! Gii:
GHz
s s
f
GHz s f t n
s
n
t
n
f
B
A A A
A
B
B
B
4
6
10 24
6
10 20 2 . 1
10 20 2 10
6
2 . 1
9 9
9
=
!
=
! !
=
! = ! = ! =
!
= =
NKK-HUST
S lnh v s chu ky trn mt lnh
! Trong trung hop cc lnh khc nhau c CPI khc
nhau, cn tnh CPI trung bnh
! S chu ky = S lnh x S chu ky trn mt lnh
CPI IC n ! =
n - s chu ky, IC - s lnh (Instruction Count), CPI - s
chu ky trn mt lnh (Cycles per Instruction)

! Thi gian thuc hin ca CPU:
0
0
f
CPI IC
T CPI IC t
CPU
!
= ! ! =
NKK-HUST
V du
! My tnh A: T
A
= 250ps, CPI
A
= 2.0
! My tnh B: T
B
= 500ps, CPI
B
= 1.2
! Cng kin trc tp lnh (ISA)
! My no nhanh hon v nhanh hon bao nhiu ?
NKK-HUST
V du
! My tnh A: T
A
= 250ps, CPI
A
= 2.0
! My tnh B: T
B
= 500ps, CPI
B
= 1.2
! Cng kin trc tp lnh (ISA)
! My no nhanh hon v nhanh hon bao nhiu ?
1.2
500ps IC
600ps IC
A
t
B
t
600ps IC 500ps 1.2 IC
B
T
B
CPI IC
B
t
500ps IC 250ps 2.0 IC
A
T
A
CPI IC
A
t
=
!
!
=
! = ! ! =
! ! =
! = ! ! =
! ! =
Vy:
A nhanh hon B 1.2 ln
NKK-HUST
Chi tit hon v CPI
! Nu loai lnh khc nhau c s chu ky khc
nhau, ta c tng s chu ky:
!
=
" =
K
1 i
i i
) IC (CPI n
! CPI trung bnh:
!
=
"
#
$
%
&
'
( = =
K
1 i
i
i TB
IC
IC
CPI
IC
n
CPI
NKK-HUST
V du
! Cho bng chi ra cc dy lnh s dung cc lnh
thuc cc loai A, B, C. Tnh CPI trung bnh?
Loai lnh A B C
CPI theo loai lnh 1 2 3
IC trong dy lnh 1 2 1 2
NKK-HUST
V du
! Cho bng chi ra cc dy lnh s dung cc lnh
thuc cc loai A, B, C. Tnh CPI trung bnh?
Loai lnh A B C
CPI theo loai lnh 1 2 3
! Dy lnh 1: IC = 5
! S chu ky
= 21 + 12 + 23
= 10
! CPI
TB
= 10/5 = 2.0
! Dy lnh 2: IC = 6
! S chu ky
= 41 + 12 + 13
= 9
! CPI
TB
= 9/6 = 1.5
NKK-HUST
Tm tt v Hiu nng
! Hiu nng phu thuc vo:
! Thut ton
! Ngn ng lp trnh
! Chuong trnh djch
! Kin trc tp lnh

cycle Clock
Seconds
n Instructio
cycles Clock
Program
ns Instructio
Time CPU ! ! =
0
0
f
CPI IC
T CPI IC t
CPU
!
= ! ! =
NKK-HUST
MIPS nhu l thuc do hiu nng
! MIPS: Millions of Instructions Per Second
(S triu lnh trn 1 giy)

10 CPI
rate Clock
10
rate Clock
CPI count n Instructio
count n Instructio
10 time Execution
count n Instructio
MIPS
6
6
6
!
=
!
!
=
!
=
6
0
10 MIPS
f
CPI
!
=
6
0
10 CPI
f
MIPS
!
=
NKK-HUST
V du
Tnh MIPS ca b x l vi:
clock rate = 2GHz v CPI = 4
NKK-HUST
V du
Tnh MIPS ca b x l vi:
clock rate = 2GHz v CPI = 4
0.5ns
2ns
1 chu ky = 1/(2x10
9
) = 0,5ns
CPI = 4 " thi gian thuc hin 1 lnh:
4 x 0,5ns = 2ns
Vy b x l thuc hin duoc 500 MIPS
NKK-HUST
V du
Tnh CPI ca b x l vi:
clock rate = 1GHz v 400 MIPS?
NKK-HUST
V du
Tnh CPI ca b x l vi:
clock rate = 1GHz v 400 MIPS?
1ns
4x10
8
lnh thuc hin trong 1s
" 1 lnh thuc hin trong 1/(4x10
8
)s = 2,5ns
" CPI = 2,5
NKK-HUST
MFLOPS
Millions of Floating Point Operations per Second
(S triu php ton s du phy dng trn mt giy)
GFLOPS10
9

TFLOPS10
12

6
10 time Execution
operations point floating Executed
MFLOPS
!
=
NKK-HUST
H%t ch!"ng 1
NKK-HUST
Kin trc my tnh
Ch!"ng 2
C& B'N V( LOGIC S)
Nguy!n Kim Khnh
NKK-HUST
Ni dung hoc phn
Chuong 6. B x l

NKK-HUST
2.1. Cc h dm co bn
2.2. ai s Boole
2.3. Cc cng logic
2.4. Mach t hop
2.5. Mach dy
Ni dung ca chuong 2
NKK-HUST
2.1. Cc h dm co bn
! H thp phn (Decimal System)
" con ngui s dung
! H nhj phn (Binary System)
" my tnh s dung
! H mui su (Hexadecimal System)
" dng d vit gon cho s nhj phn
NKK-HUST
1. H thp phn
! Co s 10
! 10 ch s: 0,1,2,3,4,5,6,7,8,9
! Dng n ch s thp phn c th biu din
duoc 10
n
gi trj khc nhau:
! 00...000 = 0
! 99...999 = 10
n
- 1
NKK-HUST
Dang tng qut ca s thp phn
Gi trj ca A duoc hiu nhu sau:
m n n
a ... a a a ... a a A
! ! !
=
1 0 1 1
,
m
m
n
n
n
n
a ... a a a ... a a A
!
!
!
!
!
!
+ + + + + + + = 10 10 10 10 10 10
1
1
0
0
1
1
1
1
i
n
m i
i
a A 10
!
" =
=
NKK-HUST
V du s thp phn
472.38 = 4x10
2
+ 7x10
1
+ 2x10
0
+ 3x10
-1
+ 8x10
-2
! Cc ch s ca phn nguyn:
! 472 : 10 = 47 du 2
! 47 : 10 = 4 du 7
! 4 : 10 = 0 du 4
! Cc ch s ca phn l:
! 0.38 x 10 = 3.8 phn nguyn = 3
! 0.8 x 10 = 8.0 phn nguyn = 8
NKK-HUST
2. H nhj phn
! Co s 2
! 2 ch s nhj phn: 0 v 1
! ch s nhj phn goi l bit (binary digit)
! Bit l don vj thng tin nh nht
! Dng n bit c th biu din duoc 2
n
gi trj
khc nhau:
! 00...000 = 0
! 11...111 = 2
n
- 1
NKK-HUST

Bits, Bytes, Nibbles
! Bits
! Bytes & Nibbles
! Bytes
10010110
nibble
byte
CEBF9AD7
least
significant
byte
most
significant
byte
10010110
least
significant
bit
most
significant
bit
NKK-HUST

Ly tha hai
! 2
10
= 1 kilo = 1000 (1024)
! 2
20
= 1 mega = 1 triu (1,048,576)
! 2
30
= 1 giga = 1 t (1,073,741,824)
! 2
40
= 1 tera = 1000 t
! 2
50
= 1 peta = 1 triu t
NKK-HUST
Dang tng qut ca s nhj phn
Gi trj ca A duoc tnh nhu sau:
m n n
a ... a a a ... a a A
! ! !
=
1 0 1 1
,
m
m
n
n
n
n
a ... a a a ... a a A
!
!
!
!
!
!
+ + + + + + + = 2 2 2 2 2 2
1
1
0
0
1
1
1
1
i
n
m i
i
a A 2
!
" =
=
C mt s nhj phn A nhu sau:
NKK-HUST
V du s nhj phn
1101001.1011
(2)
=
6 5 4 3 2 1 0 -1 -2 -3 -4

= 2
6
+ 2
5
+ 2
3
+ 2
0
+ 2
-1
+ 2
-3
+ 2
-4

= 64 + 32 + 8 + 1 + 0.5 + 0.125 + 0.0625

= 105.6875
(10)
NKK-HUST
Chuyn di s nguyn thp phn sang nhj phn
! Phuong php 1: chia dn cho 2 ri ly
phn du
! Phuong php 2: Phn tch thnh tng
ca cc s 2
i
" nhanh hon
NKK-HUST
Phuong php chia dn cho 2
! V du: chuyn di 105
(10)

! 105 : 2 = 52 du 1
! 52 : 2 = 26 du 0
! 26 : 2 = 13 du 0
! 13 : 2 = 6 du 1
! 6 : 2 = 3 du 0
! 3 : 2 = 1 du 1
! 1 : 2 = 0 du 1
! Kt qu: 105
(10)
= 1101001
(2)

NKK-HUST
Phuong php phn tch thnh tng ca cc 2
i
! Kt qu: 105
(10)
= 0110 1001
(2)

2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0

128 64 32 16 8 4 2 1
0 1 1 0 1 0 0 1
! V du 1: chuyn di 105
(10)

! 105 = 64 + 32 + 8 +1 = 2
6
+ 2
5
+ 2
3
+ 2
0

! V du 2: 17000
(10)
= 16384 + 512 + 64 + 32 + 8
= 2
14
+ 2
9
+ 2
6
+ 2
5
+ 2
3
17000
(10)
= 0100 0010 0110 1000
(2)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NKK-HUST
Chuyn di s l thp phn sang nhj phn
! V du 1: chuyn di 0.6875
(10)

! 0.6875 x 2 = 1.375 phn nguyn = 1
! 0.375 x 2 = 0.75 phn nguyn = 0
! 0.75 x 2 = 1.5 phn nguyn = 1
! 0.5 x 2 = 1.0 phn nguyn = 1
! Kt qu : 0.6875
(10)
= 0.1011
(2)
NKK-HUST
Chuyn di s l thp phn sang nhj phn (tip)
(10)

! 0.81 x 2 = 1.62 phn nguyn = 1
! 0.62 x 2 = 1.24 phn nguyn = 1
! 0.24 x 2 = 0.48 phn nguyn = 0
! 0.48 x 2 = 0.96 phn nguyn = 0
! 0.96 x 2 = 1.92 phn nguyn = 1
! 0.92 x 2 = 1.84 phn nguyn = 1
! 0.84 x 2 = 1.68 phn nguyn = 1
! 0.81
(10)
! 0.1100111
(2)

NKK-HUST
Chuyn di s l thp phn sang nhj phn (tip)
(10)

! 0.2 x 2 = 0.4 phn nguyn = 0
! 0.4 x 2 = 0.8 phn nguyn = 0
! 0.8 x 2 = 1.6 phn nguyn = 1
! 0.6 x 2 = 1.2 phn nguyn = 1
! 0.2 x 2 = 0.4 phn nguyn = 0
! 0.4 x 2 = 0.8 phn nguyn = 0
! 0.8 x 2 = 1.6 phn nguyn = 1
! 0.6 x 2 = 1.2 phn nguyn = 1
! 0.2
(10)
! 0.00110011
(2)

NKK-HUST
3. H mui su (Hexa)
! Co s 16
! 16 ch s: 0,1,2,3,4,5,6,7,8,9, A,B,C,D,E,F
! Dng d vit gon cho s nhj phn: c mt
nhm 4-bit s duoc thay bng mt ch s
Hexa
NKK-HUST
Quan h gia s nhj phn v s Hexa
4-bit Ch! s" Hexa
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 A
1011 B
1100 C
1101 D
1110 E
1111 F
V du chuyn di s nhj phn " s Hexa:
! 1011 0011
2
= B3
16

! 0000 0000
2
= 00
16

! 0010 1101 1001 1010
2
= 2D9A
16
! 1111 1111 1111 1111
2
= FFFF
16
NKK-HUST
2.2. ai s Boole
! ai s Boole s dung cc bin logic v php
ton logic
! Bin logic c th nhn gi trj 1 (TRUE) hoc 0
(FALSE)
! Php ton logic co bn l AND, OR v NOT
vi k hiu nhu sau:
! A AND B : AB
! A OR B : A + B
! NOT A : A
! Th tu uu tin: NOT > AND > OR
NKK-HUST
Cc php ton logic (tip)
! Cc php ton NAND, NOR, XOR:
! A NAND B:
! A NOR B :
! A XOR B:
B A
B A+
B A B A B A + = !
NKK-HUST
Php ton dai s Boole
P Q P
P AND Q
PQ
P OR Q
P + Q
P NAND Q
PQ
P NOR Q
P+Q
P XOR Q
P " Q
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
1
1
0
NKK-HUST
Cc dng nht thc ca dai s Boole
A B = B A
A (B + C) = (A B) + (A C)
1 A = A
A A = 0
A + B = B + A
A + (B C) = (A + B) ( A + C)
0 + A = A
A + A = 1
0 A = 0
A A = A
A (B C) = (A B) C
A B = A + B (#(nh l) De Morgan)
1 + A = 1
A + A = A
A + (B + C) = (A + B) + C
A + B = A B (#(nh l) De Morgan)
NKK-HUST
2.3. Cc cng logic (Logic Gates)
! Thuc hin cc hm logic:
! NOT, AND, OR, NAND, NOR, etc.
! Cng logic mt du vo:
! Cng NOT, b dm (buffer)
! Cng hai du vo:
! AND, OR, XOR, NAND, NOR, XNOR
! Cng nhiu du vo
NKK-HUST
Cc cng logic
368 CHAPTER 11 / DIGITAL LOGIC
11.2 GATES
The fundamental building block of all digital logic circuits is the gate. Logical func-
tions are implemented by the interconnection of gates.
A gate is an electronic circuit that produces an output signal that is a sim-
ple Boolean operation on its input signals. The basic gates used in digital logic are
AND, OR, NOT, NAND, NOR, and XOR. Figure 11.1 depicts these six gates. Each
gate is defined in three ways: graphic symbol, algebraic notation, and truth table.
The symbology used in this chapter is from the IEEE standard, IEEE Std 91. Note
that the inversion (NOT) operation is indicated by a circle.
Each gate shown in Figure 11.1 has one or two inputs and one output.
However, as indicated in Table 11.1b, all of the gates except NOT can have more
than two inputs. Thus, (X + Y + Z) can be implemented with a single OR gate
with three inputs. When one or more of the values at the input are changed, the
correct output signal appears almost instantaneously, delayed only by the propaga-
tion time of signals through the gate (known as the gate delay). The significance of
this delay is discussed in Section 11.3. In some cases, a gate is implemented with two
outputs, one output being the negation of the other output.
A B F
0 0 1
0 1 0
1 0 0
1 1 0
A B F
0 0 0
0 1 1
1 0 1
1 1 0
Graphical Symbol
Algebraic
Function
Truth Table Name
AND
OR
NOT
NAND
NOR
XOR
F A B
or
F AB
F A B
A B F
0
0
1
1
0
0
0
1
0
1
0
1
A B F
0
0
1
1
0
1
1
1
0
1
0
1
A B F
0
0
1
1
1
1
1
0
0
1
0
1
A F
0
1
1
0
A
A
B
F A
or
F A
F AB
F A B
F A B
F
A
B
F
A
B
F
F
A
B
F
A
B
F
Figure 11.1 Basic Logic Gates
NKK-HUST
Tp dy d
! L tp cc cng c th thuc hin duoc
bt ky hm logic no t cc cng ca
tp d.
! Mt s v du v tp dy d:
! {AND, OR, NOT}
! {AND, NOT}
! {OR, NOT}
! {NAND}
! {NOR}
NKK-HUST
S dung cng NAND
11.2 / GATES 369
Here we introduce a common term: we say that to assert a signal is to cause a
signal line to make a transition from its logically false (0) state to its logically true
(1) state. The true (1) state is either a high or low voltage state, depending on the
type of electronic circuitry.
Typically, not all gate types are used in implementation. Design and fabrication
are simpler if only one or two types of gates are used. Thus, it is important to identify
functionally complete sets of gates. This means that any Boolean function can be imple-
mented using only the gates in the set. The following are functionally complete sets:
AND, OR, NOT
AND, NOT
OR, NOT
NAND
NOR
It should be clear that AND, OR, and NOT gates constitute a functionally
complete set, because they represent the three operations of Boolean algebra. For
the AND and NOT gates to form a functionally complete set, there must be a way
to synthesize the OR operation from the AND and NOT operations. This can be
done by applying DeMorgans theorem:
A + B = A
#
B
A OR B = NOT((NOT A) AND(NOT B))
Similarly, the OR and NOT operations are functionally complete because
they can be used to synthesize the AND operation.
Figure 11.2 shows how the AND, OR, and NOT functions can be implemented
solely with NAND gates, and Figure 11.3 shows the same thing for NOR gates.
For this reason, digital circuits can be, and frequently are, implemented solely with
NAND gates or solely with NOR gates.
A
A
A
B
A
B
A
B
A+B
A B
A B
Figure 11.2 Some Uses of NAND Gates
NKK-HUST
S dung cng NOR
With gates, we have reached the most primitive circuit level of computer
hardware. An examination of the transistor combinations used to construct gates
departs from that realm and enters the realm of electrical engineering. For our pur-
poses, however, we are content to describe how gates can be used as building blocks
to implement the essential logical circuits of a digital computer.
11.3 COMBINATIONAL CIRCUITS
A combinational circuit is an interconnected set of gates whose output at any time
is a function only of the input at that time. As with a single gate, the appearance of
the input is followed almost immediately by the appearance of the output, with only
gate delays.
In general terms, a combinational circuit consists of n binary inputs and m
binary outputs. As with a gate, a combinational circuit can be defined in three ways:
Truth table: For each of the 2
n
possible combinations of input signals, the
binary value of each of the m output signals is listed.
Graphical symbols: The interconnected layout of gates is depicted.
Boolean equations: Each output signal is expressed as a Boolean function of
its input signals.
Implementation of Boolean Functions
Any Boolean function can be implemented in electronic form as a network of gates.
For any given function, there are a number of alternative realizations. Consider the
Boolean function represented by the truth table in Table 11.3. We can express this func-
tion by simply itemizing the combinations of values of A, B, and C that cause F to be 1:
F + ABC + ABC + ABC (11.1)
A A
A
B
A
B
A (A+B)
B
A+B
A B
Figure 11.3 Some Uses of NOR Gates
NKK-HUST
Mt s v du vi mach logic
20-34 CHAPTER 20 / DIGITAL LOGIC
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC 4B 4A 4Y 3B 3A 3Y
1A 1B 1Y 2A 2B 2Y GND
7400
14 13 12 11 10 9 8
1 2 3 4 5 6 7
7408
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC 2D 2C NC 2B 2A 2Y
1A 1B NC 1C 1D 1Y GND
7422
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC 1C 1Y 3C 3B 3A 3Y
1A 1B 2A 2B 2C 2Y GND
7411
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC 6A 6Y 5A 5Y 4A 4Y
1A 1Y 2A 2Y 3A 3Y GND
7404
14 13 12 11 10 9 8
1 2 3 4 5 6 7
7432
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC NC H G NC NC Y
A B C D E F GND
7430
14 13 12 11 10 9 8
1 2 3 4 5 6 7
7486
Figure 20.32 Some SSI Chips. Pin layouts fromThe TTL Data Book for Design Engineers,
copyright 1976 Texas Instrument Incorporated.
NKK-HUST
2.4. Mach t hop
! Mach logic l mach bao gm:
! Cc du vo (Inputs)
! Cc du ra (Outputs)
! c t chc nng (Functional specification)
! c t thi gian (Timing specification)
! Cc kiu mach logic:
! Mach logic t hop (Combinational Logic)
! Mach khng nh
! u ra duoc xc djnh bi cc gi trj hin tai ca du vo
! Mach logic dy (Sequential Logic)
! Mach c nh
! u ra duoc xc djnh bi cc gi trj truc d v gi trj hin tai
ca du vo
NKK-HUST
Mach t hop
! Mach t hop l mach logic trong d du
ra chi phu thuc du vo thi dim
hin tai.
! L mach khng nh v duoc thuc hin
bng cc cng logic co bn
! Mach t hop c th duoc djnh ngha
theo ba cch:
! Bng tht
! Dang so d
! Phuong trnh Boole
NKK-HUST
V du
C AB BC A C B A F + + =
A B C F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
11.3 / COMBINATIONAL CIRCUITS 371
There are three combinations of input values that cause F to be 1, and if any
one of these combinations occurs, the result is 1. This form of expression, for self-
evident reasons, is known as the sum of products (SOP) form. Figure 11.4 shows a
straightforward implementation with AND, OR, and NOT gates.
Another form can also be derived from the truth table. The SOP form
expresses that the output is 1 if any of the input combinations that produce 1 is true.
We can also say that the output is 1 if none of the input combinations that produce
0 is true. Thus,
F = 1A B C2 # 1A B C2 # 1A B C2 # 1A B C2 # 1A B C2
This can be rewritten using a generalization of DeMorgans theorem:
(X # Y # Z) = X + Y + Z
Table 11.3 A Boolean Function of Three Variables
A B C F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
A B C
F
Figure 11.4 Sum-of-Products Implementation of Table 11.3
NKK-HUST
B dn knh (Multiplexer-MUX)
! 2
n
du vo d liu
! n du vo chon
! 1 du ra
! u vo chon (S) xc djnh du vo no (D) s
duoc ni vi du ra (F).
S2 S1 F
0
0
1
1
0
1
0
1
D0
D1
D2
D3
NAND AND NOR IMPLEMENTATIONS Another consideration in the
implementation of Boolean functions concerns the types of gates used. It is sometimes
desirable to implement a Boolean function solely with NAND gates or solely with
NOR gates. Although this may not be the minimum-gate implementation, it has the
advantage of regularity, which can simplify the manufacturing process. Consider
again Equation (11.3):
F = B(A + C)
Because the complement of the complement of a value is just the original value,
F = B(A + C) = (AB + (BC)
Applying DeMorgans theorem,
F = (AB)(BC)
which has three NAND forms, as illustrated in Figure 11.11.
Multiplexers
The multiplexer connects multiple inputs to a single output. At any time, one of the
inputs is selected to be passed to the output. A general block diagram representation
is shown in Figure 11.12. This represents a 4-to-1 multiplexer. There are four input
lines, labeled D0, D1, D2, and D3. One of these lines is selected to provide the
A
B
B
C
F
Figure 11.11 NAND Implementation of
Table 11.3
D0
D1
D2
S2 S1
D3
F
4-to-1
MUX
Figure 11.12 4-to-1 Multiplexer
Representation
NKK-HUST
Thuc hin MUX bn du vo
output signal F. To select one of the four possible inputs, a 2-bit selection code is
needed, and this is implemented as two select lines labeled S1 and S2.
An example 4-to-1 multiplexer is defined by the truth table in Table 11.7. This
is a simplified form of a truth table. Instead of showing all possible combinations of
input variables, it shows the output as data from line D0, D1, D2, or D3. Figure 11.13
shows an implementation using AND, OR, and NOT gates. S1 and S2 are connected
to the AND gates in such a way that, for any combination of S1 and S2, three of the
AND gates will output 0. The fourth AND gate will output the value of the selected
line, which is either 0 or 1. Thus, three of the inputs to the OR gate are always 0,
and the output of the OR gate will equal the value of the selected input gate. Using
this regular organization, it is easy to construct multiplexers of size 8-to-1, 16-to-1,
and so on.
Multiplexers are used in digital circuits to control signal and data routing. An
example is the loading of the program counter (PC). The value to be loaded into the
program counter may come from one of several different sources:
D0
D1
D2
D3
S1 S2
F
Figure 11.13 Multiplexer Implementation
Table 11.7 4-to-1 Multiplexer Truth Table
S2 S1 F
0 0 D0
0 1 D1
1 0 D2
1 1 D3
NKK-HUST
B gii m (Decoder)
! N du vo, 2
N
du ra
! Chi c mt du ra tch cuc (duoc chon) tuong
ng vi mt t hop ca N du vo.
2:4
Decoder
A1
A0
Y3
Y2
Y1
Y0 00
01
10
11
0 0
0 1
1 0
1 1
0
0
0
1
Y3 Y2 Y1 Y0 A0 A1
0
0
1
0
0
1
0
0
1
0
0
0
Y3
Y2
Y1
Y0
A0 A1
NKK-HUST
Thuc hin b gii m 3 ra 8
A
D0
000
D1
001
D2
010
D3
011
D4
100
D5
101
D6
110
D7
111
B
C
Figure 11.15 Decoder with 3 Inputs and 2
3
= 8 Outputs
256 8
RAM
256 8
RAM
256 8
RAM
256 8
RAM
Enable Enable Enable Enable
A0
A7
A8
A9
2-to-4
Decoder
Figure 11.16 Address Decoding
NKK-HUST
B cng (Adder)
! B cng bn phn (Half-adder)
! Cng hai bit tao ra bit tng v bit nh
! B cng ton phn (Full-adder)
! Cng 3 bit
! Cho php xy dung b cng N-bit
NKK-HUST
B cng (tip)
NKK-HUST
B cng 4-bit v b cng 32-bit
Thus we have the necessary logic to implement a multiple-bit adder such as
shown in Figure 11.21. Note that because the output from each adder depends on
the carry from the previous adder, there is an increasing delay from the least signifi-
cant to the most significant bit. Each single-bit adder experiences a certain amount
of gate delay, and this gate delay accumulates. For larger adders, the accumulated
delay can become unacceptably high.
If the carry values could be determined without having to ripple through all
the previous stages, then each single-bit adder could function independently, and
delay would not accumulate. This can be achieved with an approach known as carry
lookahead. Let us look again at the 4-bit adder to explain this approach.
We would like to come up with an expression that specifies the carry input to
any stage of the adder without reference to previous carry values. We have
C
A
B
C
A
B
C
A
B
C
A
B
B
A
C
A
C
B
Sum
Carry
Figure 11.20 Implementation of an Adder
A31
C23
Cout
B31
S31 S24
A24 B24
8-bit
adder
A23
C15
B23
S23 S16
A16 B16
8-bit
adder
A15
C7
B15
S15 S8
A8 B8
8-bit
adder
A7
Cin
B7
S7 S0
A0 B0
8-bit
adder
Figure 11.21 Construction of a 32-Bit Adder Using 8-Bit Adders
0 0 1 1
+0 +1 +0 +1
0 1 1 10
However, addition can still be dealt with in Boolean terms. In Table 11.9a, we
show the logic for adding two input bits to produce a 1-bit sum and a carry bit.
This truth table could easily be implemented in digital logic. However, we are not
interested in performing addition on just a single pair of bits. Rather, we wish to
add two n-bit numbers. This can be done by putting together a set of adders so that
the carry from one adder is provided as input to the next. A 4-bit adder is depicted
in Figure 11.19.
For a multiple-bit adder to work, each of the single-bit adders must have three
inputs, including the carry from the next-lower-order adder. The revised truth table
appears in Table 11.9b. The two outputs can be expressed:
Sum = A BC + ABC + ABC + ABC
Carry = AB + AC + BC
Figure 11.20 is an implementation using AND, OR, and NOT gates.
A3
C3
S3
Cin
B3 A2
C2
S2
Cin
B2 A1
C1
S1
Cin
B1 A0
C0
S0
Cin 0
B0
Overflow
signal
Figure 11.19 4-Bit Adder
Table 11.9 Binary Addition Truth Tables
(a) Single-Bit Addition
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
(b) Addition with Carry Input
Cin A B Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
NKK-HUST
2.5. Mach dy
! Mach dy l mach logic trong d du ra
phu thuc gi trj du vo thi dim
hin tai v qu kh
! L mach c nh, duoc thuc hin bng
phn t nh (Latch, Flip-Flop) v c th
kt hop vi cc cng logic co bn
! Mach dy bao gm:
! Mach t hop
! Mach hi tip
NKK-HUST
Cc thnh phn chnh ca mach dy
NKK-HUST
Cc Flip-Flop co bn
Name Graphical Symbol Truth Table
SR
S Q
R Q
S R
0 0
0
1
1
Qn
Qn1
1
0
0
1
1
JK
J Q
K Q
J K
0 0
0
1
1
Qn
Qn
Qn1
1
0 0
1
1
D
D Q
Q
D
0 0
1
Qn1
1
Ck
Ck
Ck
Figure 11.27 Basic Flip-Flops
causing the output to be 1; if only the Kinput is asserted, the result is a reset function,
causing the output to be 0. When both J and K are 1, the function performed is
referred to as the toggle function: the output is reversed. Thus, if Qis 1 and 1 is applied
to J and K, then Q becomes 0. The reader should verify that the implementation of
Figure 11.26 produces this characteristic function.
J
K
Q
Q
Clock
Figure 11.26 JK Flip-Flop
NKK-HUST
R-S Latch v cc Flip-Flop
R-S Latch
R-S Flip Flop
J-K Flip Flop
D Flip Flop
NKK-HUST
Thanh ghi 8-bit song song
11.4 / SEQUENTIAL CIRCUITS 393
Registers
As an example of the use of flip-flops, let us first examine one of the essential ele-
ments of the CPU: the register. As we know, a register is a digital circuit used within
the CPU to store one or more bits of data. Two basic types of registers are com-
monly used: parallel registers and shift registers.
PARALLEL REGISTERS A parallel register consists of a set of 1-bit memories that
can be read or written simultaneously. It is used to store data. The registers that we
have discussed throughout this book are parallel registers.
The 8-bit register of Figure 11.28 illustrates the operation of a parallel register
using D flip-flops. A control signal, labeled load, controls writing into the register
from signal lines, D11 through D18. These lines might be the output of multiplexers,
so that data from a variety of sources can be loaded into the register.
SHIFT REGISTER A shift register accepts and/or transfers information serially.
Consider, for example, Figure 11.29, which shows a 5-bit shift register constructed
from clocked D flip-flops. Data are input only to the leftmost flip-flop. With each
clock pulse, data are shifted to the right one position, and the rightmost bit is
transferred out.
Shift registers can be used to interface to serial I/O devices. In addition, they
can be used within the ALU to perform logical shift and rotate functions. In this
D
D08
D18
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q
Clock
Load
D17 D16 D15 D14 D13 D12 D11
D07 D06 D05
Output lines
Data lines
D04 D03 D02 D01
Figure 11.28 8-Bit Parallel Register
D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q
Clock
Serial in Serial out
Figure 11.29 5-Bit Shift Register
NKK-HUST
Thanh ghi djch 5-bit
11.4 / SEQUENTIAL CIRCUITS 393
Registers
As an example of the use of flip-flops, let us first examine one of the essential ele-
ments of the CPU: the register. As we know, a register is a digital circuit used within
the CPU to store one or more bits of data. Two basic types of registers are com-
monly used: parallel registers and shift registers.
PARALLEL REGISTERS A parallel register consists of a set of 1-bit memories that
can be read or written simultaneously. It is used to store data. The registers that we
have discussed throughout this book are parallel registers.
The 8-bit register of Figure 11.28 illustrates the operation of a parallel register
using D flip-flops. A control signal, labeled load, controls writing into the register
from signal lines, D11 through D18. These lines might be the output of multiplexers,
so that data from a variety of sources can be loaded into the register.
SHIFT REGISTER A shift register accepts and/or transfers information serially.
Consider, for example, Figure 11.29, which shows a 5-bit shift register constructed
from clocked D flip-flops. Data are input only to the leftmost flip-flop. With each
clock pulse, data are shifted to the right one position, and the rightmost bit is
transferred out.
Shift registers can be used to interface to serial I/O devices. In addition, they
can be used within the ALU to perform logical shift and rotate functions. In this
D
D08
D18
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q
Clock
Load
D17 D16 D15 D14 D13 D12 D11
D07 D06 D05
Output lines
Data lines
D04 D03 D02 D01
Figure 11.28 8-Bit Parallel Register
D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q D
Clk
Q
Clock
Serial in Serial out
Figure 11.29 5-Bit Shift Register
NKK-HUST
B dm 4-bit
latter capacity, they need to be equipped with parallel read/write circuitry as well
as serial.
Counters
Another useful category of sequential circuit is the counter. A counter is a register
whose value is easily incremented by 1 modulo the capacity of the register; that is,
after the maximum value is achieved the next increment sets the counter value to 0.
Thus, a register made up of n flip-flops can count up to 2
n
- 1. An example of a
counter in the CPU is the program counter.
Counters can be designated as asynchronous or synchronous, depending on
the way in which they operate. Asynchronous counters are relatively slow because
the output of one flip-flop triggers a change in the status of the next flip-flop. In a
synchronous counter, all of the flip-flops change state at the same time. Because the
latter type is much faster, it is the kind used in CPUs. However, it is useful to begin
the discussion with a description of an asynchronous counter.
RIPPLE COUNTER An asynchronous counter is also referred to as a ripple counter,
because the change that occurs to increment the counter starts at one end and
ripples through to the other end. Figure 11.30 shows an implementation of a
4-bit counter using JK flip-flops, together with a timing diagram that illustrates its
behavior. The timing diagram is idealized in that it does not show the propagation
delay that occurs as the signals move down the series of flip-flops. The output of
the leftmost flip-flop (Q0) is the least significant bit. The design could clearly be
extended to an arbitrary number of bits by cascading more flip-flops.
J Q
Q0
Q0
Q1
Q2
Q3
K Q
Ck
J Q
Q1
K Q
Ck
J Q
Q2
K Q
Ck
J Q
Q3
K Q
Ck Clock
Clock
High
(a) Sequential circuit
(b) Timing diagram
Figure 11.30 Ripple Counter
NKK-HUST
H%t ch!"ng 2
NKK-HUST
Kin trc my tnh
Ch!"ng 3
H$ TH)NG MY TNH
Nguy!n Kim Khnh
NKK-HUST
Ni dung hoc phn
Chuong 6. B x l

NKK-HUST
3.1. Cc thnh phn co bn ca my tnh
3.2. Hoat dng co bn ca my tnh
3.3. Bus my tnh
Ni dung ca chuong 3
NKK-HUST
3.1. Cc thnh phn co bn ca my tnh
! B x l trung tm (CPU)
! B nh (Memory)
! Vo ra (Input/Output )
! Bus lin kt h thng (System Interconnection Bus)
NKK-HUST
! Chc nng:
! diu khin hoat dng ca my tnh
! x l d liu
! Nguyn tc hoat dng co bn:
CPU hoat dng theo chuong trnh nm trong
b nh chnh.
1. B x l trung tm (CPU)
NKK-HUST
Cu trc co bn ca CPU
!"n v#
$i%u khi&n
(CU)
!"n v#
s' h(c v
logic
(ALU)
T)p cc
thanh ghi
(RF)
!"n v# n'i ghp bus (BIU)
bus bn ngoi
bus bn trong
NKK-HUST
! *"n v+ ,i-u khi.n (Control Unit - CU): diu
khin hoat dng ca my tnh theo chuong trnh
d djnh sn.
! *"n v+ s/ h0c v logic (Arithmetic and Logic
Unit - ALU): thuc hin cc php ton s hoc v
php ton logic.
! T1p thanh ghi (Register File - RF): luu gi cc
thng tin tam thi phuc vu cho hoat dng ca
CPU.
! *"n v+ n/i ghp bus (Bus Interface Unit - BIU)
kt ni v trao di thng tin gia bus bn trong
(internal bus) v bus bn ngoi (external bus).
Cc thnh phn co bn ca CPU
NKK-HUST
2. B nh my tnh
! Chc nng: luu tr chuong trnh v d
liu.
! Cc thao tc co bn vi b nh:
! Thao tc ghi (Write)
! Thao tc doc (Read)
! Cc thnh phn chnh:
! B nh trong (Internal Memory)
! B nh ngoi (External Memory)
NKK-HUST
Cc thnh phn ca b nh my tnh
CPU
B! nh"
trong
B! nh"
ngoi
NKK-HUST
! Chc nng v dc dim:
! Cha cc thng tin m CPU c th trao di
truc tip
! Tc d rt nhanh
! Dung luong khng ln
! S dung b nh bn dn: ROM v RAM
! Cc loai b nh trong:
! B nh chnh
! B nh cache (b nh dm)
B nh trong
NKK-HUST
B nh chnh (Main Memory)
! Cha cc chuong trnh v
d liu dang duoc CPU s
dung.
! T chc thnh cc ngn
nh duoc dnh dja chi.
! Ngn nh thung duoc t
chc theo byte.
! Ni dung ca ngn nh c
th thay di, song dja chi vt
l ca ngn nh lun c
djnh.
N2i dung ja chi
1011 0010 0000
1110 0010 0001
0001 1111 0010
1010 1011 0011
0000 1000 0100
1111 1111 0101
0011 1100 0110
1000 1111 0111
1111 0001 1000
0011 1101 1001
1000 1111 1010
0011 0011 1011
1100 1101 1100
0101 1010 1101
1000 1101 1110
1111 0000 1111
NKK-HUST
B nh cache
! B nh c tc d nhanh duoc dt dm gia
CPU v b nh chnh nhm tng tc d
CPU truy cp b nh
! Dung luong nh hon b nh chnh
! Tc d nhanh hon
! Cache thung duoc chia thnh mt s
mc
! Cache c th duoc tch hop trn cng chip
b x l.
! Cache c th c hoc khng
NKK-HUST
B nh ngoi (External Memory)
! Chc nng v dc dim
! Luu gi ti nguyn phn mm ca my tnh
! uoc kt ni vi h thng dui dang cc thit
bj vo-ra
! Dung luong ln
! Tc d chm
! Cc loai b nh ngoi
! B nh t: da cng
! B nh quang: da CD, DVD
! B nh bn dn: nh flash, th nh, SSD
NKK-HUST
3. Vo-ra (Input-Output)
! Chc nng: Trao di thng tin gia my
tnh vi th gii bn ngoi.
! Cc thao tc co bn:
! Vo d liu (Input)
! Ra d liu (Output)
! Cc thnh phn chnh:
! Cc thit bj ngoai vi (Peripheral Devices)
! Cc m-dun vo-ra (IO Modules)
NKK-HUST
Cu trc co bn ca vo-ra
M-!un
vo-ra
M-!un
vo-ra
C"ng
vo-
ra
Thi#t b$
ngo%i vi
Thi#t b$
ngo%i vi
Thi#t b$
ngo%i vi
n&i ghp
v'i CPU
v b(
nh'
chnh
C"ng
vo-
ra
C"ng
vo-
ra
bus
h)
th&ng
NKK-HUST
Cc thit bj ngoai vi
! Chc nng: chuyn di d liu gia
bn trong v bn ngoi my tnh
! Cc loai thit bj ngoai vi co bn
! Thit bj vo: bn phm, chut, my qut ...
! Thit bj ra: mn hnh, my in ...
! Thit bj nh: cc da ...
! Thit bj truyn thng: MODEM ...
NKK-HUST
M-dun vo-ra
! Chc nng: ni ghp cc thit bj ngoai vi
vi my tnh
! Mi m-dun vo-ra c mt hoc mt vi
cng vo-ra (I/O Port).
! Mi cng vo-ra duoc dnh mt dja chi
xc djnh.
! Cc thit bj ngoai vi duoc kt ni v trao
di d liu vi my tnh thng qua cc
cng vo-ra.
NKK-HUST
3.2. Hoat dng co bn ca my tnh
! Thuc hin chuong trnh
! Hoat dng ngt
! Hoat dng vo-ra
NKK-HUST
1. Thuc hin chuong trnh
! L hoat dng co bn ca my tnh
! My tnh lp di lp lai hai buc:
! Nhn lnh
! Thuc hin lnh
! Thuc hin chuong trnh bj dng nu
thuc hin lnh bj li hoc gp lnh dng.
NKK-HUST
Nhn lnh
! Bt du mi chu trnh lnh, CPU nhn lnh t
b nh chnh.
! B dm chuong trnh PC (Program Counter)
ca CPU gi dja chi ca lnh s duoc nhn.
! CPU nhn lnh t ngn nh duoc tr bi PC.
! Lnh duoc nap vo thanh ghi lnh IR
(Instruction Register).
! Sau khi lnh duoc nhn vo, ni dung PC tu
dng tng d tr sang lnh k tip.
NKK-HUST
Minh hoa qu trnh nhn lnh
CPU
l!nh i+2
l!nh i+1
l!nh i
l!nh
l!nh
302
304
303
302
301
300
PC

IR
Tr!"c khi nh#n l$nh i
CPU
l!nh i+2
l!nh i+1
l!nh i
l!nh
l!nh
303
304
303
302
301
300
PC
l!nh i
IR
Sau khi nh!n l"nh i
NKK-HUST
Thuc hin lnh
! B x l gii m lnh d duoc nhn v
pht tn hiu diu khin thuc hin thao
tc m lnh yu cu.
! Cc kiu thao tc ca lnh:
! Trao di d liu gia CPU v b nh chnh
! Trao di d liu gia CPU v m-dun vo-ra
! X l d liu: thuc hin cc php ton s
hoc hoc php ton logic vi cc d liu.
! iu khin r nhnh
! Kt hop cc thao tc trn.
NKK-HUST
2. Hoat dng ngt (Interrupt)
! Khi nim chung v ngt: Ngt l co ch cho
php CPU tam dng chuong trnh dang thuc
hin d chuyn sang thuc hin mt chuong trnh
khc, goi l ch!"ng trnh con ph#c v# ng$t.
! Cc loai ngt:
! Ngt do li khi thuc hin chuong trnh, v du: trn s,
chia cho 0.
! Ngt do li phn cng, v du li b nh RAM.
! Ngt do m-dun vo-ra pht tn hiu ngt dn CPU
yu cu trao di d liu.
! Ngt do b djnh thi trong ch d da chuong trnh
NKK-HUST
Hoat dng ngt (tip)
! Sau khi hon thnh mi mt lnh, b x l kim
tra tn hiu ngt
! Nu khng c ngt " b x l nhn lnh tip theo
ca chuong trnh hin tai
! Nu c tn hiu ngt:
! Tam dng chuong trnh dang thuc hin
! Ct ng cnh (cc thng tin lin quan dn chuong trnh
bj ngt)
! Thit lp PC tr dn chuong trnh con phuc vu ngt
! Chuyn sang thuc hin chuong trnh con phuc vu ngt
! Cui chuong trnh con phuc vu ngt, khi phuc ng
cnh v tip tuc chuong trnh dang bj tam dng
NKK-HUST
Hoat dng ngt (tip)
l!nh i+1
l!nh i
l!nh
l!nh
l!nh
l!nh
Ng"t # $y
. . .
l!nh
l!nh
l!nh
RETURN
. . .
l!nh
l!nh
Ch%&ng trnh
$ang th'c hin
Ch%&ng trnh con
ph(c v( ng"t
NKK-HUST
X l vi nhiu tn hiu yu cu ngt
! X l ngt tun tu
! Khi mt ngt dang
duoc thuc hin, cc
ngt khc s bj cm.
! B x l s b qua cc
ngt tip theo trong khi
dang x l mt ngt
! Cc yu cu ngt vn
dang doi v duoc kim
tra sau khi ngt du
tin duoc x l xong
! Cc ngt duoc thuc
hin tun tu
NKK-HUST
X l vi nhiu tn hiu yu cu ngt
! X l ngt uu tin
! Cc ngt duoc djnh
ngha mc uu tin
khc nhau
! Ngt c mc uu
tin thp hon c th
bj ngt bi ngt uu
tin cao hon
! Xy ra ngt lng
nhau
NKK-HUST
3. Hoat dng vo-ra
! Hoat dng vo-ra: l hoat dng trao di
d liu gia m-dun vo-ra vi bn trong
my tnh.
! Cc kiu hoat dng vo-ra:
! CPU trao di d liu vi m-dun vo-ra
! M-dun vo-ra trao di d liu truc tip vi
b nh chnh (DMA- Direct Memory Access).
NKK-HUST
3.3. Bus my tnh
! Cc m-dun trong my tnh:
! CPU
! M-dun nh
! M-dun vo-ra
# cn duoc kt ni vi nhau
1. Lung thng tin trong my tnh
NKK-HUST
Kt ni m-dun nh
Tn hi!u "i#u khi$n "%c
"&a ch'
d( li!u
Tn hi!u "i#u khi$n ghi
d( li!u ho)c l!nh
M-!un
nh"
NKK-HUST
Kt ni m-dun nh (tip)
! ja chi dua dn d xc djnh ngn nh
! D liu duoc dua dn khi ghi
! D liu hoc lnh duoc dua ra khi doc
(luu : b nh khng phn bit lnh v
d liu)
! Nhn cc tn hiu diu khin:
! iu khin doc (Read)
! iu khin ghi (Write)
NKK-HUST
Kt ni m-dun vo-ra
!"a ch#

tn hi$u !i%u khi&n !'c
tn hi$u !i%u khi&n ghi
Cc tn hi$u !i%u khi&n TBNV

Cc tn hi$u !i%u khi&n ng(t
d) li$u t* bn trong
d) li$u t* TBNV d) li$u !+n bn trong
d) li$u !+n TBNV
M-!un
vo-ra
NKK-HUST
Kt ni m-dun vo-ra (tip)
! ja chi dua dn d xc djnh cng vo-ra
! Ra d liu (Output)
! Nhn d liu t CPU hoc b nh chnh
! ua d liu ra thit bj ngoai vi
! Vo d liu (Input)
! Nhn d liu t thit bj ngoai vi
! ua d liu vo CPU hoc b nh chnh
! Nhn cc tn hiu diu khin t CPU
! Pht cc tn hiu diu khin dn thit bj ngoai vi
! Pht cc tn hiu ngt dn CPU
NKK-HUST
Kt ni CPU
CPU
l!nh
d" li!u
#$a ch%
d" li!u

Cc tn hi!u #i&u khi'n ng(t

Cc tn hi!u #i&u khi'n
b) nh* v vo-ra
NKK-HUST
Kt ni CPU (tip)
! Pht dja chi dn cc m-dun nh hay
cc m-dun vo-ra
! oc lnh v d liu
! ua d liu ra (sau khi x l)
! Pht tn hiu diu khin dn cc m-dun
nh v cc m-dun vo-ra
! Nhn cc tn hiu ngt
NKK-HUST
! Bus: tp hop cc dung kt ni dng d
vn chuyn thng tin gia cc m-dun ca
my tnh vi nhau.
! Cc bus chc nng:
! Bus dja chi
! Bus d liu
! Bus diu khin
! rng bus: l s dung dy ca bus c
th truyn cc bit thng tin dng thi (chi
dng cho bus dja chi v bus d liu)
2. Cu trc bus co bn
NKK-HUST
So d cu trc bus co bn
bus !i"u khi#n
bus !$a ch%
bus d& li'u
CPU
M-!un
nh(
M-!un
vo-ra
M-!un
nh(
M-!un
vo-ra
NKK-HUST
Bus dja chi
! Chc nng: vn chuyn dja chi d xc
djnh ngn nh hay cng vo-ra
! rng bus dja chi: cho bit s luong
ngn nh ti da duoc dnh dja chi.
! N bit: A
N-1
, A
N-2
, ... A
2
, A
1
, A
0

# c th dnh dja chi ti da cho 2
N
ngn nh
(khng gian dja chi b nh)
! V du:
! B x l Pentium c bus dja chi 32 bit
# c kh nng dnh dja chi cho 2
32
bytes nh
(4GBytes) (ngn nh t chc theo byte)
NKK-HUST
Bus d liu
! Chc nng:
! vn chuyn lnh t b nh dn CPU
! vn chuyn d liu gia CPU, m dun nh,
m dun vo-ra vi nhau
! rng bus d liu: Xc djnh s bit d
liu c th duoc trao di dng thi.
! M bit: D
M-1
, D
M-2
, ... D
2
, D
1
, D
0
! M thung l 8, 16, 32, 64,128 bit.
! V du: Cc b x l Pentium c bus d
liu 64 bit
NKK-HUST
Bus diu khin
! Chc nng: vn chuyn cc tn hiu
diu khin
! Cc loai tn hiu diu khin:
! Cc tn hiu diu khin doc/ghi
! Cc tn hiu diu khin ngt
! Cc tn hiu diu khin bus
NKK-HUST
Mt s tn hiu diu khin din hnh
! Cc tn hiu (pht ra t CPU) diu khin
doc-ghi:
! Memory Read (MEMR): diu khin doc d liu
t mt ngn nh c dja chi xc djnh ln bus d
liu.
! Memory Write (MEMW): diu khin ghi d liu
c sn trn bus d liu dn mt ngn nh c dja
chi xc djnh.
! I/O Read (IOR): diu khin doc d liu t mt
cng vo-ra c dja chi xc djnh ln bus d liu.
! I/O Write (IOW): diu khin ghi d liu c sn
trn bus d liu ra mt cng c dja chi xc djnh.
NKK-HUST
Mt s tn hiu diu khin din hnh (tip)
! Cc tn hiu diu khin ngt:
! Interrupt Request (INTR): Tn hiu t b diu khin
vo-ra gi dn yu cu ngt CPU d trao di vo-
ra. Tn hiu INTR c th bj che.
! Interrupt Acknowledge (INTA): Tn hiu pht ra t
CPU bo cho b diu khin vo-ra bit CPU chp
nhn ngt d trao di vo-ra.
! Non Maskable Interrupt (NMI): tn hiu ngt khng
che duoc gi dn ngt CPU.
! Reset: Tn hiu t bn ngoi gi dn CPU v cc
thnh phn khc d khi dng lai my tnh.
NKK-HUST
Mt s tn hiu diu khin din hnh (tip)
! Cc tn hiu diu khin bus:
! Bus Request (BRQ) hay l Hold: Tn hiu t
m-dun diu khin vo-ra gi dn yu cu
CPU chuyn nhuong quyn s dung bus.
! Bus Grant (BGT) hay l Hold Acknowledge
(HLDA): Tn hiu pht ra t CPU chp nhn
chuyn nhuong quyn s dung bus.
! Lock/ Unlock: Tn hiu c%m/cho-php xin
chuyn nhuong bus
NKK-HUST
c dim ca cu trc don bus
! Bus h thng chi phuc vu duoc mt yu cu
trao di d liu tai mt thi dim
! Bus h thng phi c tc d bng tc d bus
ca m-dun nhanh nht trong h thng
! Bus h thng phu thuc vo cu trc bus (cc
tn hiu) ca b x l " cc m-dun nh v
cc m-dun vo-ra cng phu thuc vo b x
l.
! Khc phuc: phn cp bus " cu trc da bus
NKK-HUST
3. Phn cp bus trong my tnh
! T chc thnh nhiu bus trong h thng
my tnh
! Cho cc thnh phn khc nhau:
! Bus ca b x l
! Bus ca b nh chnh
! Cc bus vo-ra
! Cc bus khc nhau v tc d
! Bus b nh chnh v cc bus vo-ra
khng phu thuc vo b x l cu th.
NKK-HUST
Mt s bus din hnh trong my tnh
! Bus ca b x l: c tc d nhanh nht
! Bus ca b nh chnh (ni ghp vi cc m-dun
RAM)
! PCI Express bus (Peripheral Component
Interconnect): ni ghp vi cc thit bj ngoai vi c
tc d trao di d liu nhanh.
! SATA (Serial Advanced Technology Attachment):
Bus kt ni vi da cng hoc da CD/DVD
! USB (Universal Serial Bus): Bus ni tip da nng
NKK-HUST
V du bus trong my tnh
NKK-HUST
V du bus trong my tnh (tip)
NKK-HUST
V du v bo mach chnh
NKK-HUST
V du bo mach chnh trong my tnh d bn
NKK-HUST
Ht chuong 3
NKK-HUST
Kin trc my tnh
Ch!"ng 4
S) H3C MY TNH
Nguy!n Kim Khnh
NKK-HUST
Ni dung hoc phn
Chuong 6. B x l

NKK-HUST
4.1. Biu din s nguyn
4.2. Php cng v php tr s nguyn
4.3. Php nhn v php chia s nguyn
4.4. S du phy dng
N2i dung ch!"ng 4
NKK-HUST
4.1. Biu din s nguyn
! S nguyn khng du (Unsigned Integer)
! S nguyn c du (Signed Integer)
NKK-HUST
1. Biu din s nguyn khng du
Gi trj ca A duoc tnh nhu sau:
i
n
i
i
a A 2
1
0
!
"
=
=
! Nguyn tc tng qut: Dng n bit biu din s
nguyn khng du A:
0 1 2 2 1
a a a ... a a
n n ! !
Di biu din ca A: t 0 dn 2
n
1
NKK-HUST
Cc v du
! V du 1. Biu din cc s nguyn khng du
sau dy bng 8-bit:
A = 41 ; B = 150
Gii:
A = 41 = 32 + 8 + 1 = 2
5
+ 2
3
+ 2
0

41 = 0010 1001

B = 150 = 128 + 16 + 4 + 2 = 2
7
+ 2
4
+ 2
2
+ 2
1

150 = 1001 0110
NKK-HUST
Cc v du (tip)
! V du 2. Cho cc s nguyn khng du M, N
duoc biu din bng 8-bit nhu sau:
! M = 0001 0010
! N = 1011 1001
Xc djnh gi trj ca chng ?
Gii:
! M = 0001 0010 = 2
4
+ 2
1
= 16 +2 = 18
! N = 1011 1001 = 2
7
+ 2
5
+ 2
4
+ 2
3
+ 2
0

= 128 + 32 + 16 + 8 + 1 = 185

NKK-HUST
Vi n = 8 bit
0000 0000 = 0
0000 0001 = 1
0000 0010 = 2
0000 0011 = 3
...
1111 1111 = 255

Biu din duoc cc gi trj t 0 dn 255
Ch :
1111 1111
+ 0000 0001
1 0000 0000
Vy: 255 + 1 = 0 ?
" do trn nh ra
ngoi
NKK-HUST
Truc s hoc vi n = 8 bit
Truc s hoc:
Truc s hoc my tnh:
! " # $ "%%
!
"
#
$
"%%
"%&
NKK-HUST
Vi n = 16 bit, 32 bit, 64 bit
! n= 16 bit: di biu din t 0 dn 65535 (2
16
1)
! 0000 0000 0000 0000 = 0
! ...
! 0000 0000 1111 1111 = 255
! 0000 0001 0000 0000 = 256
! ...
! 1111 1111 1111 1111 = 65535

! n= 32 bit: di biu din t 0 dn 2
32
- 1
! n= 64 bit: di biu din t 0 dn 2
64
- 1
NKK-HUST
2. Biu din s nguyn c du
S b chn v S b mui
! Cho mt s thp phn A duoc biu din
bng n ch s thp phn, ta c:
! S b chn ca A = (10
n
-1) A
! S b mui ca A = 10
n
A
! S b mui ca A = (S b chn ca A) +1
NKK-HUST
S b chn v S b mui (tip)
! V du: vi n=4, cho A = 3265
! S b chn ca A:
9999 (10
4
-1)
- 3265 (A)
6734
! S b mui ca A:
10000 (10
4
)
- 3265 (A)
6735
NKK-HUST
S b mt v S b hai
! jnh ngha: Cho mt s nhj phn A
duoc biu din bng n bit, ta c:
! S b mt ca A = (2
n
-1) A
! S b hai ca A = 2
n
A
! S b hai ca A = (S b mt ca A) +1
NKK-HUST
S b mt v S b hai (tip)
V du: vi n = 8 bit, cho A = 0010 0101
! S b mt ca A duoc tnh nhu sau:
1111 1111 (2
8
-1)
- 0010 0101 (A)
1101 1010
" do cc bit ca A
! S b hai ca A duoc tnh nhu sau:
1 0000 0000 (2
8
)
- 0010 0101 (A)
1101 1011
" thuc hin kh khn
NKK-HUST
Quy tc tm S b mt v S b hai
! S b mt ca A = do gi trj cc bit ca A
! (S b hai ca A) = (S b mt ca A) + 1
! V du:
! Cho A = 0010 0101
! S b mt = 1101 1010
+ 1
! S b hai = 1101 1011
! Nhn xt:
A = 0010 0101
S b hai = + 1101 1011
1 0000 0000 = 0
(b qua bit nh ra ngoi)
" S b hai ca A = -A
NKK-HUST
Biu din s nguyn c du bng m b hai
! Vi A l s duong: bit a
n-1
= 0, cc bit cn lai
biu din d ln nhu s khng du
! Vi A l s m: duoc biu din bng s b hai
ca s duong tuong ng, v vy bit a
n-1
= 1

0 1 2 2 1
a a a ... a a
n n ! !
Nguyn tc tng qut: Dng n bit biu din s
nguyn c du A:
NKK-HUST
Biu din s duong

0 1 2 2 n
a a a ... a 0
!
i
n
i
i
a A 2
2
0
!
"
=
=
! Gi trj ca s duong A:

! Dang tng qut ca s duong A:
! Di biu din cho s duong: 0 dn 2
n-1
-1

NKK-HUST
Biu din s m
0 1 2 2 n
a a a ... a 1
!
! Dang tng qut ca s m A:
i
n
i
i
n
a A 2 2
2
0
1
!
"
=
"
+ " =
! Gi trj ca s m A:

! Di biu din cho s m: -1 dn -2
n-1

NKK-HUST
Biu din tng qut cho s nguyn c du
0 1 2 2 1
a a a ... a a
n n ! !
! Dang tng qut ca s nguyn A:
i
n
i
i
n
n
a a A 2 2
2
0
1
1 !
"
=
"
"
+ " =
! Gi trj ca A duoc xc djnh nhu sau:

! Di biu din: t -(2
n-1
) dn +(2
n-1
-1)
NKK-HUST
Cc v du
! V du 1. Biu din cc s nguyn c du sau
dy bng 8-bit:
A = +58 ; B = -80
Gii:
A = +58 = 0011 1010

B = -80
Ta c: + 80 = 0101 0000
S b mt = 1010 1111
+ 1
S b hai = 1011 0000

Vy: B = -80 = 1011 0000
NKK-HUST
Cc v du
! V du 2. Hy xc djnh gi trj ca cc s nguyn
c du duoc biu din dui dy:
! P = 0110 0010
! Q = 1101 1011
Gii:
! P = 0110 0010 = 64+32+2 = +98
! Q = 1101 1011 = -128+64+16+8+2+1 = -37
NKK-HUST
Vi n = 8 bit
0000 0000 = 0
0000 0001 = +1
0000 0010 = +2
0000 0011 = +3
...
0111 1111 = +127
1000 0000 = - 128
1000 0001 = - 127
...
1111 1110 = -2
1111 1111 = -1

Biu din duoc cc gi trj t -128 dn +127
Ch :
+127 + 1 = -128
(-128)+(-1) = +127
" do trn xy ra
NKK-HUST
Truc s hoc s nguyn c du vi n = 8 bit
! Truc s hoc:
! Truc s hoc my tnh:
! " # $# %#"&
$#"'
$"
!
"#
"$
"%
&$
&#
"$#' &$#(
&%
NKK-HUST
Vi n = 16 bit, 32 bit, 64 bit
! Vi n=16bit: biu din t -32768 dn +32767
! 0000 0000 0000 0000 = 0
! 0000 0000 0000 0001 = +1
! ...
! 0111 1111 1111 1111 = +32767
! 1000 0000 0000 0000 = -32768
! ...
! 1111 1111 1111 1111 = -1

! Vi n=32bit: biu din t -2
31
dn 2
31
-1
! Vi n=64bit: biu din t -2
63
dn 2
63
-1
NKK-HUST
Chuyn di d liu t 8 bit thnh 16 bit
! i vi s duong:
+19 = 0001 0011 (8bit)
+19 = 0000 0000 0001 0011 (16bit)
" thm 8 bit 0 bn tri

! i vi s m:
- 19 = 1110 1101 (8bit)
- 19 = 1111 1111 1110 1101 (16bit)
" thm 8 bit 1 bn tri
NKK-HUST
B! c!ng n-bit
X Y
S
Cin
Cout
n bit n bit
n bit
1. Php cng s nguyn khng du
B cng n-bit
4.2. Thuc hin php cng/tr vi s nguyn
NKK-HUST
Nguyn tc cng s nguyn khng du
Khi cng hai s nguyn khng du n-bit,
kt qu nhn duoc l n-bit:
! Nu C
out
=0 " nhn duoc kt qu dng.
! Nu C
out
=1 " nhn duoc kt qu sai,
do trn nh ra ngoi (Carry Out).
! Trn nh ra ngoi khi: tng > (2
n
1)
NKK-HUST
V du cng s nguyn khng du
! 57 = 0011 1001
+ 34 = + 0010 0010
91 0101 1011 = 64+16+8+2+1=91 " dng

! 209 = 1101 0001
+ 73 = + 0100 1001
282 1 0001 1010
0001 1010 = 16+8+2=26 " sai
" c trn nh ra ngoi (C
out
=1)

c kt qu dng ta thuc hin cng theo 16-bit:
209 = 0000 0000 1101 0001
+ 73 = + 0000 0000 0100 1001
0000 0001 0001 1010 = 256+16+8+2 = 282
NKK-HUST
2. Php do du
! Ta c:
+ 37 = 0010 0101
b mt = 1101 1010
+ 1
b hai = 1101 1011 = -37

! Ly b hai ca s m:
- 37 = 1101 1011
b mt = 0010 0100
+ 1
b hai = 0010 0101 = +37
! Kt lun: Php &'o d%u s( nguyn trong my tnh
th)c ch%t l l%y b hai
NKK-HUST
3. Cng s nguyn c du
Khi cng hai s nguyn c du n-bit, kt qu
nhn duoc l n-bit v khng cn quan tm dn
bit C
out
.

! Cng hai s khc du: kt qu lun lun dng.
! Cng hai s cng du:
! nu du kt qu cng du vi cc s hang th kt
qu l dng.
! nu kt qu c du nguoc lai, khi d c trn xy ra
(Overflow) v kt qu bj sai.
! Trn xy ra khi tng nm ngoi di biu din:
[ -(2
n-1
),+(2
n-1
-1)]
NKK-HUST
V du cng s nguyn c du khng trn
! ( + 70) = 0100 0110
+ ( + 42) = 0010 1010
+ 112 0111 0000 = +112

! (+ 97) = 0110 0001
+ (- 52) = 1100 1100 (+52=0011 0100)
+ 45 1 0010 1101 = +45

! ( - 90) = 1010 0110 (+90=0101 1010)
+ ( +36) = 0010 0100
- 54 1100 1010 = - 54

! ( - 74) = 1011 0110 (+74=0100 1010)
+( - 30) = 1110 0010 (+30=0001 1110)
-104 1 1001 1000 = -104
NKK-HUST
V du cng s nguyn c du bj trn
! ( + 75) = 0100 1011
+( + 82) = 0101 0010
+157 1001 1101
= - 128+16+8+4+1= -99 " sai

! ( - 104) = 1001 1000 (+104=0110 1000)
+ ( - 43) = 1101 0101 (+ 43 =0010 1011)
- 147 1 0110 1101
= 64+32+8+4+1= +109 " sai
! C hai v du du trn v tng nm ngoi di
biu din [-128, +127]
NKK-HUST
4. Nguyn tc thuc hin php tr
! Php tr hai s nguyn: X-Y = X+(-Y)
! Nguyn tc: Ly b hai ca Y d duoc Y,
ri cng vi X
B! c!ng n-bit
Y X
S= X-Y
B hai
n-bit n-bit
n-bit
NKK-HUST
4.3. Php nhn v php chia s nguyn
1011 S bj nhn (11)
x 1101 S nhn (13)
1011
0000 Cc tch ring phn
1011
1011
10001111 Tch (143)
1. Nhn s nguyn khng du
NKK-HUST
Nhn s nguyn khng du (tip)
! Cc tch ring phn duoc xc djnh nhu sau:
! Nu bit ca s nhn bng 0 " tch ring phn bng 0.
! Nu bit ca s nhn bng 1 " tch ring phn bng s
bj nhn.
! Tch ring phn tip theo duoc djch tri mt bit so vi
tch ring phn truc d.
! Tch bng tng cc tch ring phn
! Nhn hai s nguyn n-bit, tch c d di 2n bit
(khng bao gi trn).
NKK-HUST
B nhn s nguyn khng du
B! c!ng n-bit
B! logic "i#u khi$n
c!ng v d%ch
!i"u khi#n
d$ch ph%i
!i"u
khi#n
c&ng
S& nhn
Mn-1 Mn-2 M0 M1 . . .
An-1 An-2 A0 A1 . . . Qn-1 Qn-2 Q0 Q1 . . . C
S& b% nhn
NKK-HUST
Luu d nhn s nguyn khng du
B!t "#u
C !0; A !0
M ! S$ b% nhn
Q ! S$ nhn
B& "'m !n
B& "'m = 0 ?
K't thc
Yes No
Q0 = 1 ?
C,A ! A+M
D%ch ph(i C,A,Q
B& "'m !B& "'m-1
Yes
No
Tch trong AQ
NKK-HUST
V du nhn s nguyn khng du
! S bj nhn M = 1011 (11)
! S nhn Q = 1101 (13)
! Tch = 1000 1111 (143)

C A Q
! 0 0000 1101 Cc gi trj khi du
+ 1011
0 1011 1101 A # A + M
! 0 0101 1110 Djch phi
! 0 0010 1111 Djch phi
+ 1011
0 1101 1111 A # A + M
! 0 0110 1111 Djch phi
+ 1011
1 0001 1111 A # A + M
! 0 1000 1111 Djch phi
NKK-HUST
V du nhn s nguyn khng du
! S bj nhn M = 0010 (2)
! S nhn Q = 0011 (3)
! Tch = 0000 0110 (6)

C A Q
! 0 0000 0011 Cc gi trj khi du
+ 0010
0 0010 0011 A # A + M
! 0 0001 0001 Djch phi
+ 0010
0 0011 0001
! 0 0001 1000 Djch phi
! 0 0000 1100 Djch phi
! 0 0000 0110 Djch phi
NKK-HUST
2. Nhn s nguyn c du
! S dung thut gii nhn khng du
! S dung thut gii Booth
NKK-HUST
S dung thut gii nhn khng du
! Buc 1. Chuyn di s bj nhn v s
nhn thnh s duong tuong ng
! Buc 2. Nhn hai s duong bng thut
gii nhn s nguyn khng du, duoc
tch ca hai s duong.
! Buc 3. Hiu chinh du ca tch:
! Nu hai tha s ban du cng du th gi
nguyn kt qu buc 2.
! Nu hai tha s ban du l khc du th do
du kt qu ca buc 2 (ly b hai).
NKK-HUST
Thut gii Booth (tham kho COA-[1])
10.3 / INTEGER ARITHMETIC 335
as the twos complement value -7, then each partial product must be a negative
twos complement number of 2n (8) bits, as shown in Figure 10.11b. Note that this is
accomplished by padding out each partial product to the left with binary 1s.
If the multiplier is negative, straightforward multiplication also will not work.
The reason is that the bits of the multiplier no longer correspond to the shifts or
multiplications that must take place. For example, the 4-bit decimal number -3 is
written 1101 in twos complement. If we simply took partial products based on each
bit position, we would have the following correspondence:
1101 g -(1 * 2
3
+ 1 * 2
2
+ 0 * 2
1
+ 1 * 2
0
) = -(2
3
+ 2
2
+ 2
0
)
In fact, what is desired is -(2
1
+ 2
0
). So this multiplier cannot be used directly in
the manner we have been describing.
There are a number of ways out of this dilemma. One would be to convert
both multiplier and multiplicand to positive numbers, perform the multiplication,
and then take the twos complement of the result if and only if the sign of the two
original numbers differed. Implementers have preferred to use techniques that
do not require this final transformation step. One of the most common of these is
Booths algorithm. This algorithm also has the benefit of speeding up the multipli-
cation process, relative to a more straightforward approach.
Booths algorithm is depicted in Figure 10.12 and can be described as follows.
As before, the multiplier and multiplicand are placed in the Q and M registers,
START
END
Yes No
10 01
11
00
A 0, Q1 0
M Multiplicand
Q Multiplier
Count n
Arithmetic shift
Right: A, Q, Q1
Count Count 1
A A M A A M
Q0, Q1
Count 0?
Figure 10.12 Booths Algorithm for Twos
Complement Multiplication
NKK-HUST
3. Chia s nguyn khng du
S bj chia 10010011 1011 S chia
- 1011 00001101 Thuong
001110
- 1011
001111
- 1011
100 Phn du
NKK-HUST
B chia s nguyn khng du
B! c!ng/tr" n-bit
B! logic #i$u khi%n
c!ng/tr" v d&ch
!i"u khi#n
d$ch tri
!i"u
khi#n
c%ng/tr&
S' b& chia Q
Mn-1 Mn-2 M0 M1 . . .
An-1 An-2 A0 A1 . . . Qn-1 Qn-2 Q0 Q1 . . .
S' chia M
NKK-HUST
Luu d chia s nguyn khng du
B!t "#u
A ! 0
M !S$ chia
Q !S$ b% chia
B& "'m ! n
B& "'m = 0 ?
K't thc
Yes No
A < 0 ?
Q0 !0
A ! A + M
B& "'m!B& "'m-1
Yes
No
Q0 !1
D%ch tri A,Q
A !A - M
Th()ng * Q
S$ d( * A
NKK-HUST
4. Chia s nguyn c du
! Buc 1. Chuyn di s bj chia v s chia v thnh s
duong tuong ng.
! Buc 2. S dung thut gii chia s nguyn khng du d
chia hai s duong, kt qu nhn duoc l thuong Q v
phn du R du l duong
! Buc 3. Hiu chinh du ca kt qu nhu sau:
(L!u *: php do du thuc cht l thuc hin php ly b hai)
S/ b+ chia S/ chia Th!"ng S/ d!
duong duong gi nguyn gi nguyn
duong m do du gi nguyn
m duong do du do du
m m gi nguyn do du
NKK-HUST
4.4. S du phy dng
1. Nguyn tc chung
! Floating Point Number " biu din cho s
thuc
! Tng qut: mt s thuc X duoc biu din
theo kiu s du phy dng nhu sau:
X = M * R
E
! M l phn djnh trj (Mantissa),
! R l co s (Radix),
! E l phn m (Exponent).
NKK-HUST
2. Chun IEEE754-2008
! Co s R = 2
! Cc dang:
! Dang 32-bit

! Dang 64-bit

! Dang 128-bit
346 CHAPTER 10 / COMPUTER ARITHMETIC
is implementation dependent, but the standard places certain constraints on the
length of the exponent and significand. These formats are arithmetic format types
but not interchange format types. The extended formats are to be used for inter-
mediate calculations. With their greater precision, the extended formats lessen the
Table 10.3 IEEE 754 Format Parameters
Parameter
Format
Binary32 Binary64 Binary128
Storage width (bits) 32 64 128
Exponent width (bits) 8 11 15
Exponent bias 127 1023 16383
Maximum exponent 127 1023 16383
Minimum exponent -126 -1022 -16382
Approx normal number range
(base 10)
10
-38
, 10
+38
10
-308
, 10
+308
10
-4932
, 10
+4932
Trailing significand width (bits)* 23 52 112
Number of exponents 254 2046 32766
Number of fractions 2
23
2
52
2
112
Number of values 1.98 * 2
31
1.99 * 2
63
1.99 * 2
128
Smallest positive normal number 2
-126
2
-1022
2
-16362
Largest positive normal number 2
128
- 2
104
2
1024
- 2
971
2
16384
- 2
16271
Smallest subnormal magnitude 2
-149
2
-1074
2
-16494
Note: *not including implied bit and not including sign bit
Trailing significand field
(c) Binary128 format
Biased
exponent
Trailing significand field
(b) Binary64 format
8 bits
Sign
bit
Trailing
significand field
(a) Binary32 format
Biased
exponent
23 bits
11 bits 52 bits
15 bits 112 bits
Sign
bit
Biased
exponent
Sign
bit
Figure 10.21 IEEE 754 Formats
NKK-HUST
Dang 32 bit
! S l bit du:
! S = 0 " s duong
! S = 1 " s m
! e (8 bit) l m excess-127 ca phn m E:
! e = E+127 " E = e 127
! gi trj 127 goi l l d lch (bias)
! m (23 bit) l phn l ca phn djnh trj M:
! M = 1.m
! Cng thc xc djnh gi trj ca s thuc:
X = (-1)
S
*
1.m
*
2
e-127

S m e
!" $$ % !% $!
NKK-HUST
V du 1
Xc djnh gi trj ca s thuc duoc biu din bng
32-bit nhu sau:
! 1100 0001 0101 0110 0000 0000 0000 0000
! S = 1 " s m
! e = 1000 0010
2
= 130 " E = 130-127=3
Vy
X = -1.10101100
*
2
3
= -1101.011 = -13.375

! 0011 1111 1000 0000 0000 0000 0000 0000 = ?
= +1.0
NKK-HUST
V du 2
Biu din s thuc X= 83.75 v dang s du phy
dng IEEE754 32-bit
Gii:
! X = 83.75
(10)
= 1010011.11
(2)
= 1.01001111 x 2
6

! Ta c:
! S = 0 v dy l s duong
! E = e-127 = 6 " e = 127 + 6 = 133
(10)
= 1000 0101
(2)

! Vy:
X = 0100 0010 1010 0111 1000 0000 0000 0000

NKK-HUST
V du 3
Biu din s thuc X= -0,2 v dang s du phy
dng IEEE754 32-bit
Gii:
! X = -0,2
(10)
= - 0.00110011...0011...
(2)
=
= - 1.100110011..0011... x 2
-3
! Ta c:
! S = 1 v dy l s m
! E = e-127 = -3 " e = 127 -3 = 124
(10)
= 0111 1100
(2)

! Vy:
X = 1011 1110 0100 1100 1100 1100 1100 1100
NKK-HUST
Bi tp
Biu din cc s thuc sau dy v dang
s du phy dng IEEE754 32-bit:
X = - 27.0625; Y = 1/32
NKK-HUST
Cc qui uc dc bit
! Cc bit ca e bng 0, cc bit ca m bng 0, th X = 0
x000 0000 0000 0000 0000 0000 0000 0000 " X = 0
! Cc bit ca e bng 1, cc bit ca m bng 0, th X = $
x111 1111 1000 0000 0000 0000 0000 0000 " X = $

! Cc bit ca e bng 1, cn m c t nht mt bit bng 1, th
n khng biu din cho s no c (NaN - not a number)
NKK-HUST
Di gi trj biu din
! 2
-127
dn 2
+127

! 10
-38
dn 10
+38

! "#
$%#&
$#
$%#&
$#
"%#&
"#
"%#&
NKK-HUST
Dang 64-bit
! S l bit du
! e (11 bit): m excess-1023 ca phn
m E " E = e 1023
! m (52 bit): phn l ca phn djnh trj M
! Gi trj s thuc:
X = (-1)
S
*
1.m
*
2
e-1023
! Di gi trj biu din: 10
-308
dn 10
+308

NKK-HUST
Dang 128-bit
! S l bit du
! e (15 bit): m excess-16383 ca phn
m E " E = e 16383
! m (112 bit): phn l ca phn djnh trj M
! Gi trj s thuc:
X = (-1)
S
*
1.m
*
2
e-16383
! Di gi trj biu din: 10
-4932
dn 10
+4932

NKK-HUST
3. Thuc hin php ton s du phy dng
! X1 = M1
*
R
E1

! X2 = M2
*
R
E2

! Ta c
! X1
*
X2 = (M1
*
M2)
*
R
E1+E2
! X1 / X2 = (M1 / M2)
*
R
E1-E2
! X1 X2 = (M1
*
R
E1-E2
M2)
*
R
E2
, vi E2 % E1
NKK-HUST
Cc kh nng trn s
! Trn trn s m (Exponent Overflow): m
duong vuot ra khi gi trj cuc dai ca s m
duong c th. (" )
! Trn dui s m (Exponent Underflow): m m
vuot ra khi gi trj cuc dai ca s m m c th
(" 0).
! Trn trn phn djnh trj (Mantissa Overflow):
cng hai phn djnh trj c cng du, kt qu bj
nh ra ngoi bit cao nht.
! Trn dui phn djnh trj (Mantissa Underflow):
Khi hiu chinh phn djnh trj, cc s bj mt bn
phi phn djnh trj.
NKK-HUST
Php cng v php tr
! Kim tra cc s hang c bng 0 hay
khng
! Hiu chinh phn djnh trj
! Cng hoc tr phn djnh trj
! Chun ho kt qu
NKK-HUST
Thut ton cng/tr s du phy dng
TR!
D"ch ph#i
ph$n %"nh tr"
Ph$n m&
b" trn?
Y
N
X = 0 ?
C't s( kia
vo Z
)*i d'u c+a Y
T,ng ph$n m&
nh- h.n
Z !Y
C/NG Y = 0 ?
Z ! X
TR0 V1
Ph$n m&
b2ng nhau?
Y
N
Y = 0 ?
TR0 V1
C3ng c d'u
ph$n %"nh tr"
%"nh tr" = 0? Z ! 0
TR0 V1
N
N
Y
Y
%"nh tr" b"
trn?
N
Y
D"ch ph#i
ph$n %"nh tr"
T,ng ph$n m&
Y
Bo trn
TR0 V1
N
Ph$n m& b"
trn d45i?
N
K6t qu#
chu7n ha?
Y
D"ch ph#i
ph$n %"nh tr"
Gi#m ph$n m&
Y
Lm trn
k6t qu#
TR0 V1
Bo trn d45i
TR0 V1
N
Y
N
NKK-HUST
Thut ton nhn s du phy dng
NHN
Thng bo
trn trn
Y
N
X = 0 ?
Lm trn
Tr! cho
"# l$ch
Z ! 0
Y = 0 ? C#ng ph%n m&
TR' V(
Y
N
Trn d)*i
ph%n m&?
TR' V(
Thng bo
trn d)*i
TR' V(
N
N
Trn trn
ph%n m&?
Nhn ph%n
"+nh tr+
Chu,n ha
Y
Y
NKK-HUST
Thut ton chia s du phy dng
CHIA
Thng bo
trn trn
Y
N
X = 0 ?
Lm trn
Cng thm
!" l#ch Z ! 0
Y = 0 ? Tr$ ph%n m&
TR' V(
Y
N
Trn d)*i
ph%n m&?
TR' V(
Thng bo
trn d)*i
TR' V(
N
N
Trn trn
ph%n m&?
Chia ph%n
!+nh tr+
Chu,n ha
Y
Y
Z ! !
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H%t ch!"ng 4
NKK-HUST
Kin trc my tnh
Ch!"ng 5
KI4N TRC T5P L$NH
(Instruction Set Architecture)
Nguy!n Kim Khnh
NKK-HUST
Ni dung hoc phn
Chuong 6. B x l

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5.1. Gii thiu chung v kin trc tp lnh
5.2. Kin trc tp lnh MIPS
5.3. Kin trc tp lnh Intel x86 *
Ni dung ca chuong 5
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5.1. Gii thiu chung v kin trc tp lnh
PC: Program Counter
IR: Instruction Register
1. M hnh lp trnh ca my tnh
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Tp thanh ghi
! Cha cc thng tin (d liu, dja chi, trang
thi) cho hoat dng diu khin v x l
d liu ca CPU thi dim hin tai
! uoc coi l mc du tin ca h thng
nh
! S luong thanh ghi nhiu " tng hiu
nng ca CPU
! C hai loai thanh ghi:
! Cc thanh ghi lp trnh duoc
! Cc thanh ghi khng lp trnh duoc

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Mt s thanh ghi din hnh
! B dm chuong trnh PC (Program Counter)
! Con tr d liu DP (Data Pointer)
! Con tr ngn xp SP (Stack Pointer)
! Thanh ghi co s v Thanh ghi chi s
(Base Register & Index Register)
! Cc thanh ghi d liu
! Thanh ghi trang thi
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B dm chuong trnh PC
! Cn duoc goi l con tr lnh
IP (Instruction Pointer)
! Gi dja chi ca lnh tip theo
s duoc nhn vo.
! Sau khi mt lnh duoc nhn
vo, ni dung PC tu dng
tng d tr sang lnh k tip.
! PC tng bao nhiu?
l!nh
l!nh
l!nh k" ti"p
l!nh s# $%&c nh'n
l!nh
l!nh
l!nh
PC
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Thanh ghi con tr d liu
! Cha dja chi ca
ngn nh d liu m
CPU mun truy nhp
d! li"u
d! li"u
d! li"u
d! li"u
d! li"u c#n $%c/ghi
d! li"u
d! li"u
d! li"u
DP
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Ngn xp (Stack)
! Ngn xp l vng nh c cu trc LIFO
(Last In - First Out " vo sau ra truc)
! Ngn xp thung dng d phuc vu cho
chuong trnh con
! y ngn xp l mt ngn nh xc djnh
! inh ngn xp l thng tin nm vj tr
trn cng trong ngn xp
! inh ngn xp c th bj thay di
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Con tr ngn xp SP (Stack Pointer)
! Cha dja chi ca ngn nh dinh
ngn xp
! Khi ct mt thng tin vo ngn
xp:
! Ni dung ca SP gim
! Thng tin duoc ct vo ngn nh
duoc tr bi SP
! Khi ly mt thng tin ra khi
ngn xp:
! Thng tin duoc doc t ngn nh
duoc tr bi SP
! Ni dung ca SP tng
! Khi ngn xp rng, SP tr vo
dy
!y ng"n x#p

!$nh ng"n x#p SP
chi%u
!&a
ch$
t"ng
d'n
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Thanh ghi co s v thanh ghi chi s
! truy nhp mt ngn nh c
th s dung hai tham s:
! ja chi co s (base address)
! Phn djch chuyn dja chi (offset)
! ja chi ca ngn nh cn truy
nhp = dja chi co s + offset
! C th s dung cc thanh ghi
d qun l cc tham s ny:
! Thanh ghi co s: cha dja chi co
s
! Thanh ghi chi s: cha phn djch
chuyn dja chi

Ng!n nh" c#n truy nh$p

Ng!n nh" c% s&

'(a ch) c% s&
Offset
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Cc thanh ghi d liu
! Cha cc d liu tam thi hoc cc kt
qu trung gian
! Cn c nhiu thanh ghi d liu
! Cc thanh ghi s nguyn: 8, 16, 32, 64 bit
! Cc thanh ghi s du phy dng
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Thanh ghi trang thi (Status Register)
! uoc s dung trn mt s kin trc cu th
! Cn goi l thanh ghi c (Flag Register)
! Cha cc thng tin trang thi ca CPU
! Cc c php ton: bo hiu trang thi ca kt
qu php ton
! Cc c diu khin: biu thj trang thi diu
khin ca CPU
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2. Th tu luu tr cc byte trong b nh chnh
! B nh chnh thung dnh dja chi theo
byte
! Hai cch luu tr thng tin nhiu byte:
! u nh (Little-endian): Byte c ngha
thp duoc luu tr ngn nh c dja chi
nh, byte c ngha cao duoc luu tr
ngn nh c dja chi ln.
! u to (Big-endian): Byte c ngha cao
duoc luu tr ngn nh c dja chi nh,
byte c ngha thp duoc luu tr ngn
nh c dja chi ln.
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V du luu tr d liu 32-bit
1A 2B 3C 4D
4D
1A
2B
3C
little-endian
3000
3003
3002
3001
1A
4D
3C
2B
big-endian
3000
3003
3002
3001
0001 1010 0010 1011 0011 1100 0100 1101
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Luu tr ca cc b x l din hnh
! Intel x86: little-endian
! Motorola 680x0, MIPS, SunSPARC: big-endian
! Power PC, Itanium: bi-endian
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3. Gii thiu chung v tp lnh
! Mi b x l c mt tp lnh xc djnh
! Tp lnh thung c hng chuc dn hng
trm lnh
! Mi lnh l mt chui s nhj phn m b x
l hiu duoc d thuc hin mt thao tc xc
djnh.
! Cc lnh duoc m t bng cc k hiu goi
nh dang text " chnh l cc lnh ca hop
ng (assembly language)

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Cc thnh phn ca lnh my
! M thao tc (operation code " opcode): m
ha cho thao tc m b x l phi thuc hin
! ja chi ton hang: chi ra noi cha cc ton
hang m thao tc s tc dng
! Ton hang ngun (source operand): d liu vo ca
thao tc
! Ton hang dch (destination operand): d liu ra ca
thao tc
M thao tc !"a ch# c$a cc ton h%ng
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Cc kiu thao tc thng dung ca tp lnh
! Cc lnh chuyn d liu
! Cc lnh x l s hoc
! Cc lnh x l logic
! Cc lnh chuyn diu khin (r nhnh, nhy)
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jnh dja chi ton hang
! Ton hang ca lnh c th l:
! Mt gi trj cu th nm ngay trong lnh
! Ni dung ca thanh ghi
! Ni dung ca ngn nh hoc cng vo-ra
! Phuong php djnh dja chi (addressing
modes) l cch thc dja chi ha trong
trung dja chi ca lnh d xc djnh noi
cha ton hang
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Cc phuong php djnh dja chi thng dung
! jnh dja chi tc th
! jnh dja chi thanh ghi
! jnh dja chi truc tip
! jnh dja chi gin tip qua thanh ghi
! jnh dja chi djch chuyn
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jnh dja chi tc th
! Ton hang l hng s nm ngay trong lnh
! Chi c th l ton hang ngun
! V du:
ADD R1, 5 # R1$ R1+5
! Khng tham chiu b nh
! Truy nhp ton hang rt nhanh
! Di gi trj ca ton hang bj han ch
M thao tc Ton h!ng
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jnh dja chi thanh ghi
! Ton hang nm trong thanh ghi c
tn duoc chi ra trong lnh
! V du:
ADD R1, R2 # R1$ R1+R2
! S luong thanh ghi t " Trung dja
chi ton hang chi cn t bit
! Khng tham chiu b nh
! Truy nhp ton hang nhanh
! Tng s luong thanh ghi " hiu
qu hon
M thao tc Tn thanh ghi
T!p thanh ghi
Ton h"ng
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jnh dja chi truc tip
! Ton hang l ngn nh c dja chi
duoc cho truc tip trong lnh
! V du:
ADD R1, A #R1 $ R1 + (A)
! Cng ni dung thanh ghi R1 vi ni
dung ca ngn nh c dja chi l A
! Tm ton hang trong b nh dja
chi A
! CPU tham chiu b nh mt ln
d truy nhp d liu
M thao tc !"a ch#
B$ nh%
Ton h&ng
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jnh dja chi gin tip qua thanh ghi
! Ton hang nm ngn nh
c dja chi trong thanh ghi
! Trung dja chi ton hang cho
bit tn thanh ghi d
! Thanh ghi c th l ngm djnh
! Thanh ghi ny duoc goi l
thanh ghi con tr
! Vng nh c th duoc tham
chiu l ln (2
n
), (vi n l d
di ca thanh ghi)
T!p thanh ghi
B" nh#
$%a ch&
Ton h'ng
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jnh dja chi djch chuyn
! xc djnh ton hang,
Trung dja chi cha hai
thnh phn:
! Tn thanh ghi
! Hng s (offset)
! ja chi ca ton hang =
ni dung thanh ghi +
hng s
! Thanh ghi c th duoc
ngm djnh
T!p thanh ghi
B nh
"#a ch$ Ton h%ng
H&ng s'
+
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S luong dja chi ton hang trong lnh (1)
! Ba dja chi ton hang:
! 2 ton hang ngun, 1 ton hang dch
! Ph hop vi dang: c = a + b
! add r1, r2, r3 # r1 $ r2 + r3
! T lnh di v phi m ho dja chi cho c ba
ton hang
! uoc s dung trn cc b x l tin tin
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! Hai dja chi ton hang:
! Mt ton hang va l ton hang ngun va
l ton hang dch; ton hang cn lai l ton
hang ngun
! a = a + b
! add r1, r2 # r1 $ r1 + r2
! Gi trj c ca 1 ton hang ngun bj mt v
phi cha kt qu
! Rt gon d di t lnh
! Ph bin
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! Mt dja chi ton hang:
! Mt ton hang duoc chi ra trong lnh
! Mt ton hang l ngm djnh " thung l
thanh ghi (thanh cha accumulator)
! add r1 # Acc $ Acc + r1
! uoc s dung trn cc my cc th h
truc

NKK-HUST
! 0 dja chi ton hang:
! Cc ton hang du duoc ngm djnh
! S dung Stack
! V du:
push a
push b
add
pop c
c ngha l : c = a+b
! khng thng dung
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4. CISC v RISC
! CISC: Complex Instruction Set Computer:
! My tnh vi tp lnh phc tap
! Cc b x l truyn thng: Intel x86, Motorola
680x0
! RISC: Reduced Instruction Set Computer:
! My tnh vi tp lnh thu gon
! SunSPARC, Power PC, MIPS, ARM ...
! RISC di nghjch vi CISC
! Kin trc tp lnh tin tin
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Cc dc trung ca RISC
! S luong lnh t
! Hu ht cc lnh truy nhp ton hang cc
thanh ghi
! Truy nhp b nh bng cc lnh LOAD/STORE
! Thi gian thuc hin lnh l mt chu ky my
! Cc lnh c d di c djnh (32 bit)
! S luong dang lnh t (<=4)
! CPU c tp thanh ghi ln
! C t phuong php djnh dja chi ton hang(<=4)
! H tro cc thao tc ca ngn ng bc cao
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5.2. Ki%n trc t1p l6nh MIPS
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1. Gii thiu chung
! MIPS- Microprocessor without Interlocked
Pipeline Stages
! uoc pht trin dai hoc Stanford, sau d
duoc thuong mai ha bi Cng ty MIPS
Technologies
! Nm 2012: MIPS Technologies duoc bn cho
Imagination Technologies (imgtech.com)
! Kin trc RISC
! Chim thj phn ln trong cc sn phm nhng
! in hnh cho nhiu kin trc tp lnh hin dai
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2. Php ton s hoc v cc ton hang
! Cng v tr: 3 ton hang
! Hai ton hang ngun v mt ton hang
dch
add a, b, c # a $ b + c
! Tt c cc lnh s hoc c dang trn
! Ton hang c th l:
! Ni dung thanh ghi
! Ni dung ngn nh
! Hng s
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Ton hang thanh ghi
! Cc lnh s hoc s dung ton hang
thanh ghi
! MIPS c tp 32 thanh ghi 32-bit
! uoc s dung thung xuyn
! uoc dnh s t 0 dn 31 (dng 5 bit)
! D liu 32-bit duoc goi l word
! Chuong trnh djch Assembler dt tn:
! $t0, $t1, , $t9 cha cc gi trj tam thi
! $s0, $s1, , $s7 ct cc bin
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Tp thanh ghi ca MIPS
Tn thanh ghi S" hi#u thanh ghi Cng d$ng
$zero 0 the constant value 0
$at 1 assembler temporary
$v0-$v1 2-3 procedure return values
$a0-$a3 4-7 procedure arguments
$t0-$t7 8-15 temporaries
$s0-$s7 16-23 saved variables
$t8-$t9 24-25 more temporaries
$k0-$k1 26-27 OS temporaries
$gp 28 global pointer
$sp 29 stack pointer
$fp 30 frame pointer
$ra 31 procedure return address
245 Jan2014 Computer Architecture 245
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V du ton hang thanh ghi
! M C:
a = b + c;
d = a e;
! M hop ng:
add a,b,c
sub d,a,e

! M C:
f = (g + h) - (i + j);
! f, g, h, i, j nm $s0, $s1, $s2, $s3, $s4
! uoc djch thnh m MIPS:
add $t0, $s1, $s2 # $t0 $ $s1+$s2
add $t1, $s3, $s4 # $t1 $ $s3+$s4
sub $s0, $t0, $t1 # $s0 $ $t0-$t1
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Ton hang b nh
! B nh chnh duoc s dung luu tr cc d liu
! Bin v hung, mng, bn ghi, d liu dng
! Mun thuc hin php ton s hoc, cn phi:
! Nap (Load) cc gi trj t b nh vo cc thanh ghi
! Thuc hin php ton trn cc thanh ghj
! Luu (store) kt qu t thanh ghi ra b nh
! B nh duoc dnh dja chi theo byte
! Mi dja chi xc djnh vj tr ca mt byte nh
! Mi Word c d di 32 bit " dja chi ca cc
Word l bi ca 4
! MIPS luu tr theo kiu u to (Big Endian)
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V du ton hang b nh
! M C:
g = h + A[8];
! g $s1, h $s2, dja chi co s ca mng
A $s3
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
!"a ch# c$ s%
NKK-HUST
V du ton hang b nh
! M C:
g = h + A[8];
! g $s1, h $s2, dja chi co s ca mng
A $s3
! M MIPS:
! Chi s 8 yu cu phn djch chuyn (offset)
l 32 (chi s t 0) do 4 bytes/ word
lw $t0,32($s3) # load word A[8]
add $s1,$s2,$t0 # g = h+A[8]
offset
base register
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
!"a ch# c$ s%
NKK-HUST
V du ton hang b nh (tip)
! M C:
A[12] = h + A[8];
! h $s2, dja chi co s ca mng A nm $s3
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
!"a ch# c$ s%
NKK-HUST
V du ton hang b nh (tip)
! M C:
A[12] = h + A[8];
! h $s2, dja chi co s ca mng A nm $s3
! M MIPS:
lw $t0, 32($s3) #load word from A[8]
add $t0, $s2, $t0 #t0 = h + A[8]
sw $t0, 48($s3) #store word to A[12]
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
!"a ch# c$ s%
NKK-HUST
Thanh ghi vi B nh
! Truy nhp thanh ghi nhanh hon b nh
! Thao tc d liu trn b nh yu cu
nap (load) v luu (store).
! Cn thuc hin nhiu lnh hon
! Chuong trnh djch s dung cc thanh
ghi cho cc bin nhiu nht c th
! Chi s dung b nh cho cc bin t duoc
s dung
! Cn ti uu ha s dung thanh ghi
NKK-HUST
Ton hang tc th (immediate)
! D liu hng s duoc xc djnh ngay
trong lnh
addi $s3, $s3, 4 # $s3 $ $s3+4
! Khng c lnh tr (subi) vi gi trj tc
th
! S dung hng s m d thuc hin php tr
addi $s2, $s1, -1 # $s2 $ $s1-1
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Hng s Zero
! Thanh ghi 0 ca MIPS ($zero hay $0) lun
cha hng s 0
! Khng th thay di gi trj
! Hu ch cho mt s thao tc thng dung
! Chng han, chuyn d liu gia cc thanh ghi
add $t2, $s1, $zero # $t2 $ $s1
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3. M my
! Cc lnh duoc m ha dui dang nhj
phn duoc goi l m my
! Cc lnh ca MIPS:
! uoc m ha bng cc t lnh 32-bit
! C t dang lnh
! S hiu thanh ghi
! $t0 $t7 l cc thanh ghi 8 15
! $t8 $t9 l cc thanh ghi 24 25
! $s0 $s7 l cc thanh ghi 16 23
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Cc dang lnh ca MIPS
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Lnh dang R (Register)
! Cc trung ca lnh
! op: operation code (opcode): m thao tc
! rs: s hiu thanh ghi ngun th nht
! rt: s hiu thanh ghi ngun th hai
! rd: s hiu thanh ghi dch
! shamt (shift amount): s bit duoc djch
! funct: function code (extends opcode): m
hm (m thao tc m rng)
op rs rt rd shamt funct
6 bits 6 bits 5 bits 5 bits 5 bits 5 bits
NKK-HUST

V du dang lnh R
add $s0, $s1, $s2
sub $t0, $t3, $t5
H!p ng"
0 17 18 16 0 32
Gi tr! cc tr"#ng
0 11 13 8 0 34
000000 10001 10010 10000 00000 100000
000000 01011 01101 01000 00000 100010
M my
(0x02328020)
(0x016D4022)
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Lnh dang I (Immediate)
! Dng cho cc lnh s hoc vi ton hang tc th v
cc lnh load/store (nap/luu)
! rt: s hiu thanh ghi dch hoc thanh ghi ngun
! Hng s: t 2
15
dn +2
15
1
! ja chi: offset cng vi dja chi co s nm rs
! addi rt, rs, imm #(rt) $ (rs)+imm
! lw rt, imm(rs) #(rt) $ mem[(rs)+imm]
! sw rt, imm(rs) #(rt) " mem[(rs)+imm]
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits
NKK-HUST
V du lnh dang I
H!p ng"
8 17 16 5
Gi tr# cc tr$%ng
op rs rt imm
addi $s0, $s1, 5
addi $t0, $s3, -12
lw $t2, 32($0)
sw $s1, 4($t1)
8 19 8 -12
35 0 10 32
43 9 17 4
(0x22300005)
(0x2268FFF4)
(0x8C0A0020)
(0xAD310004)
001000 10001 10000 0000 0000 0000 0101
op rs rt imm
M my
001000 10011 01000 1111 1111 1111 0100
100011 00000 01010 0000 0000 0010 0000
101011 01001 10001 0000 0000 0000 0100
NKK-HUST
Lnh lui
0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0
31 25 20 15 0
lui = 15 Destination Unused
Immediate operand
op rs rt operand / offset
I
Content of $s0 after the instruction is executed
lui $s0, 61 # Gi trj tc th 61 duoc nap vo
# na cao ca $s0 vi 16 bit thp
# duoc thit lp v 0
NKK-HUST
Lnh kiu J
! Jump-type
! Ton hang 26-bit dja chi (addr)
! uoc s dung cho cc lnh jump (j)

op addr
6 bits 26 bits
J-Type
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Cc lnh logic
! Cc lnh logic d thao tc trn cc bit
Operation C Java MIPS
Shift left << << sll
Shift right >> >>> srl
Bitwise AND & & and, andi
Bitwise OR | | or, ori
Bitwise NOT ~ ~ nor
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V du lnh logic
1111 1111 1111 1111 0000 0000 0000 0000 $s1
0100 0110 1010 0001 1111 0000 1011 0111 $s2
$s3
$s4
$s5
$s6
Source Registers
Result Assembly Code
and $s3, $s1, $s2
or $s4, $s1, $s2
xor $s5, $s1, $s2
nor $s6, $s1, $s2
NKK-HUST
V du lnh logic
1111 1111 1111 1111 0000 0000 0000 0000 $s1
0100 0110 1010 0001 1111 0000 1011 0111 $s2
0100 0110 1010 0001 0000 0000 0000 0000 $s3
1111 1111 1111 1111 1111 0000 1011 0111 $s4
1011 1001 0101 1110 1111 0000 1011 0111 $s5
0000 0000 0000 0000 0000 1111 0100 1000 $s6
Source Registers
Result Assembly Code
and $s3, $s1, $s2
or $s4, $s1, $s2
xor $s5, $s1, $s2
nor $s6, $s1, $s2
NKK-HUST
V du lnh logic
0000 0000 0000 0000 0000 0000 1111 1111 $s1
Assembly Code
0000 0000 0000 0000 1111 1010 0011 0100 imm
$s2
$s3
$s4
andi $s2, $s1, 0xFA34
Source Values
Result
ori $s3, $s1, 0xFA34
xori $s4, $s1, 0xFA34
zero-extended
NKK-HUST
V du lnh logic
0000 0000 0000 0000 0000 0000 1111 1111 $s1
Assembly Code
0000 0000 0000 0000 1111 1010 0011 0100 imm
0000 0000 0000 0000 0000 0000 0011 0100 $s2
0000 0000 0000 0000 1111 1010 1111 1111 $s3
0000 0000 0000 0000 1111 1010 1100 1011 $s4
andi $s2, $s1, 0xFA34
Source Values
Result
ori $s3, $s1, 0xFA34
xori $s4, $s1, 0xFA34
zero-extended
NKK-HUST
ngha ca cc php ton logic
! Php AND dng d gi nguyn mt s bit trong
word, xa cc bit khc v 0
! Php OR dng d gi nguyn mt s bit trong
word, thit lp cc bit cn lai ln 1
! Php XOR dng d gi nguyn mt s bit trong
word, do gi trj cc bit cn lai
! Php NOT dng d do cc bit trong word
! i 0 thnh 1, v di 1 thnh 0
! MIPS khng c lnh NOT, nhung c lnh NOR vi 3
ton hang
! a NOR b == NOT ( a OR b )
nor $t0, $t1, $zero
NKK-HUST
Thao tc djch bit
! shamt: djch bao nhiu vj tr
! Djch tri logic (shift left logical)
! Djch tri v din cc bit 0 vo bn phi
! sll vi i bits l nhn vi 2
i
! Djch phi logic (shift right logical)
! Djch phi v din cc bit 0 vo bn tri
! srl vi i bits l chia cho 2
i
(chi vi s nguyn
khng du)
NKK-HUST
Lnh djch
! sll: shift left logical
! sll $t0, $t1, 5 # $t0 <= $t1 << 5
! srl: shift right logical
! srl $t0, $t1, 5 # $t0 <= $t1 >> 5
! sra: shift right arithmetic
! sra $t0, $t1, 5 # $t0 <= $t1 >>> 5
Variable shift instructions:
! sllv: shift left logical variable
! sllv $t0, $t1, $t2 # $t0 <= $t1 << $t2
! srlv: shift right logical variable
! srlv $t0, $t1, $t2 # $t0 <= $t1 >> $t2
! srav: shift right arithmetic variable
! srav $t0, $t1, $t2 # $t0 <= $t1 >>> $t2
NKK-HUST
V du cc lnh djch
sll $t0, $s1, 2
srl $s2, $s1, 2
sra $s3, $s1, 2
Assembly Code
0 0 17 8 2 0
Field Values
0 0 17 18 2 2
0 0 17 19 2 3
000000 00000 10001 01000 00010 000000
Machine Code
000000 00000 10001 10010 00010 000010
000000 00000 10001 10011 00010 000011
(0x00114080)
(0x00119082)
(0x00119883)
NKK-HUST

Nap hng s vo thanh ghi
! Trung hop hng s 16-bit " s dung lnh addi:
! V du: nap hng s 0x4f3c vo thanh ghi $s0:
addi $s0, $0, 0x4f3c
! Trong trung hop hng s 32-bit " s dung lnh
lui v lnh ori:
lui rt, constant_hi16bit
! Copy 16 bit cao ca hng s vo 16 bit tri ca rt
! Xa 16 bits bn phi ca rt v 0
ori rt,rt,constant_low16bit
! ua 16 bit thp ca hng s 32 bit vo thanh ghi rt

NKK-HUST
V du khi tao thanh ghi 32-bit
! 0010 0001 0001 0000 0000 0000 0011 1101 = 0x2110003d
lui $s0,0x2110
ori $s0,$s0,0x003d

0010 0001 0001 0000 0000 0000 0000 0000
0010 0001 0001 0000 0000 0000 0011 1101
! 1111 1111 1111 1111 1111 1111 1111 1111 = 0xffffffff
C th lm tuong tu nhu trn vi gi trj ny, tuy nhin c th
thuc hin don gin hon:
nor $s1,$zero,$zero
! Nap vo cc thanh ghi $s0 v $s1 cc gi trj 32-bit sau:
0010 0001 0001 0000 0000 0000 0011 1101
1111 1111 1111 1111 1111 1111 1111 1111
NKK-HUST
4. Tao cc cu trc diu khin
! Cu lnh If
! Cu lnh If/else
! Cu lnh lp While
! Cu lnh lp For
NKK-HUST
Cc lnh r nhnh v lnh nhy
! R nhnh dn lnh duoc dnh nhn nu diu
kin l dng, nguoc lai, thuc hin tun tu
! bltz rs,L1
! branch on less than zero
! nu (rs < 0) r nhnh dn lnh nhn L1;
! beq rs, rt, L1
! branch on equal
! nu (rs == rt) r nhnh dn lnh nhn L1;
! bne rs, rt, L1
! branch on not equal
! nu (rs != rt) r nhnh dn lnh nhn L1;
! j L1
! nhy (jump) khng diu kin dn lnh nhn L1
NKK-HUST
Djch cu lnh If
! M C:
if (i==j)
f = g+h;
f = f-i;
! f, g, h, i, j $s0, $s1, $s2, $s3, $s4

NKK-HUST
Djch cu lnh If
! M C:
if (i==j)
f = g+h;
f = f-i;
! f, g, h, i, j $s0, $s1, $s2, $s3, $s4

! M MIPS:
# $s0 = f, $s1 = g, $s2 = h
# $s3 = i, $s4 = j
bne $s3, $s4, L1 #Nu i=j
add $s0, $s1, $s2 #th f=g+h
L1: sub $s0, $s0, $s3 #f=f-i
NKK-HUST
Djch cu lnh If/else
! M C:
if (i==j) f = g+h;
else f = g-h;
! f, g, h, i, j $s0, $s1, $s2, $s3, $s4
NKK-HUST
Djch cu lnh If/else
! M C:
if (i==j) f = g+h;
else f = g-h;
! f, g, h, i, j $s0, $s1, $s2, $s3, $s4
! M MIPS:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit:
Assembler calculates addresses
NKK-HUST
Djch cu lnh vng lp While
! M C:
while (save[i] == k) i += 1;
! i $s3, k $s5, dja chi ca mng save $s6

NKK-HUST
Djch cu lnh vng lp While
! M C:
while (save[i] == k) i += 1;
! i $s3, k $s5, dja chi ca mng save $s6

! M MIPS duoc djch:
Loop: sll $t1,$s3,2 #$t1=4*i
add $t1,$t1,$s6 #$t1 tr! t"i save[i]
lw $t0,0($t1) #$t0 $ save[i]
bne $t0,$s5,Exit #n#u save[i]=k
addi $s3,$s3,1 #th i = i+1
j Loop #quay l$i
Exit: #n#u save[i]<>k,thot
NKK-HUST
Djch cu lnh vng lp For
! M C:
// add the numbers from 0 to 9
int sum = 0;
int i;
for (i=0; i!=10; i = i+1) {
sum = sum + i;
}
NKK-HUST
Djch cu lnh vng lp For
! M C:
// add the numbers from 0 to 9
int sum = 0;
int i;
for (i=0; i!=10; i = i+1) {
sum = sum + i;
}
! M MIPS duoc djch:
# $s0 = i, $s1 = sum
addi $s1, $0, 0 # sum = 0
add $s0, $0, $0 # i = 0
addi $t0, $0, 10 # $t0 = 10
for: beq $s0, $t0, done # Nu i = 10, thot
add $s1, $s1, $s0 # sum = sum + i
addi $s0, $s0, 1 # i = i+1
j for # quay lai
done:
NKK-HUST
Khi lnh co s
! Khi lnh co s l dy cc lnh vi
! Khng c lnh r nhnh nhng trong d
(ngoai tr cui)
! Khng c dch r nhnh ti (ngoai tr vj tr
du tin)
! Chuong trnh djch xc
djnh khi co s d ti uu
ha
! Cc b x l tin tin c
th tng tc d thuc hin
khi co s
NKK-HUST
Thm cc thao tc diu kin
! Thit lp kt qu = 1 nu diu kin l
dng, tri lai kt qu = 0
! slt rd, rs, rt
! set on less than
! if (rs < rt) rd = 1; else rd = 0;
! slti rt, rs, constant
! if (rs < constant) rt = 1; else rt = 0;
! S dung kt hop vi cc lnh beq, bne
slt $t0, $s1, $s2 # if ($s1 < $s2)
bne $t0, $zero, L # branch to L
NKK-HUST
V du m lnh slt v slti
! slt $s1,$s2,$s3 # n!u $s2)<($s3), $s1 $ 1
! # ng"#c l$i $s1 $ 0;
! # th"%ng theo sau l beq/bne
! slti $s1,$s2,61 # n!u ($s2)<61, $s1 $ 1
! # ng"#c l$i $s1 $ 0
1 1 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
31 25 20 15 0
ALU
instruction
Source 1
register
Source 2
register
op rs rt
R
rd sh
10 5
fn
Destination Unused slt = 42
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0
31 25 20 15 0
slti = 10 Destination Source Immediate operand
I 1
NKK-HUST
So snh s c du v khng du
! So snh s c du: slt, slti
! So snh s khng du: sltu, sltiu
! V du
! $s0 = 1111 1111 1111 1111 1111 1111 1111 1111
! $s1 = 0000 0000 0000 0000 0000 0000 0000 0001
! slt $t0, $s0, $s1 # signed
! 1 < +1 & $t0 = 1
! sltu $t0, $s0, $s1 # unsigned
! +4,294,967,295 > +1 & $t0 = 0
NKK-HUST
5. Goi th tuc (Procedure Calling)
! Cc buc yu cu:
1. t cc tham s vo cc thanh ghi
2. Chuyn diu khin dn th tuc
3. Thuc hin cc thao tc ca th tuc
4. t kt qu vo thanh ghi cho chuong
trnh d goi th tuc
5. Tr v vj tr d goi
NKK-HUST
S dung cc thanh ghi
! $a0 $a3: cc tham s (cc thanh ghi 4 7)
! $v0, $v1: gi trj kt qu (cc thanh ghi 2 v 3)
! $t0 $t9: cc gi trj tam thi
! C th duoc ghi lai bi th tuc duoc goi
! $s0 $s7: ct gi cc bin
! Cn phi ct/khi phuc bi th tuc duoc goi
! $gp: global pointer - con tr ton cuc cho d liu
tnh (thanh ghi 28)
! $sp: stack pointer -con tr ngn xp (thanh ghi 29)
! $fp: frame pointer con tr khung (thanh ghi 30)
! $ra: return address dja chi tr v (thanh ghi 31)
NKK-HUST
Cc lnh goi th tuc
! Goi th tuc: jump and link
jal ProcedureLabel
! ja chi ca lnh k tip duoc ct $ra
! Nhy dn nhn dch
! Tr v t th tuc: jump register
jr $ra
! Copy $ra vo b dm chuong trnh PC
NKK-HUST
Minh hoa goi Th tuc
jal proc
jr $ra
proc
Save, etc.
Restore
PC
Prepare
to continue
Prepare
to call
main
NKK-HUST
Goi th tuc lng nhau
jal abc
jr $ra
abc
Save
Restore
PC
Prepare
to continue
Prepare
to call
main
jal xyz
jr $ra
xyz
Procedure
abc
Procedure
xyz
NKK-HUST
V du Th tuc l
! Th tuc l l th tuc khng c li goi th
tuc khc
! M C:
int leaf_example (int g, h, i, j)
{ int f;
f = (g + h) - (i + j);
return f;
}
! Cc tham s g, h, i, j $a0, $a1, $a2, $a3
! f $s0 (do d, cn ct $s0 ra ngn xp)
! Kt qu $v0
NKK-HUST
V du Th tuc l
! M MIPS:
leaf_example:
addi $sp, $sp, -4
sw $s0, 0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a3
sub $s0, $t0, $t1
add $v0, $s0, $zero
lw $s0, 0($sp)
addi $sp, $sp, 4
jr $ra
C(t $s0 ra stack
Thn th) t*c
Khi ph*c $s0
K+t qu,
Tr- v.
NKK-HUST
V du Th tuc cnh
! L th tuc c goi th tuc khc
! C code:
int fact (int n)
{
if (n < 1) return (1);
else return n * fact(n - 1);
}
! Tham s n $a0
! Kt qu $v0
NKK-HUST
V du Th tuc cnh (tip)
! M MIPS:
fact:
addi $sp, $sp, -8 # dnh stack cho 2 muc
sw $ra, 4($sp) # ct dja chi tr v
sw $a0, 0($sp) # ct tham s n
slti $t0, $a0, 1 # kim tra n < 1
beq $t0, $zero, L1
addi $v0, $zero, 1 # nu dng, kt qu l 1
addi $sp, $sp, 8 # ly 2 muc t stack
jr $ra # v tr v
L1: addi $a0, $a0, -1 # nu khng, gim n
jal fact # goi d qui
lw $a0, 0($sp) # khi phuc n ban du
lw $ra, 4($sp) # v dja chi tr v
addi $sp, $sp, 8 # ly 2 muc t stack
mul $v0, $a0, $v0 # nhn d nhn kt qu
jr $ra # v tr v
NKK-HUST
S dung Stack khi goi th tuc
b
a
$sp
c
Frame for
current
procedure
$fp
.
.
.
Before calling
b
a
$sp
c
Frame for
previous
procedure
$fp
.
.
.
After calling
Frame for
current
procedure
Old ($fp)
Saved
registers
y
z
.
.
.
Local
vari ables
NKK-HUST
V du s dung stack
proc: sw $fp,-4($sp) # c&t gi tr' c( c)a frame pointer
addi $fp,$sp,0 # c&t ($sp) sang $fp
addi $sp,$sp,12 # chuy*n +,nh stack 3 v' tr
sw $ra,-8($fp) # c&t ($ra) ra stack
sw $s0,-12($fp) # c&t ($s0) ra stack
.
.
.

lw $s0,-12($fp) # l&y ph-n t. +,nh stack +"a vo $s0
lw $ra,-8($fp) # l&y ph-n t. ti!p theo / stack +"a vo $ra
addi $sp,$fp, 0 # khi ph0c $sp
lw $fp,-4($sp) # khi ph0c $fp
jr $ra # tr/ v1 t2 th) t0c
!Ct $fp, $ra v $s0 ra stack v khi
phuc chng cui th tuc
!$fp
!$sp
!($fp)
!$fp
!$sp
!($ra)
!($s0)
NKK-HUST
D liu k tu
! Cc tp k tu duoc m ha theo byte
! ASCII: 128 k tu
! 95 k thj hin thj , 33 m diu khin
! Latin-1: 256 k tu
! ASCII v cc k tu m rng
! Unicode: Tp k tu 32-bit
! uoc s dung trongJava, C++,
! Hu ht cc k tu ca cc ngn ng trn th
gii v cc k hiu
NKK-HUST
Cc thao tc vi Byte/Halfword
! C th s dung cc php ton logic
! Nap/Luu byte/halfword trong MIPS

! lb rt, offset(rs) lh rt, offset(rs)
! M rng du thnh 32 bits trong rt

! lbu rt, offset(rs) lhu rt, offset(rs)
! M rng zero thnh 32 bits trong rt

! sb rt, offset(rs) sh rt, offset(rs)
! Chi luu byte/halfword bn phi
NKK-HUST
V du copy String
! M C:
void strcpy (char x[], char y[])
{ int i;
i = 0;
while ((x[i]=y[i])!='\0')
i += 1;
}
! Cc dja chi ca x, y $a0, $a1
! i $s0
NKK-HUST
V du Copy String
! MIPS code:
strcpy:
addi $sp, $sp, -4 # adjust stack for 1 item
sw $s0, 0($sp) # save $s0
add $s0, $zero, $zero # i = 0
L1: add $t1, $s0, $a1 # addr of y[i] in $t1
lbu $t2, 0($t1) # $t2 = y[i]
add $t3, $s0, $a0 # addr of x[i] in $t3
sb $t2, 0($t3) # x[i] = y[i]
beq $t2, $zero, L2 # exit loop if y[i] == 0
addi $s0, $s0, 1 # i = i + 1
j L1 # next iteration of loop
L2: lw $s0, 0($sp) # restore saved $s0
addi $sp, $sp, 4 # pop 1 item from stack
jr $ra # and return
NKK-HUST
ja chi ha cho cc lnh Branch
! Cc lnh Branch chi ra:
! M thao tc, hai thanh ghi, offset
! Hu ht cc dch r nhnh l r nhnh gn
! R xui hoc r nguoc
op rs rt constant
! jnh dja chi tuong di vi PC
! PC-relative addressing
! ja chi dch = PC + hng s 4
! Ch : truc d PC d duoc tng ln
NKK-HUST
V du lnh Branch

! bltz $s1,L # r3 nhnh khi ($s1)< 0
! beq $s1,$s2,L # r3 nhnh khi ($s1)=($s2)
! bne $s1,$s2,L # r3 nhnh khi ($s1)'($s2)
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0
31 25 20 15 0
bltz = 1 Zero Source Relati ve branch distance in words
I 0
1 1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0
31 25 20 15 0
beq = 4
bne = 5
Source 2 Source 1 Relati ve branch distance in words
I 1
NKK-HUST
ja chi ha cho lnh Jump
! ch ca lnh Jump (j v jal) c th l
bt ky ch no trong chuong trnh
! Cn m ha dy d dja chi trong lnh
op address
6 bits 26 bits
! jnh dja chi nhy (gi) truc tip
(Pseudo)Direct jump addressing
! ja chi dch = PC
3128
: (address 4)
NKK-HUST
V du m lnh Jump
! j verify # nh4y +!n v' tr c nhn verify
! jr $ra # nh4y +!n v' tr c +'a ch, / $ra;
# $ra may hold a return address
0
0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0
31 0
j = 2

op jump target address
J
Effecti ve target address (32 bits)
25
From PC
0 0
x x x x
0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
31 25 20 15 0
ALU
instruction
Source
register
Unused
op rs rt
R
rd sh
10 5
fn
Unused Unused jr = 8
!$ra l thanh ghi $31
(return address)
NKK-HUST
V du m ha lnh
Loop: sll $t1, $s3, 2 80000 0 0 19 9 2 0
add $t1, $t1, $s6 80004 0 9 22 9 0 32
lw $t0, 0($t1) 80008 35 9 8 0
bne $t0, $s5, Exit 80012 5 8 21 2
addi $s3, $s3, 1 80016 8 19 19 1
j Loop 80020 2 20000
Exit: 80024
NKK-HUST
R nhnh xa
! Nu dch r nhnh l qu xa d m ha
vi offset 16-bit, assembler s vit lai
code
! V du
beq $s0,$s1, L1

bne $s0,$s1, L2
j L1
L2:
NKK-HUST
6. Tm tt v cc phuong php djnh dja chi
1. jnh dja chi tc th
2. jnh dja chi thanh ghi
3. jnh dja chi co s

4. jnh dja chi tuong di vi PC

5. jnh dja chi gi truc tip
NKK-HUST
7. Thm mt s lnh
1 0 0 1 1 0 0
fn
0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 1 1 0 0 0 0 0 0 0 0
31 25 20 15 0
ALU
instruction
Source
register 1
Source
register 2
op rs rt
R
rd sh
10 5
Unused Unused mult = 24
di v = 26
1 0 0 0 0 0 0 1 0 0
fn
0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0
31 25 20 15 0
ALU
instruction
Unused Unused
op rs rt
R
rd sh
10 5
Destination
register
Unused mfhi = 16
mflo = 18
Lnh nhn v lnh chia:
mult $s0, $s1 # set Hi,Lo to ($s0)(($s1)
div $s0, $s1 # set Hi to ($s0)mod($s1)
# and Lo to ($s0)/($s1)
Lnh copy ni dung cc thanh ghi Hi v Lo
mfhi $t0 # set $t0 to (Hi)
mflo $t0 # set $t0 to (Lo)
Reg
file
Mul/Div
unit
Hi Lo
NKK-HUST
Cc lnh s hoc s nguyn khng du
addu $t0,$s0,$s1 # set $t0 to ($s0)+($s1)
subu $t0,$s0,$s1 # set $t0 to ($s0)($s1)
multu $s0,$s1 # set Hi,Lo to ($s0)(($s1)
divu $s0,$s1 # set Hi to ($s0)mod($s1)
# and Lo to ($s0)/($s1)
addiu $t0,$s0,61 # set $t0 to ($s0)+61;
# the immediate operand is
# sign extended
NKK-HUST
Cc lnh vi s du phy dng
! Cc thanh ghi s du phy dng
! 32 thanh ghi 32-bit (single-precision): $f0, $f1,
$f31
! Cp di d cha d liu dang 64-bit (double-
precision): $f0/$f1, $f2/$f3,
! (Release 2 of MIPs ISA supports 32 64-bit FP regs)
! Cc lnh s du phy dng chi thuc hin trn
cc thanh ghi s du phy dng
! FP load and store instructions
! lwc1, ldc1, swc1, sdc1
! e.g., ldc1 $f8, 32($sp)
NKK-HUST
Cc lnh vi s du phy dng
! Single-precision arithmetic
! add.s, sub.s, mul.s, div.s
! e.g., add.s $f0, $f1, $f6
! Double-precision arithmetic
! add.d, sub.d, mul.d, div.d
! e.g., mul.d $f4, $f4, $f6
! Single- and double-precision comparison
! c.xx.s, c.xx.d (xx is eq, lt, le, )
! Sets or clears FP condition-code bit
! e.g. c.lt.s $f3, $f4
! Branch on FP condition code true or false
! bc1t, bc1f
! e.g., bc1t TargetLabel
NKK-HUST
8. Thuc hnh lp trnh hop ng MIPS
! Phn mm lp trnh: MARS
! Lp trnh cc v du
! Chay cc chuong trnh c sn v phn tch
! MIPS Reference Data
NKK-HUST

Djch v chay ng dung
Assembly Code
High Level Code
Compiler
Object File
Assembler
Executable
Linker
Memory
Loader
Object Files
Library Files
NKK-HUST

Chuong trnh trong b nh
! Cc lnh (instructions)
! D liu
! Ton cuc/tnh: duoc cp pht truc khi chuong trnh
bt du thuc hin
! ng: duoc cp pht trong khi chuong trnh thuc
hin

! B nh:
! 2
32
= 4 gigabytes (4 GB)
! T dja chi 0x00000000 dn 0xFFFFFFFF
NKK-HUST

Bn d b nh ca MIPS
Segment Address
0xFFFFFFFC
0x80000000
0x7FFFFFFC
0x10010000
0x1000FFFC
0x10000000
0x0FFFFFFC
0x00400000
0x003FFFFC
0x00000000
Reserved
Stack
Heap
Static Data
Text
Reserved
Dynamic Data
NKK-HUST

V du: M C
int f, g, y; // global
variables

int main(void)
{
f = 2;
g = 3;
y = sum(f, g);
return y;
}

int sum(int a, int b) {
return (a + b);
}
NKK-HUST

V du chuong trnh hop ng
.data
f:
g:
y:
.text
main:
addi $sp, $sp, -4 # stack frame
sw $ra, 0($sp) # store $ra
addi $a0, $0, 2 # $a0 = 2
sw $a0, f # f = 2
addi $a1, $0, 3 # $a1 = 3
sw $a1, g # g = 3
jal sum # call sum
sw $v0, y # y = sum()
lw $ra, 0($sp) # restore $ra
addi $sp, $sp, 4 # restore $sp
jr $ra # return to OS
sum:
add $v0, $a0, $a1 # $v0 = a + b
jr $ra # return
NKK-HUST

Bng k hiu
K hiu ja chi
f 0x10000000
g 0x10000004
y 0x10000008
main 0x00400000
sum 0x0040002C
NKK-HUST

Chuong trnh thuc thi
Executable file header Text Size Data Size
Text segment
Data segment
Address Instruction
Address Data
0x00400000
0x00400004
0x00400008
0x0040000C
0x00400010
0x00400014
0x00400018
0x0040001C
0x00400020
0x00400024
0x00400028
0x0040002C
0x00400030
addi $sp, $sp, -4
sw $ra, 0 ($sp)
addi $a0, $0, 2
sw $a0, 0x8000 ($gp)
addi $a1, $0, 3
sw $a1, 0x8004 ($gp)
jal 0x0040002C
sw $v0, 0x8008 ($gp)
lw $ra, 0 ($sp)
addi $sp, $sp, -4
jr $ra
add $v0, $a0, $a1
jr $ra
0x10000000
0x10000004
0x10000008
f
g
y
0xC (12 bytes) 0x34 (52 bytes)
0x23BDFFFC
0xAFBF0000
0x20040002
0xAF848000
0x20050003
0xAF858004
0x0C10000B
0xAF828008
0x8FBF0000
0x23BD0004
0x03E00008
0x00851020
0x03E0008
NKK-HUST

Chuong trnh trong b nh
y
g
f
0x03E00008
0x00851020
0x03E00008
0x23BD0004
0x8FBF0000
0xAF828008
0x0C10000B
0xAF858004
0x20050003
0xAF848000
0x20040002
0xAFBF0000
0x23BDFFFC
Memory Address
$sp = 0x7FFFFFFC 0x7FFFFFFC
0x10010000
0x00400000
Stack
Heap
$gp = 0x10008000
PC = 0x00400000
0x10000000
Reserved
Reserved
NKK-HUST

V du lnh gi (Pseudoinstruction)
Pseudoinstruction MIPS Instructions
li $s0, 0x1234AA77 lui $s0, 0x1234
ori $s0, 0xAA77
mul $s0, $s1, $s2 mult $s1, $s2
mflo $s0
clear $t0 add $t0, $0, $0
move $s1, $s2 add $s2, $s1, $0
nop sll $0, $0, 0
NKK-HUST
5.3. Kin trc tp lnh Intel x86(*)
! Su tin ha ca cc b x l Intel
! 8080 (1974): 8-bit microprocessor
! Accumulator, plus 3 index-register pairs
! 8086 (1978): 16-bit extension to 8080
! Complex instruction set (CISC)
! 8087 (1980): floating-point coprocessor
! Adds FP instructions and register stack
! 80286 (1982): 24-bit addresses, MMU
! Segmented memory mapping and protection
! 80386 (1985): 32-bit extension (now IA-32)
! Additional addressing modes and operations
! Paged memory mapping as well as segments
NKK-HUST
Kin trc tp lnh Intel x86
! i486 (1989): pipelined, on-chip caches and FPU
! Compatible competitors: AMD, Cyrix,
! Pentium (1993): superscalar, 64-bit datapath
! Later versions added MMX (Multi-Media eXtension)
instructions
! The infamous FDIV bug
! Pentium Pro (1995), Pentium II (1997)
! New microarchitecture
! Pentium III (1999)
! Added SSE (Streaming SIMD Extensions) and
associated registers
! Pentium 4 (2001)
! New microarchitecture
! Added SSE2 instructions
! Intel Core (2006)
! Added SSE4 instructions, virtual machine support
NKK-HUST
Cc thanh ghi co bn ca x86
NKK-HUST
Cc phuong php djnh dja chi co bn
! Hai ton hang ca lnh
Source/dest operand Second source operand
Register Register
Register Immediate
Register Memory
Memory Register
Memory Immediate
! Cc phuong php djnh dja chi
! Address in register
! Address = R
base
+ displacement
! Address = R
base
+ 2
scale
R
index
(scale = 0, 1, 2, or 3)
! Address = R
base
+ 2
scale
R
index
+ displacement
NKK-HUST
M ha lnh x86
NKK-HUST
H%t ch!"ng 5
NKK-HUST
Kin trc my tnh
Ch!"ng 6
B7 X8 L9
(Processor)
Nguy!n Kim Khnh
NKK-HUST
Ni dung hoc phn
Chuong 6. B x l

NKK-HUST
6.1. T chc ca b x l
6.2. Thit k don vj diu khin
6.3. K thut dung ng lnh
6.4. V d# thi+t k+ b, x- l* theo ki+n trc
MIPS*
Ni dung
NKK-HUST
6.1. T chc ca CPU
! Nhim vu ca CPU:
! Nhn lnh (Fetch Instruction): CPU doc lnh t b
nh.
! Gii m lnh (Decode Instruction): xc djnh thao tc
m lnh yu cu.
! Nhn d liu (Fetch Data): nhn d liu t b nh
hoc cc cng vo-ra.
! X l d liu (Process Data): thuc hin php ton s
hoc hay php ton logic vi cc d liu.
! Ghi d liu (Write Data): ghi d liu ra b nh hay
cng vo-ra
1. Cu trc co bn ca CPU
NKK-HUST
So d cu trc co bn ca CPU
!"n v#
$i%u khi&n
(CU)
!"n v#
s' h(c
v logic
(ALU)
T)p
thanh ghi
(RF)
!"n v# n'i ghp bus (BIU)
bus d* li+u
bus bn trong
bus $#a ch, bus $i%u khi&n
NKK-HUST
! on vj diu khin (Control Unit - CU)
! on vj s hoc v logic (Arithmetic and
Logic Unit - ALU)
! Tp thanh ghi (Register File - RF)
! on vj ni ghp bus (Bus Interface Unit -
BIU)
! Bus bn trong (Internal Bus)
Cc thnh phn co bn ca CPU
NKK-HUST
2. on vj s hoc v logic
! Chc nng: Thuc hin cc php ton
s hoc v php ton logic:
! S hoc: cng, tr, nhn, chia, tng, gim,
do du
! Logic: AND, OR, XOR, NOT, php djch bit.
NKK-HUST
M hnh kt ni ALU
!"n v#
s$ h%c v logic
(ALU)
D& li'u t(
cc thanh ghi
Cc tn hi'u
t( )"n v#
)i*u khi+n
Thanh ghi c,
D& li'u )-n
cc thanh ghi
NKK-HUST
3. on vj diu khin
! Chc nng
! iu khin nhn lnh t b nh dua vo
thanh ghi lnh
! Tng ni dung ca PC d tr sang lnh k
tip
! Gii m lnh d duoc nhn d xc djnh thao
tc m lnh yu cu
! Pht ra cc tn hiu diu khin thuc hin lnh
! Nhn cc tn hiu yu cu t bus h thng v
dp ng vi cc yu cu d.
NKK-HUST
M hnh kt ni don vj diu khin
!"n v# $i%u khi&n
Thanh ghi l'nh
Bus $i%u khi&n
Cc tn hi'u
$i%u khi&n
bn trong CPU
Cc c(
Clock
Cc tn hi'u
$i%u khi&n $)n
bus h' th*ng
Cc tn hi'u
$i%u khi&n t+
bus h' th*ng
NKK-HUST
Cc tn hiu dua dn don vj diu khin
! Clock: tn hiu nhjp t mach tao dao
dng bn ngoi.
! M lnh t thanh ghi lnh dua dn d
gii m.
! Cc c t thanh ghi c cho bit trang
thi ca CPU.
! Cc tn hiu yu cu t bus diu khin
NKK-HUST
Cc tn hiu pht ra t don vj diu khin
! Cc tn hiu diu khin bn trong CPU:
! iu khin cc thanh ghi
! iu khin ALU
! Cc tn hiu diu khin bn ngoi CPU:
! iu khin b nh
! iu khin cc m-dun vo-ra
NKK-HUST
4. Hoat dng ca chu trnh lnh
Chu trnh lnh
! Nhn lnh
! Gii m lnh
! Nhn ton hang
! Thuc hin lnh
! Ct ton hang
! Ngt

NKK-HUST
Gin d trang thi chu trnh lnh
Nh!n l"nh
Tnh
#$a ch%
c&a l"nh
Gi'i m
thao tc
l"nh
Nh!n
ton h(ng
Tnh
#$a ch%
ton h(ng
Thao tc
d) li"u
C*t
ton h(ng
Tnh
#$a ch%
ton h(ng
Ki+m tra
ng,t
Ng,t
L"nh hon thnh,
nh!n l"nh ti-p theo
Quay l(i v.i d) li"u
String ho/c Vector
Khng
ng,t
Nhi0u
ton
h(ng
Nhi0u
ton
h(ng
C
ng,t
NKK-HUST
Nhn lnh
! CPU dua dja chi ca lnh cn nhn t b
dm chuong trnh PC ra bus dja chi
! CPU pht tn hiu diu khin doc b nh
! Lnh t b nh duoc dt ln bus d liu
v duoc CPU copy vo thanh ghi lnh IR
! CPU tng ni dung PC d tr sang lnh
k tip
NKK-HUST
So d m t qu trnh nhn lnh
CPU
PC
!"n v#
$i%u khi&n
IR
B' nh(
Bus
$#a
ch)
Bus
$i%u
khi&n
Bus
d*
li+u
PC: B' $,m ch-"ng trnh
IR: Thanh ghi l+nh
NKK-HUST
Gii m lnh
! Lnh t thanh ghi lnh IR duoc dua
dn don vj diu khin
! on vj diu khin tin hnh gii m lnh
d xc djnh thao tc phi thuc hin
! Gii m lnh xy ra bn trong CPU
NKK-HUST
Nhn d liu t b nh
! CPU dua dja chi ca ton hang ra bus
dja chi
! CPU pht tn hiu diu khin doc
! Ton hang duoc doc vo CPU
! Tuong tu nhu nhn lnh
NKK-HUST
So d m t nhn d liu t b nh
CPU
MAR
!"n v#
$i%u khi&n
MBR
B' nh(
Bus
$#a
ch)
Bus
$i%u
khi&n
Bus
d*
li+u
MAR: Thanh ghi $#a ch) b' nh(
MBR: Thanh ghi $+m b' nh(
NKK-HUST
Thuc hin lnh
! C nhiu dang tuy thuc vo lnh
! C th l:
! oc/Ghi b nh
! Vo/Ra
! Chuyn gia cc thanh ghi
! Thao tc s hoc/logic
! Chuyn diu khin (r nhnh)
! ...
NKK-HUST
Ghi ton hang
! CPU dua dja chi ra bus dja chi
! CPU dua d liu cn ghi ra bus d liu
! CPU pht tn hiu diu khin ghi
! D liu trn bus d liu duoc copy dn
vj tr xc djnh
NKK-HUST
So d m t qu trnh ghi ton hang
CPU
MAR
!"n v#
$i%u khi&n
MBR
B' nh(
Bus
$#a
ch)
Bus
$i%u
khi&n
Bus
d*
li+u
MAR: Thanh ghi $#a ch) b' nh(
MBR: Thanh ghi $+m b' nh(
NKK-HUST
Ngt
! Ni dung ca b dm chuong trnh PC (dja
chi tr v sau khi ngt) duoc dua ra bus d
liu
! CPU dua dja chi (thung duoc ly t con tr
ngn xp SP) ra bus dja chi
! CPU pht tn hiu diu khin ghi b nh
! ja chi tr v trn bus d liu duoc ghi ra vj
tr xc djnh ( ngn xp)
! ja chi lnh du tin ca chuong trnh con
diu khin ngt duoc nap vo PC
NKK-HUST
So d m t chu trnh ngt
CPU
MAR
MBR
B! nh"
PC
#$n v%
&i'u khi(n
SP
Bus
&%a
ch)
Bus
&i'u
khi(n
Bus
d*
li+u
MAR: Thanh ghi &%a ch) b! nh"
MBR: Thanh ghi &+m b! nh"
PC: B! &,m ch-$ng trnh
SP: Con tr. ng/n x,p
NKK-HUST
6.2. Cc phuong php thit k don vj diu khin
! on vj diu khin vi chuong trnh
(Microprogrammed Control Unit)
! on vj diu khin ni kt cng
(Hardwired Control Unit)
NKK-HUST
1. on vj diu khin vi chuong trnh
! B nh vi chuong trnh
(ROM) luu tr cc vi
chuong trnh
(microprogram)
! Mt vi chuong trnh bao
gm cc vi lnh
(microinstruction)
! Mi vi lnh m ho cho
mt vi thao tc
(microoperation)
! hon thnh mt lnh
cn thuc hin mt hoc
mt vi vi chuong trnh
! Tc d chm
B! nh"
vi ch#$ng trnh
Thanh ghi l%nh
Tn hi%u &i'u
khi(n bn trong
CPU
Cc c)
Clock
Tn hi%u &i'u
khi(n &*n bus h%
th+ng
Thanh ghi &,a ch- vi l%nh M.ch dy
B! gi/i m
B! gi/i m vi l%nh
Thanh ghi &%m vi lnh
Cc tn hi%u
&i'u khi(n t0
bus h% th+ng
Vi l%nh
ti*p
theo
NKK-HUST
2. on vj diu khin ni kt cng
! S dung mach
cng d gii m
v tao cc tn hiu
diu khin thuc
hin lnh
! Tc d nhanh
! on vj diu khin
phc tap

!"n v#
$i%u khi&n
B' gi(i m
Cc
c)
Clock
Cc tn hi*u $i%u khi&n
M+ch
phn
chia th)i
gian
T1
.
.
.
.
.
.
C0
. . .
Thanh ghi l*nh
T2
Tn
Cm-1 C1
NKK-HUST
6.3. K thut dung ng lnh v song song mc lnh
! K thut dung ng lnh (Instruction Pipelining):
Chia chu trnh lnh thnh cc cng doan v cho
php thuc hin gi ln nhau (nhu dy chuyn lp
rp)
! Chng han c 6 cng doan:
! Nhn lnh (Fetch Instruction - FI)
! Gii m lnh (Decode Instruction - DI)
! Tnh dja chi ton hang (Calculate Operand Address-CO)
! Nhn ton hang (Fetch Operands - FO)
! Thuc hin lnh (Execute Instruction - EI)
! Ghi ton hang (Write Operands - WO)
NKK-HUST
Biu d thi gian ca dung ng lnh
1 10 9 8 7 5 4 3 2 6 t 13 12 11
FI EI FO CO DI WO
FI EI FO CO DI WO
FI EI FO CO DI WO
FI EI FO CO DI WO
FI EI FO CO DI WO
FI EI FO CO DI WO
FI EI FO CO DI WO
FI EI FO CO DI WO
l!nh 1
l!nh 2
l!nh 3
l!nh 4
l!nh 5
l!nh 6
l!nh 7
l!nh 8
NKK-HUST
Cc Hazard (tr ngai) ca dung ng lnh
! Hazard: Tnh hung ngn cn bt du ca
lnh tip theo chu ky tip theo.
! Hazard cu trc: do ti nguyn duoc yu cu
dang bn
! Hazard d liu: cn phi doi d lnh truc hon
thnh vic doc/ghi d liu
! Hazard diu khin: do r nhnh gy ra

NKK-HUST
Hazard v cu trc
! Khc phuc:
! nhn ti nguyn d trnh xung dt
! Lm tr
V du:
! Bus d liu: truyn lnh v d liu
" Bus lnh ring, bus d liu ring (cache
lnh v cache d liu)
NKK-HUST
V du Hazard v cu trc
conflict on arithmetic unit
cache miss
TLB miss
MULT A,B,C
MULT D,E,F
I D F E E E W
I D F F F E E E W
3 clocks necessary for multiplication
stall
NKK-HUST
Hazard v d liu
! Cc dang:
! RAW (Read After Write)
! WAR (Write After Read)
! WAW (Write After Write)
NKK-HUST
Su phu thuc v d liu
RAW
WAR
WAW
ADD A,B,C
ADD E,A,D
ADD A,B,C
ADD B,D,E
ADD A,B,C
ADD A,D,E
Write-A must be earlier than
Read-A
Read-B must be earlier than
Write-B
First Write-A must be earlier
Than second Write-A
NKK-HUST
WAR and WAW
WAR
WAW
ADD A,B,C
ADD B,D,E
ADD A,B,C
ADD A,D,E
Read-B is earlier than Write-B
first Write-A is earlier than second Write-A
I D F E W
I D F E W
Write B
Read B
I D F E W
I D F E W
Write A
Write A
no conflict at in-order pipeline
conflict at out-of-order pipeline
NKK-HUST
RAW
ADD A,B,C
ADD E,A,D
I D F E W
I D F E C
I D F E W
I D D D F E W
Read A
Write A
stall
Write-A must be earlier
Than Read-A
Write A
Read A
NKK-HUST
Hazard diu khin
BEQ A, B, Label
LOAD C, X

Label: LOAD C, Y
I D F E C
I D F E C
set PC
stall
Wait for branch
address
calculation
next instruction to a branch instruction cannot be fetched until branch condition
defined and PC updated
NKK-HUST
Cc kin trc song song mc lnh
! Siu dung ng (Superpipeline & Hyperpipeline)
CO L!nh 1 FI DI FO EI WO
CO FI DI FO EI WO
CO FI DI FO EI WO
CO FI DI FO EI WO L!nh 4
L!nh 3
L!nh 2
CO L!nh 1 FI DI FO EI WO
CO FI DI FO EI WO
CO FI DI FO EI WO
L!nh 3
L!nh 2
CO FI DI FO EI WO
L!nh 5
! Siu v hung (Superscalar)
NKK-HUST
6.4. Thi+t k+ b, x- l* theo ki+n trc MIPS*
B x l MIPS Chapter 4 [2]
NKK-HUST
H%t ch!"ng 6
NKK-HUST
Kin trc my tnh
Ch!"ng 7
B7 NH# MY TNH

Nguy!n Kim Khnh
NKK-HUST
Ni dung hoc phn
Chuong 6. B x l

NKK-HUST
7.1. Phn cp b nh
7.2. B nh chnh
7.3. B nh cache
7.4. B nh ngoi
7.5. B nh o
Ni dung ca chuong 7
NKK-HUST
7.1. Phn cp b nh my tnh
! Vj tr
! Bn trong CPU:
! tp thanh ghi
! B nh trong:
! b nh chnh
! b nh cache
! B nh ngoi: cc thit bj nh
! Dung luong
! di t nh (tnh bng bit)
! S luong t nh
1. Cc dc trung ca b nh my tnh
NKK-HUST
Cc dc trung ca h thng nh (tip)
! on vj truyn
! T nh
! Khi nh
! Phuong php truy nhp
! Truy nhp tun tu (bng t)
! Truy nhp truc tip (cc loai da)
! Truy nhp ngu nhin (b nh bn dn)
! Truy nhp lin kt (cache)
NKK-HUST
! Hiu nng (performance)
! Thi gian truy nhp
! Chu ky nh
! Tc d truyn
! Kiu vt l
! B nh bn dn
! B nh t
! B nh quang
NKK-HUST
! Cc dc tnh vt l
! Kh bin / Khng kh bin
(volatile / nonvolatile)
! Xo duoc / khng xo duoc
! T chc

NKK-HUST
2. Phn cp b nh
4.1 / COMPUTER MEMORY SYSTEM OVERVIEW 117
decreasing frequency of access. We examine this concept in greater detail when we
discuss the cache, later in this chapter, and virtual memory in Chapter 8. A brief
explanation is provided at this point.
The use of two levels of memory to reduce average access time works in prin-
ciple, but only if conditions (a) through (d) apply. By employing a variety of tech-
nologies, a spectrum of memory systems exists that satisfies conditions (a) through
(c). Fortunately, condition (d) is also generally valid.
The basis for the validity of condition (d) is a principle known as locality of
reference [DENN68]. During the course of execution of a program, memory refer-
ences by the processor, for both instructions and data, tend to cluster. Programs
typically contain a number of iterative loops and subroutines. Once a loop or sub-
routine is entered, there are repeated references to a small set of instructions.
Similarly, operations on tables and arrays involve access to a clustered set of data
words. Over a long period of time, the clusters in use change, but over a short period
of time, the processor is primarily working with fixed clusters of memory references.
Inboard
m
em
ory
O
utboard
storage
O
ff-line
storage
M
ain
m
em
ory
M
agnetic disk
C
D
-RO
M
C
D
-RW
DV
D
-RW
DV
D
-R
A
M
Blu-R
ay
M
agnetic tape
C
ache
Reg-
isters
Figure 4.1 The Memory Hierarchy
NKK-HUST
Cng ngh b nh
! Static RAM (SRAM)
! 0.5ns 2.5ns, $2000 $5000 per GB
! Dynamic RAM (DRAM)
! 50ns 70ns, $20 $75 per GB
! da t
! 5ms 20ms, $0.20 $2 per GB
! B nh l tung
! Thi gian truy nhp nhu SRAM
! Dung luong v gi thnh nhu da cng
NKK-HUST
V du h thng nh thng dung
T tri sang phi:
! dung luong tng dn
! tc d gim dn
! gi thnh/1bit gim dn
B! vi x" l#
CPU
Cahe
L1
T$p
thanh
ghi
B!
nh%
chnh
B!
nh%
ngoi
Cache
L2
B! nh%
m&ng
NKK-HUST
Nguyn l cuc b ho tham chiu b nh
! Trong mt khong thi gian d nh CPU
thung chi tham chiu cc thng tin
trong mt khi nh cuc b
! V du:
! Cu trc chuong trnh tun tu
! Vng lp c thn nh
! Cu trc d liu mng
NKK-HUST
7.2. B nh chnh
Ki!u b" nh# Tiu
chu$n
Kh% n&ng xo C' ch( ghi Tnh
kh% bi(n
Read Only Memory
(ROM) B% nh&
ch' ()c
Khng xo
(*+c
M,t n-
Khng
kh. bi/n
Programmable ROM
(PROM)
B0ng (i#n
Erasable PROM
(EPROM)
B% nh&
h1u nh*
ch' ()c
b0ng tia c2c tm,
c. chip
Electrically Erasable
PROM (EEPROM)
b0ng (i#n,
m3c t4ng byte
Flash memory
B% nh&
()c-ghi
b0ng (i#n,
t4ng kh"i
Random Access
Memory (RAM)
b0ng (i#n,
m3c t4ng byte
B0ng (i#n
Kh. bi/n
1. B nh bn dn
NKK-HUST
ROM (Read Only Memory)
! B nh khng kh bin
! Luu tr cc thng tin sau:
! Thu vin cc chuong trnh con
! Cc chuong trnh diu khin h thng (BIOS)
! Cc bng chc nng
! Vi chuong trnh
NKK-HUST
Cc kiu ROM
! ROM mt na:
! thng tin duoc ghi khi sn xut
! rt dt
! PROM (Programmable ROM)
! Cn thit bj chuyn dung d ghi bng chuong
trnh " chi ghi duoc mt ln
! EPROM (Erasable PROM)
! Cn thit bj chuyn dung d ghi bng chuong
trnh " ghi duoc nhiu ln
! Truc khi ghi lai, xa bng tia cuc tm
NKK-HUST
Cc kiu ROM (tip)
! EEPROM (Electrically Erasable PROM)
! C th ghi theo tng byte
! Xa bng din
! Flash memory (B nh cuc nhanh)
! Ghi theo khi
! Xa bng din
NKK-HUST
RAM (Random Access Memory)
! B nh doc-ghi (Read/Write Memory)
! Kh bin
! Luu tr thng tin tam thi
! C hai loai: SRAM v DRAM
(Static and Dynamic)
NKK-HUST
SRAM (Static) RAM tnh
! Cc bit duoc luu tr bng cc Flip-Flop
" thng tin n djnh
! Cu trc phc tap
! Dung luong chip nh
! Tc d nhanh
! t tin
! Dng lm b nh cache
NKK-HUST
DRAM (Dynamic) RAM dng
! Cc bit duoc luu tr trn tu din
" cn phi c mach lm tuoi
! Cu trc don gin
! Dung luong ln
! Tc d chm hon
! R tin hon
! Dng lm b nh chnh
NKK-HUST
Cc DRAM tin tin
! Enhanced DRAM
! Cache DRAM
! Synchronous DRAM (SDRAM): lm vic
duoc dng b bi xung clock
! DDR-SDRAM (Double Data Rate SDRAM)
! Rambus DRAM (RDRAM)
NKK-HUST
T chc ca chip nh
% So d co bn ca chip nh
Chip nh!
2
n
x m bit
A0
An-1
A1
D0
Dm-1
D1
CS
OE WE
.
.
.
.
.
.
NKK-HUST
Cc tn hiu ca chip nh
! Cc dung dja chi: A
n-1
A
0
" c 2
n
t nh
! Cc dung d liu: D
m-1
D
0
" d di t
nh = m bit
! Dung luong chip nh = 2
n
x m bit
! Cc dung diu khin:
! Tn hiu chon chip CS (Chip Select)
! Tn hiu diu khin doc OE (Output Enable)
! Tn hiu diu khin ghi WE (Write Enable)
(Cc tn hiu diu khin thung tch cuc vi mc 0)
NKK-HUST
T chc ca DRAM
! Dng n dung dja chi dn knh " cho
php truyn 2n bit dja chi
! Tn hiu chon dja chi hng RAS
(Row Address Select)
! Tn hiu chon dja chi ct CAS
(Column Address Select)
! Dung luong ca DRAM= 2
2n
x m bit

NKK-HUST
V du chip nh
5.1 / SEMICONDUCTOR MAIN MEMORY 167
Chip Packaging
As was mentioned in Chapter 2, an integrated circuit is mounted on a package that
contains pins for connection to the outside world.
Figure 5.4a shows an example EPROM package, which is an 8-Mbit chip
organized as 1M * 8. In this case, the organization is treated as a one-word-per-chip
package. The package includes 32 pins, which is one of the standard chip package
sizes. The pins support the following signal lines:
The address of the word being accessed. For 1Mwords, a total of 20 (2
20
= 1M)
pins are needed (A0A19).
The data to be read out, consisting of 8 lines (D0D7).
The power supply to the chip (Vcc).
A ground pin (Vss).
A chip enable (CE) pin. Because there may be more than one memory chip,
each of which is connected to the same address bus, the CE pin is used to indi-
cate whether or not the address is valid for this chip. The CE pin is activated
by logic connected to the higher-order bits of the address bus (i.e., address bits
above A19). The use of this signal is illustrated presently.
Aprogramvoltage (Vpp) that is supplied during programming (write operations).
A typical DRAMpin configuration is shown in Figure 5.4b, for a 16-Mbit chip
organized as 4M * 4. There are several differences from a ROM chip. Because
a RAM can be updated, the data pins are input/output. The write enable (WE)
and output enable (OE) pins indicate whether this is a write or read operation.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
Vss
Vcc
A18
A17
A14
A13
A8
A9
A11
Vpp
A10
CE
D7
D6
D5
D4
D3
32-Pin Dip
0.6"
Top View
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
Vcc
D0
D1
WE
RAS
NC
A10
A0
A1
A2
A3
Vcc
Vss
D3
D2
CAS
OE
A9
A8
A7
A6
A5
A4
Vss
(a) 8-Mbit EPROM (b) 16-Mbit DRAM
24-Pin Dip
0.6"
Top View
Figure 5.4 Typical Memory Package Pins and Signals
NKK-HUST
Thit k m-dun nh bn dn
! Dung luong chip nh 2
n
x m bit
! Cn thit k d tng dung luong:
! Thit k tng d di t nh
! Thit k tng s luong t nh
! Thit k kt hop
NKK-HUST
Tng d di t nh
VD1:
! Cho chip nh SRAM 4K x 4 bit
! Thit k m-dun nh 4K x 8 bit
Gii:
12
x 4 bit
! chip nh c:
! 12 chn dja chi
! 4 chn d liu
! m-dun nh cn c:
! 12 chn dja chi
! 8 chn d liu
NKK-HUST
V du tng d di t nh
!
""
!
#
$
%
$
#
&'
() *)
&'
() *)
!
""
!
#
$
%
$
#
!
""
!
#
$
%
$
#
$
+
$
,
&'
()
*)
NKK-HUST
Bi ton tng d di t nh tng qut
! Cho chip nh 2
n
x mbit
! Thit k m-dun nh 2
n
x (k.m) bit
! Dng k chip nh

NKK-HUST
Tng s luong t nh
VD2:
Gii:
12
x 8 bit
! chip nh c:
! 12 chn dja chi
! 8 chn d liu
! Dung luong m-dun nh = 2
13
x 8 bit
! 13 chn dja chi
! 8 chn d liu
NKK-HUST
Tng s luong t nh
G A Y0 Y1
0 0 0 1
0 1 1 0
1 x 1 1
!""!#
$% $#
&'
() *)
!""!#
$% $#
B!
gi"i m
1! 2
!
,
-#
-"
!".
!""!#
$% $#
&'
() *)
() *)
NKK-HUST
Bi tp
1. Tng s luong t gp 4 ln:
2. Tng s luong t gp 8 ln:
3. Thit k kt hop:
NKK-HUST
B gii m 2"4
B! gi"i m
2 !4
!
#
$%
$&
'
$(
$)
G B A Y0 Y1 Y2 Y3
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 x x 1 1 1 1
NKK-HUST
Bi tp
! Tng s luong t nh gp 3 ln
! Tng s luong t nh gp 5, 6, 7 ln
NKK-HUST
2. Cc dc trung co bn ca b nh chnh
! Cha cc chuong trnh dang thuc hin v cc
d liu dang duoc s dung
! Tn tai trn moi h thng my tnh
! Bao gm cc ngn nh duoc dnh dja chi truc
tip bi CPU
! Dung luong ca b nh chnh nh hon khng
gian dja chi b nh m CPU qun l.
! Vic qun l logic b nh chnh tuy thuc vo
h diu hnh
NKK-HUST
T chc b nh dan xen (interleaved memory)
! rng ca bus d liu d trao di vi
b nh: m = 8, 16, 32, 64,128 ... bit
! Cc ngn nh duoc t chc theo byte
" t chc b nh vt l khc nhau
NKK-HUST
m=8bit " mt bng nh tuyn tnh
6
5
4
3
2
1
0
. . .
. . .
A
N-1
- A
0
D7 - D0
i
NKK-HUST
m = 16bit " hai bng nh dan xen
9
7
5
3
1
. . .
. . .
AN-1 - A1
D15 - D8
8
6
4
2
0
. . .
. . .
D7 - D0
2i 2i+1
B! t"o
tn hi#u
ch$n
byte
A0
B
W
BE1
BE0
B%ng 1 B%ng 0
BE0 BE1
1
1
0
0
BE1
1
0
1
0
BE0
khng ch$n
Ch$n byte th&p
Ch$n byte cao
Ch$n c' hai byte
Ch$n byte
C
Cc tn hi#u ch$n byte
NKK-HUST
m = 32bit " bn bng nh dan xen
17
13
9
5
1
. . .
. . .
AN-1 - A2
D15 - D8
16
12
8
4
0
. . .
. . .
D7 - D0
BE1 BE0
4i 4i+1
B! t"o
tn
hi#u
ch$n
byte
A0
B
W
BE1
19
15
11
7
3
. . .
. . .
D31-D24
18
14
10
6
2
. . .
. . .
D23-D16
BE3 BE2
4i+2 4i+3
A1
DW
BE0
BE2
BE3
b%ng 3 b%ng 2 b%ng 1 b%ng 0
NKK-HUST
m = 64bit " tm bng nh dan xen

17
9
1
. . .
. . .
AN-1 - A3
D15 - D8

16
8
0
. . .
. . .
D7 - D0
BE1 BE0
8i 8i+1

23
15
7
. . .
. . .
D63-D56
BE7
8i+7
b!ng 7 b!ng 1 b!ng 0
. . .
NKK-HUST
7.3. B nh dm nhanh (cache memory)
1. Nguyn tc chung ca cache
! Cache c tc d nhanh hon b nh chnh
! Cache duoc dt gia CPU v b nh chnh nhm
tng tc d CPU truy cp b nh
! Cache c th duoc dt trn chip CPU
cache CPU
B! nh"
chnh
truy#n theo t$ nh" truy#n theo block nh"
NKK-HUST
V du v thao tc ca cache
! CPU yu cu ni dung ca ngn nh
! CPU kim tra trn cache vi d liu ny
! Nu c, CPU nhn d liu t cache
(nhanh)
! Nu khng c, doc Block nh cha d
liu t b nh chnh vo cache
! Tip d chuyn d liu t cache vo
CPU
NKK-HUST
Cu trc chung ca cache / b nh chnh
L0
CPU
L1
L2
L3
Li
Lm-1
B0
B1
B2
B3
Bj
BP-1
Cache Tag
B! nh" chnh
. . .
. . .
. . .
. . .
NKK-HUST
Cu trc chung ca cache / b nh chnh (tip)
! B nh chnh c 2
N
byte nh
! B nh chnh v cache duoc chia thnh
cc khi c kch thuc bng nhau
! B nh chnh: B
0
, B
1
, B
2
, ... , B
p-1
(p Blocks)
! B nh cache: L
0
, L
1
, L
2
, ... , L
m-1
(m Lines)
! Kch thuc ca Block = 8,16,32,64,128 byte

NKK-HUST
Cu trc chung ca cache / b nh chnh (tip)
! Mt s Block ca b nh chnh duoc
nap vo cc Line ca cache.
! Ni dung Tag (th nh) cho bit Block
no ca b nh chnh hin dang duoc
cha Line d.
! Khi CPU truy nhp (doc/ghi) mt t nh,
c hai kh nng xy ra:
! T nh d c trong cache (cache hit)
! T nh d khng c trong cache (cache
miss).
NKK-HUST
2. Cc phuong php nh xa
(Chnh l cc phuong php t chc b
nh cache)
! nh xa truc tip
(Direct mapping)
! nh xa lin kt ton phn
(Fully associative mapping)
! nh xa lin kt tp hop
(Set associative mapping)
NKK-HUST
nh xa truc tip
! Mi Block ca b nh chnh chi c th duoc nap
vo mt Line ca cache:
! B
0
" L
0

! B
1
" L
1

! ....
! B
m-1
" L
m-1

! B
m
" L
0

! B
m+1
" L
1

! ....
! Tng qut
! B
j
chi c th nap vo L
j mod m

! m l s Line ca cache.
NKK-HUST
Minh hoa nh xa truc tip
Tag
Cache Tag
B! nh"
chnh
. . .
. . .
Line Word
Nbit #$a ch% b! nh"
T bit L bit Wbit
So snh
cache hit
L0
L1
Li
Lm-1
cache miss
. . .
. . .
B0
B1
Bj
Bm-1
X
X
NKK-HUST
c dim ca nh xa truc tip
! Mi mt dja chi N bit ca b nh chnh gm
ba trung:
! Trung Word gm W bit xc djnh mt t nh
trong Block hay Line:
2
W
= kch thuc ca Block hay Line
! Trung Line gm L bit xc djnh mt trong s cc
Line trong cache:
2
L
= s Line trong cache = m
! Trung Tag gm T bit:
T = N - (W+L)
! B so snh don gin
! Xc sut cache hit thp
NKK-HUST
nh xa lin kt ton phn
! Mi Block c th nap vo bt ky Line
no ca cache.
! ja chi ca b nh chnh bao gm hai
trung:
! Trung Word ging nhu trung hop
trn.
! Trung Tag dng d xc djnh Block ca
b nh chnh.
! Tag xc djnh Block dang nm Line d
NKK-HUST
Minh hoa nh xa lin kt ton phn
Tag
Cache
Tag
B! nh"
chnh
. . .
. . .
Word
N bit #$a ch% b! nh"
T bit Wbit
So snh
cache hit
L0
L1
Li
Lm-1
cache miss
. . .
. . .
B0
B1
Bj
Bm-1
X
X
NKK-HUST
c dim ca nh xa lin kt ton phn
! So snh dng thi vi tt c cc Tag "
mt nhiu thi gian
! Xc sut cache hit cao.
! B so snh phc tap.
NKK-HUST
nh xa lin kt tp hop
! Cache duoc chia thnh cc Tp (Set)
! Mi mt Set cha mt s Line
! V du:
! 4 Line/Set " 4-way associative mapping
! nh xa theo nguyn tc sau:
! B
0
" S
0
! B
1
" S
1
! B
2
" S
2
!
.......
NKK-HUST
Minh hoa nh xa lin kt tp hop
Tag
Cache Tag
B! nh"
chnh
. . .
Set Word
Nbit #$a ch% b! nh"
T bit S bit Wbit
So snh
cache hit
S0
S1
Sk
Sv-1
cache miss
X
X
L0
L1
L2
L3
L4
L5
L6
L7

. . .

. . .
B0
B1
B2
B3
B4
B5

. . .
NKK-HUST
c dim ca nh xa lin kt tp hop
! Kch thuc Block = 2
W
Word
! Trung Set c S bit dng d xc djnh
mt trong s V = 2
S
Set
! Trung Tag c T bit: T = N - (W+S)
! Tng qut cho c hai phuong php trn
! Thng thung 2,4,8,16Lines/Set
NKK-HUST
V du v nh xa dja chi
! Khng gian dja chi b nh chnh = 4GB
! Dung luong b nh cache l 256KB
! Kch thuc Line (Block) = 32byte.
! Xc djnh s bit ca cc trung dja chi
cho ba trung hop t chc:
! nh xa truc tip
! nh xa lin kt ton phn
! nh xa lin kt tp hop 4 dung
NKK-HUST
Vi nh xa truc tip
! B nh chnh = 4GB = 2
32
byte " N = 32 bit
! Cache = 256 KB = 2
18
byte.
! Line = 32 byte = 2
5
byte " W = 5 bit
! S Line trong cache = 2
18
/ 2
5
= 2
13
Line
" L = 13 bit
! T = 32 - (13 + 5) = 14 bit
!"#
!" $%&
$%&'
!' $%&
()*+
( $%&
NKK-HUST
Vi nh xa lin kt ton phn
32
byte " N = 32 bit
5
byte " W = 5 bit
! S bit ca trung Tag s l: T = 32 - 5 = 27 bit
!"#
!" $%&
$%&'
' $%&
NKK-HUST
Vi nh xa lin kt tp hop 4 dung
32
byte " N = 32 bit
5
byte " W = 5 bit
! S Line trong cache = 2
18
/ 2
5
= 2
13
Line
! Mt Set c 4 Line = 2
2
Line
" s Set trong cache = 2
13
/ 2
2
= 2
11
Set "
S = 11 bit
! S bit ca trung Tag s l: T = 32 - (11 + 5)
= 16 bit
!"#
!" $%&
$%&
!! $%&
'()*
' $%&
NKK-HUST
Bi tp
Gi thit rng my tnh c 128KB cache t
chc theo kiu nh xa lin kt tp hop 4-line.
Cache c tt c l 1024 Set t S0 dn
S1023. ja chi b nh chnh l 32-bit v dnh
dja chi cho tng byte.
a) Tnh s bit cho cc trung dja chi khi truy
nhp cache ?
b) Xc djnh byte nh c dja chi 003D02AF
(16)

duoc nh xa vo Set no ca cache ?
NKK-HUST
3. Thay th block trong cache
Vi nh xa truc tip:
! Khng phi lua chon
! Mi Block chi nh xa vo mt Line xc
djnh
! Thay th Block Line d
NKK-HUST
Thay th block trong cache (tip)
Vi nh xa lin kt: cn c thut gii thay th:
! Random: Thay th ngu nhin
! FIFO (First In First Out): Thay th Block no
nm lu nht trong Set d
! LFU (Least Frequently Used): Thay th Block
no trong Set c s ln truy nhp t nht trong
cng mt khong thi gian
! LRU (Least Recently Used): Thay th Block
trong Set tuong ng c thi gian lu nht khng
duoc tham chiu ti.
! Ti uu nht: LRU
NKK-HUST
4. Phuong php ghi d liu khi cache hit
! Ghi xuyn qua (Write-through):
! ghi c cache v c b nh chnh
! tc d chm
! Ghi tr sau (Write-back):
! chi ghi ra cache
! tc d nhanh
! khi Block trong cache bj thay th cn phi
ghi tr c Block v b nh chnh
NKK-HUST
7.4. B nh ngoi
Cc kiu b nh ngoi
! Bng t
! a t
! a quang
! B nh Flash
NKK-HUST
a t
188 CHAPTER 6 / EXTERNAL MEMORY
Figure 6.2 depicts this data layout. Adjacent tracks are separated by gaps. This
prevents, or at least minimizes, errors due to misalignment of the head or simply
interference of magnetic fields.
Data are transferred to and from the disk in sectors (Figure 6.2). There are
typically hundreds of sectors per track, and these may be of either fixed or variable
length. In most contemporary systems, fixed-length sectors are used, with 512 bytes
being the nearly universal sector size. To avoid imposing unreasonable precision
requirements on the system, adjacent sectors are separated by intratrack (intersec-
tor) gaps.
A bit near the center of a rotating disk travels past a fixed point (such as a read
write head) slower than a bit on the outside. Therefore, some way must be found
to compensate for the variation in speed so that the head can read all the bits at the
same rate. This can be done by increasing the spacing between bits of information
recorded in segments of the disk. The information can then be scanned at the same
rate by rotating the disk at a fixed speed, known as the constant angular velocity
(CAV). Figure 6.3a shows the layout of a disk using CAV. The disk is divided into
a number of pie-shaped sectors and into a series of concentric tracks. The advan-
tage of using CAV is that individual blocks of data can be directly addressed by
track and sector. To move the head from its current location to a specific address, it
only takes a short movement of the head to a specific track and a short wait for the
proper sector to spin under the head. The disadvantage of CAV is that the amount
of data that can be stored on the long outer tracks is the only same as what can be
stored on the short inner tracks.
Figure 6.2 Disk Data Layout
S6
S
4
S
5
S 3
S 2
S
1
S
N

S6

S
5
S
4
S 3
S 2
S
1
S
N
Intersector gap
Intertrack gap
Sectors Tracks
NKK-HUST
Nhiu da
6.1 / MAGNETIC DISK 191
tracks that are of equal distance from the center of the disk. The set of all the tracks
in the same relative position on the platter is referred to as a cylinder. For example,
all of the shaded tracks in Figure 6.6 are part of one cylinder.
Finally, the head mechanism provides a classification of disks into three types.
Traditionally, the read-write head has been positioned a fixed distance above the
platter, allowing an air gap. At the other extreme is a head mechanism that actually
comes into physical contact with the medium during a read or write operation. This
mechanism is used with the floppy disk, which is a small, flexible platter and the
least expensive type of disk.
Surface 2
Surface 1
Surface 0
Surface 4
Surface 3
Surface 6
Surface 5
Surface 8
Surface 7
Platter
Spindle Boom
Readwrite head (1 per surface) Direction of
arm motion
Surface 9
Figure 6.5 Components of a Disk Drive
Figure 6.6 Tracks and Cylinders
NKK-HUST
da cng
! Mt hoc nhiu da
! Thng dung
! Dung luong tng ln rt nhanh
! 1993: ~ 200MB
! 2003: ~ 40GB
! 2013: ~ 500GB - 1TB
! Tc d doc/ghi nhanh
! R tin
NKK-HUST
H thng luu tr dung luong ln: RAID
! Redundant Array of Inexpensive Disks
! (Redundant Array of Independent Disks)
! Tp cc da cng vt l duoc OS coi nhu mt
logic duy nht " dung luong ln
! D liu duoc luu tr phn tn trn cc da
vt l " truy cp song song (nhanh)
! Luu tr thm thng tin du tha, cho php khi
phuc lai thng tin trong trung hop da bj hng
" an ton thng tin
! 7 loai ph bin (RAID 0 6)
NKK-HUST
RAID 0, 1, 2
RAID Level 0
RAID level 0 is not a true member of the RAID family because it does not include
redundancy to improve performance. However, there are a few applications, such
as some on supercomputers in which performance and capacity are primary con-
cerns and low cost is more important than improved reliability.
For RAID 0, the user and system data are distributed across all of the disks
in the array. This has a notable advantage over the use of a single large disk: If two
-different I/O requests are pending for two different blocks of data, then there is a
good chance that the requested blocks are on different disks. Thus, the two requests
can be issued in parallel, reducing the I/O queuing time.
But RAID0, as with all of the RAIDlevels, goes further than simply distribut-
ing the data across a disk array: The data are striped across the available disks. This is
best understood by considering Figure 6.9. All of the user and systemdata are viewed
as being stored on a logical disk. The logical disk is divided into strips; these strips
may be physical blocks, sectors, or some other unit. The strips are mapped round
robin to consecutive physical disks in the RAID array. A set of logically consecu-
tive strips that maps exactly one strip to each array member is referred to as a stripe.
In an n-disk array, the first n logical strips are physically stored as the first strip on
each of the n disks, forming the first stripe; the second n strips are distributed as the
strip 12
(a) RAID 0 (Nonredundant)
strip 8
strip 4
strip 0
strip 13
strip 9
strip 5
strip 1
strip 14
strip 10
strip 6
strip 2
strip 15
strip 11
strip 7
strip 3
strip 12
(b) RAID 1 (Mirrored)
strip 8
strip 4
strip 0
strip 13
strip 9
strip 5
strip 1
strip 14
strip 10
strip 6
strip 2
strip 15
strip 11
strip 7
strip 3
strip 12
strip 8
strip 4
strip 0
strip 13
strip 9
strip 5
strip 1
strip 14
strip 10
strip 6
strip 2
(c) RAID 2 (Redundancy through Hamming code)
b0 b1 b2 b3 f0(b) f1(b) f2(b)
strip 15
strip 11
strip 7
strip 3
Figure 6.8 RAID Levels
NKK-HUST
RAID 3 & 4
6.2 / RAID 199
second strips on each disk; and so on. The advantage of this layout is that if a single
I/O request consists of multiple logically contiguous strips, then up to n strips for
that request can be handled in parallel, greatly reducing the I/O transfer time.
Figure 6.9 indicates the use of array management software to map between
logical and physical disk space. This software may execute either in the disk subsystem
or in a host computer.
block 12
(e) RAID 4 (Block-level parity)
block 8
block 4
block 0
block 13
block 9
block 5
block 1
block 14
block 10
block 6
block 2
block 15
block 7
block 3
P(12-15)
P(8-11)
P(4-7)
P(0-3)
block 12
block 8
block 4
block 0
block 9
block 5
block 1
block 13
block 6
block 2
block 14
block 10
block 3
block 15
P(16-19)
P(12-15)
P(8-11)
P(4-7)
block 16 block 17 block 18 block 19
block 11
block 7
(f ) RAID 5 (Block-level distributed parity)
(d) RAID 3 (Bit-interleaved parity)
b0 b1 b2 b3 P(b)
P(0-3)
block 11
block 12
(g) RAID 6 (Dual redundancy)
block 8
block 4
block 0
P(12-15)
block 9
block 5
block 1
Q(12-15)
P(8-11)
block 6
block 2
block 13
P(4-7)
block 3
block 14
block 10
Q(4-7)
P(0-3)
Q(8-11)
block 15
block 7
Q(0-3)
block 11
Figure 6.8 RAID Levels (continued)
NKK-HUST
RAID 5 & 6
6.2 / RAID 199
second strips on each disk; and so on. The advantage of this layout is that if a single
I/O request consists of multiple logically contiguous strips, then up to n strips for
that request can be handled in parallel, greatly reducing the I/O transfer time.
Figure 6.9 indicates the use of array management software to map between
logical and physical disk space. This software may execute either in the disk subsystem
or in a host computer.
block 12
(e) RAID 4 (Block-level parity)
block 8
block 4
block 0
block 13
block 9
block 5
block 1
block 14
block 10
block 6
block 2
block 15
block 7
block 3
P(12-15)
P(8-11)
P(4-7)
P(0-3)
block 12
block 8
block 4
block 0
block 9
block 5
block 1
block 13
block 6
block 2
block 14
block 10
block 3
block 15
P(16-19)
P(12-15)
P(8-11)
P(4-7)
block 16 block 17 block 18 block 19
block 11
block 7
(f ) RAID 5 (Block-level distributed parity)
(d) RAID 3 (Bit-interleaved parity)
b0 b1 b2 b3 P(b)
P(0-3)
block 11
block 12
(g) RAID 6 (Dual redundancy)
block 8
block 4
block 0
P(12-15)
block 9
block 5
block 1
Q(12-15)
P(8-11)
block 6
block 2
block 13
P(4-7)
block 3
block 14
block 10
Q(4-7)
P(0-3)
Q(8-11)
block 15
block 7
Q(0-3)
block 11
Figure 6.8 RAID Levels (continued)
NKK-HUST
nh xa d liu ca RAID 0
RAID 0 FOR HIGH DATA TRANSFER CAPACITY The performance of any of the
RAID levels depends critically on the request patterns of the host system and on
the layout of the data. These issues can be most clearly addressed in RAID 0, where
the impact of redundancy does not interfere with the analysis. First, let us consider
the use of RAID0 to achieve a high data transfer rate. For applications to experience
a high transfer rate, two requirements must be met. First, a high transfer capacity
must exist along the entire path between host memory and the individual disk drives.
This includes internal controller buses, host system I/O buses, I/O adapters, and host
memory buses.
The second requirement is that the application must make I/O requests that
drive the disk array efficiently. This requirement is met if the typical request is for
large amounts of logically contiguous data, compared to the size of a strip. In this
case, a single I/O request involves the parallel transfer of data from multiple disks,
increasing the effective transfer rate compared to a single-disk transfer.
RAID 0 FOR HIGH I/O REQUEST RATE In a transaction-oriented environment,
the user is typically more concerned with response time than with transfer rate. For
an individual I/Orequest for a small amount of data, the I/Otime is dominated by the
motion of the disk heads (seek time) and the movement of the disk (rotational latency).
In a transaction environment, there may be hundreds of I/O requests per sec-
ond. A disk array can provide high I/O execution rates by balancing the I/O load
across multiple disks. Effective load balancing is achieved only if there are typically
strip 12
strip 8
strip 4
strip 0
Physical
disk 0
strip 3
strip 4
strip 5
strip 6
strip 7
strip 8
strip 9
strip 10
strip 11
strip 12
strip 13
strip 14
strip 15
strip 2
strip 1
strip 0
Logical disk
Physical
disk 1
Physical
disk 2
Physical
disk 3
strip 13
strip 9
strip 5
strip 1
strip 14
strip 10
strip 6
strip 2
strip 15
strip 11
strip 7
strip 3
Array
management
software
Figure 6.9 Data Mapping for a RAID Level 0 Array
NKK-HUST
a quang
! CD (Compact Disc)
! Dung luong thng dung 650MB
! Tc d doc co s 150KByte/s.
! Tc d bi, v du: 48x, 52x,...
! DVD
! Digital Video Disc hoc Digital Versatile Disk
! Ghi mt hoc hai mt
! Mt hoc hai lp trn mt mt
! Thng dung: 4,7GB/lp
NKK-HUST
B nh flash
! B nh bn dn
! Khng kh bin
! Tc d nhanh
! Cc dang:
! nh kt ni qua cng USB
! Th nh
! SSD (Solid State Drive): kt
ni nhiu chip nh flash v cho
php truy cp song song
NKK-HUST
7.5. B nh o (Virtual Memory)
! Khi nim b nh o: gm b nh
chnh v b nh ngoi m duoc CPU
coi nhu l mt b nh duy nht (b nh
chnh).
! Cc k thut thuc hin b nh o:
! K thut phn trang: Chia khng gian dja
chi b nh thnh cc trang nh c kch
thuc bng nhau v nm lin k nhau
Thng dung: kch thuc trang = 4KBytes
! K thut phn doan: Chia khng gian nh
thnh cc doan nh c kch thuc thay
di, cc doan nh c th gi ln nhau.
NKK-HUST
Phn trang
! Phn chia b nh thnh cc phn c kch
thuc bng nhau goi l cc khung trang
! Chia chuong trnh (tin trnh) thnh cc trang
! Cp pht s hiu khung trang yu cu cho
tin trnh
! HH duy tr danh sch cc khung trang nh
trng
! Tin trnh khng yu cu cc khung trang lin
tip
! S dung bng trang d qun l
NKK-HUST
Cp pht cc khung trang
8.3 / MEMORY MANAGEMENT 287
But these addresses are not fixed. They will change each time a process is
swapped in. To solve this problem, a distinction is made between logical addresses
and physical addresses. A logical address is expressed as a location relative to the
beginning of the program. Instructions in the programcontain only logical addresses.
A physical address is an actual location in main memory. When the processor exe-
cutes a process, it automatically converts from logical to physical address by adding
the current starting location of the process, called its base address, to each logical
address. This is another example of a processor hardware feature designed to meet
an OS requirement. The exact nature of this hardware feature depends on the mem-
ory management strategy in use. We will see several examples later in this chapter.
Paging
Both unequal fixed-size and variable-size partitions are inefficient in the use of
memory. Suppose, however, that memory is partitioned into equal fixed-size chunks
that are relatively small, and that each process is also divided into small fixed-size
chunks of some size. Then the chunks of a program, known as pages, could be
assigned to available chunks of memory, known as frames, or page frames. At most,
then, the wasted space in memory for that process is a fraction of the last page.
Figure 8.15 shows an example of the use of pages and frames. At a given point
in time, some of the frames in memory are in use and some are free. The list of free
frames is maintained by the OS. Process A, stored on disk, consists of four pages.
14
13
15
16
In
use
Main
memory
(a) Before (b) After
Process A
Free frame list
13
14
15
18
20
Free frame list
20
Process A
page table
18
13
14
15
Page 0
Page 1
Page 2
Page 3
In
use
In
use
17
18
19
20
14
13
15
16
In
use
In
use
Main
memory
Page 0
of A
Page 3
of A
Page 2
of A
Page 1
of A
In
use
17
18
19
20
Process A
Page 0
Page 1
Page 2
Page 3
Figure 8.15 Allocation of Free Frames
NKK-HUST
ja chi logic v dja chi vt l ca phn trang
288 CHAPTER 8 / OPERATING SYSTEM SUPPORT
When it comes time to load this process, the OS finds four free frames and loads the
four pages of the process A into the four frames.
Now suppose, as in this example, that there are not sufficient unused con-
tiguous frames to hold the process. Does this prevent the OS from loading A?
The answer is no, because we can once again use the concept of logical address. A
simple base address will no longer suffice. Rather, the OS maintains a page table
for each process. The page table shows the frame location for each page of the
process. Within the program, each logical address consists of a page number and
a relative address within the page. Recall that in the case of simple partitioning, a
logical address is the location of a word relative to the beginning of the program;
the processor translates that into a physical address. With paging, the logical-
to-physical address translation is still done by processor hardware. The processor
must know how to access the page table of the current process. Presented with a
logical address (page number, relative address), the processor uses the page table
to produce a physical address (frame number, relative address). An example is
shown in Figure 8.16.
This approach solves the problems raised earlier. Main memory is divided
into many small equal-size frames. Each process is divided into frame-size pages:
smaller processes require fewer pages, larger processes require more. When a
process is brought in, its pages are loaded into available frames, and a page table
is set up.
30
18
13
14
15
1
Page
number
Relative address
within page
Logical
address
Physical
address
Main
memory
Process A
page table
30
Page 3
of A
Page 0
of A
Page 2
of A
Page 1
of A
13
14
15
16
17
18
13
Frame
number
Relative address
within frame
Figure 8.16 Logical and Physical Addresses
NKK-HUST
Nguyn tc lm vic ca b nh o phn trang
! Phn trang theo yu cu
! Khng yu cu tt c cc trang ca tin trnh nm
trong b nh
! Chi nap vo b nh nhng trang duoc yu cu
! Li trang
! Trang duoc yu cu khng c trong b nh
! HH cn hon di trang yu cu vo
! C th cn hon di mt trang no d ra d ly
ch
! Cn chon trang d dua ra
NKK-HUST
Tht bai
! Qu nhiu tin trnh trong b nh qu nh
! HH tiu tn ton b thi gian cho vic hon
di
! C t hoc khng c cng vic no duoc thuc
hin
! a lun lun sng
! Gii php:
! Thut ton thay trang
! Gim bt s tin trnh dang chay
! Thm b nh
NKK-HUST
Loi ch
! Khng cn ton b tin trnh nm trong
b nh d chay
! C th hon di trang duoc yu cu
! Nhu vy c th chay nhng tin trnh
ln hon tng b nh sn dng
! B nh chnh duoc goi l b nh thuc
! Ngui dng cm gic b nh ln hon
b nh thuc
NKK-HUST
Cu trc bng trang
8.3 / MEMORY MANAGEMENT 291
inverted page table for each real memory page frame rather than one per virtual
page. Thus a fixed proportion of real memory is required for the tables regardless of
the number of processes or virtual pages supported. Because more than one virtual
address may map into the same hash table entry, a chaining technique is used for
managing the overflow. The hashing technique results in chains that are typically
shortbetween one and two entries. The page tables structure is called inverted
because it indexes page table entries by frame number rather than by virtual page
number.
Translation Lookaside Buffer
In principle, then, every virtual memory reference can cause two physical mem-
ory accesses: one to fetch the appropriate page table entry, and one to fetch the
desired data. Thus, a straightforward virtual memory scheme would have the effect
of doubling the memory access time. To overcome this problem, most virtual
memory schemes make use of a special cache for page table entries, usually called
a translation lookaside buffer (TLB). This cache functions in the same way as a
memory cache and contains those page table entries that have been most recently
used. Figure 8.18 is a flowchart that shows the use of the TLB. By the principle of
locality, most virtual memory references will be to locations in recently used pages.
Therefore, most references will involve page table entries in the cache. Studies of
the VAX TLB have shown that this scheme can significantly improve performance
[CLAR85, SATY81].
Page # Offset
Frame #
m bits
m bits
n bits
n bits
Virtual address
Hash
function
Page #
Process
ID
Control
bits
Chain
Inverted page table
(one entry for each
physical memory frame)
Real address
Offset
i
0
j
2
m
1
Figure 8.17 Inverted Page Table Structure
NKK-HUST
B nh trn my tnh PC
! B nh cache: tch hop trn chip vi
x l:
! L1: cache lnh v cache d liu
! L2, L3
! B nh chnh: Tn tai dui dang cc
m-dun nh RAM
NKK-HUST
B nh trn PC (tip)
! ROM BIOS cha cc chuong trnh sau:
! Chuong trnh POST (Power On Self Test)
! Chuong trnh CMOS Setup
! Chuong trnh Bootstrap loader
! Cc trnh diu khin vo-ra co bn (BIOS)
! CMOS RAM:
! Cha thng tin cu hnh h thng
! ng h h thng
! C pin nui ring
! Video RAM: qun l thng tin ca mn hnh
! Cc loai b nh ngoi

NKK-HUST
H%t ch!"ng 7
NKK-HUST
Kin trc my tnh
Ch!"ng 8
H$ TH)NG VO-RA

Nguy!n Kim Khnh
NKK-HUST
Ni dung hoc phn
Chuong 6. B x l

NKK-HUST
8.1. Tng quan v h thng vo-ra
8.2. Cc phuong php diu khin vo-ra
8.3. Ni ghp thit bj ngoai vi

Ni dung ca chuong 8
NKK-HUST
8.1. Tng quan v h thng vo-ra
1. Gii thiu chung
! Chc nng ca h thng vo-ra: Trao
di thng tin gia my tnh vi th
gii bn ngoi
! Cc thao tc co bn:
! Vo d liu (Input)
! Ra d liu (Output)
! Cc thnh phn chnh:
! Cc thit bj ngoai vi
! Cc m-dun vo-ra
NKK-HUST
Cu trc co bn ca h thng vo-ra
M-!un
vo-ra
M-!un
vo-ra
C"ng
vo-
ra
Thi#t b$
ngo%i vi
Thi#t b$
ngo%i vi
Thi#t b$
ngo%i vi
n&i ghp
v'i CPU
v b(
nh'
chnh
C"ng
vo-
ra
C"ng
vo-
ra
bus
h)
th&ng
NKK-HUST
c dim ca h thng vo-ra
! Tn tai da dang cc thit bj ngoai vi
khc nhau v:
! Nguyn tc hoat dng
! Tc d
! Khun dang d liu
! Tt c cc thit bj ngoai vi du chm
hon CPU v RAM
" Cn c cc m-dun vo-ra d ni ghp
cc thit bj ngoai vi vi CPU v b nh
chnh
NKK-HUST
2. Cc thit bj ngoai vi
! Chc nng: chuyn di d liu gia
bn trong v bn ngoi my tnh
! Phn loai:
! Thit bj ngoai vi giao tip ngui-my:
Bn phm, Mn hnh, My in,...
! Thit bj ngoai vi giao tip my-my: gm
cc thit bj theo di v kim tra
! Thit bj ngoai vi truyn thng: Modem,
Network Interface Card (NIC)
NKK-HUST
Mt s thit bj ngoai vi
with others throughput is crucial. Furthermore, performance depends on many
aspects of the system: the device characteristics, the connection between the device
and the rest of the system, the memory hierarchy, and the operating sys tem. All of
the components, from the individual I/O devices to the processor to the system
software, will affect the dependability, expandability, and performance of tasks that
include I/O. Figure 6.1 shows the structure of a simple system with its I/O.
I/O devices are incredibly diverse. Three characteristics are useful in organizing
this wide variety:
Behavior: Input (read once), output (write only, cannot be read), or storage
(can be reread and usually rewritten).
Partner: Either a human or a machine is at the other end of the I/O device,
either feeding data on input or reading data on output.
Data rate: The peak rate at which data can be transferred between the I/O
device and the main memory or processor. It is useful to know the maximum
demand the device may generate when designing an I/O system.
For example, a keyboard is an input device used by a human with a peak data rate
of about 10 bytes per second. Figure 6.2 shows some of the I/O devices connected
to computers.
Device Behavior Partner Data rate (Mbit/sec)
Keyboard Input Human 30,000.0001
Mouse Input Human 30,000.0038
Voice input Input Human 30,000.2640
Sound input Input Machine 30,003.0000
Scanner Input Human 30,003.2000
Voice output Output Human 30,000.2640
Sound output Output Human 30,008.0000
Laser printer Output Human 30,003.2000
Graphics display Output Human 800.00008000.0000
Cable modem Input or output Machine 0.12806.0000
Network/LAN Input or output Machine 100.000010000.0000
Network/wireless LAN Input or output Machine 11.000054.0000
Optical disk Storage Machine 30,080.0000220.0000
Magnetic tape Storage Machine 005.0000120.0000
Flash memory Storage Machine 32.0000200.0000
Magnetic disk Storage Machine 800.00003000.0000
FIGURE 6.2 The diversity of I/O devices. I/O devices can be distinguished by whether they serve as
input, output, or storage devices; their communication partner (people or other computers); and their peak
communication rates. The data rates span eight orders of magnitude. Note that a network can be an input or
an output device, but cannot be used for storage. Transfer rates for devices are always quoted in base 10, so
that 10 Mbit/sec = 10,000,000 bits/sec.
6.1 Introduction 571
NKK-HUST
Cu trc chung ca thit bj ngoai vi
B!
"#m
d$
li#u
Kh%i logic "i&u khi'n
B! chuy'n "(i
tn hi#u
(Transducer)
D$ li#u t)/"*n
m-"un vo-ra
Tn hi#u
"i&u khi'n
Tn hi#u
tr+ng thi
D$ li#u "*n/t)
bn ngoi
NKK-HUST
Cc thnh phn ca thit bj ngoai vi
! B chuyn di tn hiu: chuyn di d
liu gia bn ngoi v bn trong my
tnh
! B dm d liu: dm d liu khi truyn
gia m-dun vo-ra v thit bj ngoai vi
! Khi logic diu khin: diu khin hoat
dng ca thit bj ngoai vi dp ng theo
yu cu t m-dun vo-ra
NKK-HUST
3. M-dun vo-ra
! Chc nng ca m-dun vo-ra:
! iu khin v djnh thi
! Trao di thng tin vi CPU hoc b nh
chnh
! Trao di thng tin vi thit bj ngoai vi
! m gia bn trong my tnh vi thit bj
ngoai vi
! Pht hin li ca thit bj ngoai vi
NKK-HUST
Cu trc chung ca m-dun vo-ra
Thanh
ghi
!"m
d# li"u
Kh$i logic
!i%u khi&n
C'ng
n$i
ghp
vo-ra
Cc !()ng d# li"u
!i%u khi&n
d# li"u
Cc !()ng !*a ch+
Cc !()ng !i%u khi&n
tr,ng thi
Thanh ghi tr,ng thi/
!i%u khi&n
C'ng
n$i
ghp
vo-ra
!i%u khi&n
d# li"u
tr,ng thi
Bus d# li"u bn trong
NKK-HUST
Cc thnh phn ca m-dun vo-ra
! Thanh ghi dm d liu: dm d liu
trong qu trnh trao di
! Cc cng vo-ra (I/O Port): kt ni vi
thit bj ngoai vi, mi cng c mt dja chi
xc djnh
! Thanh ghi trang thi/diu khin: luu gi
thng tin trang thi/diu khin cho cc
cng vo-ra
! Khi logic diu khin: diu khin m-
dun vo-ra
NKK-HUST
4. ja chi ha cng vo-ra
Khng gian dja chi ca b x l
Khng gian !"a ch#
b$ nh%
Khng gian !"a
ch# vo-ra
N bit N1 bit
.
.
.
000...101
000...100
000...011
000...010
000...001
000...000
.
.
.
111...111
.
.
.
00...11
00...10
00...01
00...00
.
.
.
11...11
NKK-HUST
Khng gian dja chi ca b x l (tip)
! Mt s b x l chi qun l duy nht mt
khng gian dja chi:
! khng gian dja chi b nh: 2
N
dja chi
! V du:
! Cc b x l 680x0 (Motorola)
! Cc b x l theo kin trc RISC: MIPS,
NKK-HUST
Khng gian dja chi ca b x l (tip)
! Mt s b x l qun l hai khng gian dja chi
tch bit:
! Khng gian dja chi b nh: 2
N
dja chi
! Khng gian dja chi vo-ra: 2
N1
dja chi
! C tn hiu diu khin phn bit truy nhp khng
gian dja chi
! Tp lnh c cc lnh vo-ra chuyn dung
! V du: Pentium (Intel)
! khng gian dja chi b nh = 2
32
byte = 4GB
! khng gian dja chi vo-ra = 2
16
byte = 64KB
! Tn hiu diu khin
! Lnh vo-ra chuyn dung: IN, OUT
M/IO
NKK-HUST
Cc phuong php dja chi ho cng vo-ra
! Vo-ra ring bi/t
(Isolated IO hay IO mapped IO)
! Vo-ra theo b,n 01 b' nh2
(Memory mapped IO)

NKK-HUST
Vo-ra ring bit
! Cng vo-ra duoc dnh dja chi theo
khng gian dja chi vo-ra
! CPU trao di d liu vi cng vo-ra
thng qua cc lnh vo-ra chuyn dung
(IN, OUT)
! Chi c th thuc hin trn cc h thng c
qun l khng gian dja chi vo-ra ring
bit
NKK-HUST
Vo-ra theo bn d b nh
! Cng vo-ra duoc dnh dja chi theo
khng gian dja chi b nh
! Vo-ra ging nhu doc/ghi b nh
! CPU trao di d liu vi cng vo-ra
thng qua cc lnh truy nhp d liu b
nh
! C th thuc hin trn moi h thng
NKK-HUST
8.2. Cc phuong php diu khin vo-ra
! Vo-ra bng chuong trnh
(Programmed IO)
! Vo-ra diu khin bng ngt
(Interrupt Driven IO)
! Truy nhp b nh truc tip - DMA
(Direct Memory Access)
NKK-HUST
Ba k thut thuc hin vo mt khi d liu
230 CHAPTER 7 / INPUT/OUTPUT
Figure 7.4a gives an example of the use of programmed I/Oto read in a block of
data from a peripheral device (e.g., a record from tape) into memory. Data are read
in one word (e.g., 16 bits) at a time. For each word that is read in, the processor must
remain in a status-checking cycle until it determines that the word is available in the
I/O modules data register. This flowchart highlights the main disadvantage of this
technique: it is a time-consuming process that keeps the processor busy needlessly.
I/O Instructions
With programmed I/O, there is a close correspondence between the I/O-related
instructions that the processor fetches frommemory and the I/Ocommands that the
processor issues to an I/O module to execute the instructions. That is, the instruc-
tions are easily mapped into I/O commands, and there is often a simple one-to-one
relationship. The form of the instruction depends on the way in which external
devices are addressed.
Typically, there will be many I/O devices connected through I/O modules to
the system. Each device is given a unique identifier or address. When the processor
issues an I/O command, the command contains the address of the desired device.
Thus, each I/O module must interpret the address lines to determine if the com-
mand is for itself.
Issue read
command to
I/O module
Read status
of I/O
module
Check
Status
Read word
from I/O
module
Write word
into memory
Done?
Next instruction
(a) Programmed I/O
Error
condition
Ready Ready
Yes Yes
No
Not
ready
Issue read
command to
I/O module
Do something
else
Interrupt
Read status
of I/O
module
Check
status
Read word
from I/O
module
Write word
into memory
Done?
Next instruction
(b) Interrupt-Driven I/O
Do something
else
Interrupt
Error
condition
No
Issue read
block command
to I/O module
Read status
of DMA
module
Next instruction
(c) Direct Memory Access
CPU DMA
DMA CPU
CPU I/O
CPU I/O
I/O CPU
I/O CPU
I/O CPU
CPU Memory
I/O CPU
CPU Memory
Figure 7.4 Three Techniques for Input of a Block of Data
NKK-HUST
1. Vo-ra bng chuong trnh
! Nguyn tc chung: CPU diu khin truc
tip vo-ra bng chuong trnh " cn
phi lp trnh vo-ra.
NKK-HUST
Cc tn hiu diu khin vo-ra
! Tn hiu !i"u khi#n (Control): kch hoat thit
bj ngoai vi
! Tn hiu ki#m tra (Test): kim tra trang thi
ca m-dun vo-ra v thit bj ngoai vi
! Tn hiu diu khin !$c (Read): yu cu m-
dun vo-ra nhn d liu t thit bj ngoai vi v
dua vo thanh ghi dm d liu, ri CPU
nhn d liu d
! Tn hiu diu khin ghi (Write): yu cu m-
dun vo-ra ly d liu trn bus d liu dua
dn thanh ghi dm d liu ri chuyn ra thit
bj ngoai vi
NKK-HUST
Cc lnh vo-ra
! Vi vo-ra ring bit: s dung cc lnh
vo-ra chuyn dung (IN, OUT).
! Vi vo-ra theo bn d b nh: s
dung cc lnh trao di d liu vi b
nh d trao di d liu vi cng vo-ra.
NKK-HUST
Luu d doan chuong trnh vo-ra
!"c tr#ng thi
c$a TBNV
Trao %&i d' li(u
v)i TBNV
TBNV s*n
sng?
Y
N
NKK-HUST
Hoat dng ca vo-ra bng chuong trnh
! CPU yu cu thao tc vo-ra
! M-dun vo-ra thuc hin thao tc
! M-dun vo-ra thit lp cc bit trang
thi
! CPU kim tra cc bit trang thi:
! Nu chua sn sng th quay lai kim tra
! Nu sn sng th chuyn sang trao di d
liu vi m-dun vo-ra
NKK-HUST
c dim
! Vo-ra do mun ca ngui lp trnh
! CPU truc tip diu khin vo-ra
! CPU doi m-dun vo-ra " tiu tn thi
gian ca CPU
NKK-HUST
2. Vo-ra diu khin bng ngt
! Nguyn tc chung:
! CPU khng phi doi trang thi sn sng
ca m-dun vo-ra, CPU thuc hin mt
chuong trnh no d
! Khi m-dun vo-ra sn sng th n pht tn
hiu ngt CPU
! CPU thuc hin chuong trnh con vo-ra
tuong ng d trao di d liu
! CPU tr lai tip tuc thuc hin chuong trnh
dang bj ngt
NKK-HUST
Chuyn diu khin dn chuong trnh con ngt
l!nh i+1
l!nh i
l!nh
l!nh
l!nh
l!nh
Ng"t # $y
. . .
l!nh
l!nh
l!nh
RETURN
. . .
l!nh
l!nh
Ch%&ng trnh
$ang th'c hin
Ch%&ng trnh con
ph(c v( ng"t
NKK-HUST
Hoat dng vo d liu: nhn t m-dun vo-ra
! M-dun vo-ra nhn tn hiu diu khin
&.c t CPU
! M-dun vo-ra nhn d liu t thit bj
ngoai vi, trong khi d CPU lm vic
khc
! Khi d c d liu " m-dun vo-ra pht
tn hiu ngt CPU
! CPU yu cu d liu
! M-dun vo-ra chuyn d liu dn CPU

NKK-HUST
Hoat dng vo d liu: nhn t CPU
! Pht tn hiu diu khin !$c
! Lm vic khc
! Cui mi chu trnh lnh, kim tra tn
hiu ngt
! Nu bj ngt:
! Ct ng cnh (ni dung cc thanh ghi)
! Thuc hin chuong trnh con ngt d vo
d liu
! Khi phuc ng cnh ca chuong trnh
dang thuc hin
NKK-HUST
Cc vn d ny sinh khi thit k
! Lm th no d xc djnh duoc m-dun
vo-ra no pht tn hiu ngt ?
! CPU lm nhu th no khi c nhiu yu
cu ngt cng xy ra ?
NKK-HUST
Cc phuong php ni ghp ngt
! S dung nhiu dung yu cu ngt
! Hi vng bng phn mm (Software
Poll)
! Hi vng bng phn cng (Daisy Chain
or Hardware Poll)
! S dung b diu khin ngt (PIC)
NKK-HUST
Nhiu dung yu cu ngt
! Mi m-dun vo-ra duoc ni vi mt dung yu cu
ngt
! CPU phi c nhiu dung tn hiu yu cu ngt
! Han ch s luong m-dun vo-ra
! Cc dung ngt duoc qui djnh mc uu tin
CPU
M-!un
vo-ra
INTR3
INTR2
INTR1
INTR0
Thanh
ghi
yu
c"u
ng#t
M-!un
vo-ra
M-!un
vo-ra
M-!un
vo-ra
NKK-HUST
Hi vng bng phn mm
! CPU thuc hin phn mm hi ln luot tng
m-dun vo-ra
! Chm
! Th tu cc m-dun duoc hi vng chnh l
th tu uu tin
CPU
M-!un
vo-ra
INTR
C"
ng#t
M-!un
vo-ra
M-!un
vo-ra
M-!un
vo-ra
NKK-HUST
Hi vng bng phn cng
CPU
M-!un
vo-ra
INTR C"
ng#t
Bus d$ li%u
M-!un
vo-ra
M-!un
vo-ra
M-!un
vo-ra
INTA
NKK-HUST
Kim tra vng bng phn cng (tip)
! CPU pht tn hiu chp nhn ngt
(INTA) dn m-dun vo-ra du tin
! Nu m-dun vo-ra d khng gy ra
ngt th n gi tn hiu dn m-dun k
tip cho dn khi xc djnh duoc m-dun
gy ngt
! Th tu cc m-dun vo-ra kt ni trong
chui xc djnh th tu uu tin
NKK-HUST
B diu khin ngt lp trnh duoc
! PIC Programmable Interrupt Controller
! PIC c nhiu dung vo yu cu ngt c qui
djnh mc uu tin
! PIC chon mt yu cu ngt khng bj cm c
mc uu tin cao nht gi ti CPU
CPU
M-!un
vo-ra
INTR n
INTRn-1
INTR1
INTR0
M-!un
vo-ra
M-!un
vo-ra
M-!un
vo-ra
PIC
. . .
INTR
INTA
Bus d" li#u
NKK-HUST
c dim ca vo-ra diu khin bng ngt
! C su kt hop gia phn cng v phn
mm
! Phn cng: gy ngt CPU
! Phn mm: trao di d liu
! CPU truc tip diu khin vo-ra
! CPU khng phi doi m-dun vo-ra "
hiu qu s dung CPU tt hon
NKK-HUST
3. DMA (Direct Memory Access)
! Vo-ra bng chuong trnh v bng ngt
do CPU truc tip diu khin:
! Chim thi gian ca CPU
! Tc d truyn bj han ch v phi chuyn
qua CPU
! khc phuc dng DMA
! Thm m-dun phn cng trn bus "
DMAC (Controller)
! DMAC diu khin trao di d liu gia m-
dun vo-ra vi b nh chnh
NKK-HUST
So d cu trc ca DMAC
B! "#m d$ li%u
Logic "i&u khi'n
Thanh ghi "(a ch)
Thanh ghi d$ li%u
Cc "*+ng d$ li%u
Cc "*+ng "(a ch)
Yu c,u bus
Chuy'n nh*-ng bus
Ng.t
/0c
Ghi
/i&u khi'n "0c
/i&u khi'n ghi
Yu c,u DMA
Ch1p nh2n DMA
NKK-HUST
Cc thnh phn ca DMAC
! Thanh ghi d liu: cha d liu trao di
! Thanh ghi dja chi: cha dja chi ngn
nh d liu
! B dm d liu: cha s t d liu cn
trao di
! Logic diu khin: diu khin hoat dng
ca DMAC
NKK-HUST
Hoat dng DMA
! CPU ni cho DMAC
! Vo hay Ra d liu
! ja chi thit bj vo-ra (cng vo-ra tuong ng)
! ja chi du ca mng nh cha d liu " nap vo
thanh ghi dja chi
! S t d liu cn truyn " nap vo b dm d liu
! CPU lm vic khc
! DMAC diu khin trao di d liu
! Sau khi truyn duoc mt t d liu th:
! ni dung thanh ghi dja chi tng
! ni dung b dm d liu gim
! Khi b dm d liu = 0, DMAC gi tn hiu ngt
CPU d bo kt thc DMA
NKK-HUST
Cc kiu thuc hin DMA
! DMA truyn theo khi (Block-transfer DMA):
DMAC s dung bus d truyn xong c khi
d liu
! DMA ly chu ky (Cycle Stealing DMA): DMAC
cung bc CPU treo tam thi tng chu ky
bus, DMAC chim bus thuc hin truyn mt
t d liu.
! DMA trong sut (Transparent DMA): DMAC
nhn bit nhng chu ky no CPU khng s
dung bus th chim bus d trao di mt t d
liu.
NKK-HUST
Cu hnh DMA (1)
! Mi ln trao di mt d liu, DMAC s dung
bus hai ln
! Gia m-dun vo-ra vi DMAC
! Gia DMAC vi b nh
!"#
! !
!
$%&! %'()*+
,-.
%)/01'
,-.
%)/01'
2+34'( 603
NKK-HUST
Cu hnh DMA (2)
! DMAC diu khin mt hoc vi m-dun vo-ra
! Mi ln trao di mt d liu, DMAC s dung
bus mt ln
! Gia DMAC vi b nh
!"#
! !
!
$%&! %'()*+
,-.
%)/01'
,-.
%)/01'
,-.
%)/01'
$%&!
2+34'( 603
NKK-HUST
Cu hnh DMA (3)
! Bus vo-ra tch ri h tro tt c cc thit bj cho php DMA
! Mi ln trao di mt d liu, DMAC s dung bus mt ln
! Gia DMAC vi b nh
!"#
! !
!
$%&'()
*+,
$'-./%
*+,
$'-./%
*+,
$'-./%
0$1!
2)34%& 6.3
*, 6.3
NKK-HUST
c dim ca DMA
! CPU khng tham gia trong qu trnh
trao di d liu
! DMAC diu khin trao di d liu gia
b nh chnh vi m-dun vo-ra (hon
ton bng phn cng)" tc d nhanh
! Ph hop vi cc yu cu trao di mng
d liu c kch thuc ln
NKK-HUST
4. B x l vo-ra
! Vic diu khin vo-ra duoc thuc hin
bi mt b x l vo-ra chuyn dung
! B x l vo-ra hoat dng theo chuong
trnh ca ring n
! Chuong trnh ca b x l vo-ra c th
nm trong b nh chnh hoc nm
trong mt b nh ring
! Hoat dng theo kin trc da x l
NKK-HUST
8.3. Ni ghp thit bj ngoai vi
1. Cc kiu ni ghp vo-ra
! Ni ghp song song
! Ni ghp ni tip
NKK-HUST
Ni ghp song song
! Truyn nhiu bit song song
! Tc d nhanh
! Cn nhiu dung truyn d liu
M-!un
vo-ra
song
song
!"n
thi"t b#
ngo$i
vi
!"n
bus
h%
th&ng
NKK-HUST
Ni ghp ni tip
! Truyn ln luot tng bit
! Cn c b chuyn di t d liu song song sang
ni tip hoc/v nguoc lai
! Tc d chm hon
! Cn t dung truyn d liu
M-!un
vo-ra
n"i ti#p
!"n
thi"t b#
ngo$i
vi
!"n
bus
h%
th&ng
NKK-HUST
2. Cc cu hnh ni ghp
! im ti dim (Point to Point)
! Thng qua mt cng vo-ra ni ghp vi mt
thit bj ngoai vi
! im ti da dim (Point to Multipoint)
! Thng qua mt cng vo-ra cho php ni
ghp duoc vi nhiu thit bj ngoai vi
! V du:
! USB (Universal Serial Bus): 127 thit bj
! IEEE 1394 (FireWire): 63 thit bj
! Thunderbolt
NKK-HUST
Thunderbolt
7.7 / THE EXTERNAL INTERFACE: THUNDERBOLT AND INFINIBAND 251
THUNDERBOLT PROTOCOL ARCHITECTURE Figure 7.18 illustrates the
Thunderbolt protocol architecture. The cable and connector layer provides
transmission medium access. This layer specifies the physical and electrical
attributes of the connector port.
The Thunderbolt protocol physical layer is responsible for link maintenance
including hot-plug
3
detection and data encoding to provide highly efficient data
transfer. The physical layer has been designed to introduce very minimal overhead
and provides full-duplex 10 Gbps of usable capacity to the upper layers.
The common transport layer is the key to the operation of Thunderbolt and
what makes it attractive as a high-speed peripheral I/O technology. Some of the
features include:
A high-performance, low-power, switching architecture.
A highly efficient, low-overhead packet format with flexible quality of service
(QoS) support that allows multiplexing of bursty PCI Express transactions
Processor
COMPUTER
Platform
controller
hub (PCH)
Thunderbolt
controller
Memory
TC
TC TC
Daisy
chain
Thunderbolt
connector
Thunderbolt
20 Gbps (max)
PCIe x4 DisplayPort
Graphics
Sub-
system
DisplayPort
Figure 7.17 Example Computer Conguration with Thunderbolt
3
The term hot plug is defined as pulling out a component from a system and plugging in a new one while
the main power is still on. It allows an external drive, network adapter, or other peripheral to be plugged
in without having to power down the computer.
NKK-HUST
H%t ch!"ng 8
NKK-HUST
Kin trc my tnh
Ch!"ng 9
CC KI4N TRC SONG SONG
Nguy!n Kim Khnh
NKK-HUST
Ni dung hoc phn
Chuong 6. B x l

NKK-HUST
9.1. Phn loai kin trc my tnh
9.2. H thng da x l b nh dng chung
9.3. H thng da x l b nh phn tn
9.4. GPGPU
Ni dung ca chuong 9
NKK-HUST
9.1. Phn loai kin trc my tnh
Phn loai kin trc my tnh (Michael Flynn -1966)
! SISD - Single Instruction Stream, Single Data Stream
! SIMD - Single Instruction Stream, Multiple Data Stream
! MISD - Multiple Instruction Stream, Single Data Stream
! MIMD - Multiple Instruction Stream, Multiple Data Stream
NKK-HUST
SISD
! CU: Control Unit
! PU: Processing Unit
! MU: Memory Unit
! Mt b x l
! on dng lnh
! D liu duoc luu tr trong mt b nh
! Chnh l Kin trc von Neumann (tun tu)
!" #" $"
%& '&
NKK-HUST
SIMD
!
!
!
#$
%$
&
'(
&
)*
+*
%$
,
'(
,
+*
%$
-
'(
-
+*
NKK-HUST
SIMD (tip)
! on dng lnh diu khin dng thi cc
don vj x l PUs
! Mi phn t x l c mt b nh d liu
ring LM (local memory)
! Mi lnh duoc thuc hin trn mt tp
cc d liu khc nhau
! Cc m hnh SIMD
! Vector Computer
! Array processor
NKK-HUST
MISD
! Mt lung d liu cng duoc truyn dn
mt tp cc b x l
! Mi b x l thuc hin mt dy lnh
khc nhau.
! Chua tn tai my tnh thuc t
! C th c trong tuong lai

NKK-HUST
MIMD
! Tp cc b x l
! Cc b x l dng thi thuc hin cc
dy lnh khc nhau trn cc d liu
khc nhau
! Cc m hnh MIMD
! Multiprocessors (Shared Memory)
! Multicomputers (Distributed Memory)
NKK-HUST
MIMD - Shared Memory
a x l b nh dng chung
(shared memory mutiprocessors)
.
.
.
CU
PU2
IS
DS
PU1
B! nh"
dng
chung
DS
PUn
DS
CU
CU
.
.
.
IS
IS
NKK-HUST
MIMD - Distributed Memory
a x l b nh phn tn
(distributed memory mutiprocessors or
multicomputers)
.
.
.
CU
PU2 LM2
IS
DS
PU1 LM1
DS
PUn LMn
DS
CU
CU
.
.
.
.
.
.
M!ng
lin
k"t
hi#u
n$ng
cao
IS
IS
NKK-HUST
Phn loai cc k thut song song
! Song song mc lnh
! pipeline
! superscalar
! Song song mc d liu
! SIMD
! Song song mc lung
! MIMD
! Song song mc yu cu
! Cloud computing
NKK-HUST
9.2. a x l b nh dng chung
! H thng da x l di xng (SMP-
Symmetric Multiprocessors)
! H thng da x l khng di xng
(NUMA Non-Uniform Memory Access)
! B x l da li (Multicore Processors)
NKK-HUST
SMP hay UMA (Uniform Memory Access)
598 PARALLEL COMPUTER ARCHITECTURES CHAP. 8
Memory consistency is not a done deal. Researchers are still proposing new
models (Naeem et al., 2011, Sorin et al., 2011, and Tu et al., 2010).
8.3.3 UMA Symmetric Multiprocessor Architectures
The simplest multiprocessors are based on a single bus, as illustrated in
Fig. 8-26(a). Two or more CPUs and one or more memory modules all use the
same bus for communication. When a CPU wants to read a memory word, it first
checks to see whether the bus is busy. If the bus is idle, the CPU puts the address
of the word it wants on the bus, asserts a few control signals, and waits until the
memory puts the desired word on the bus.
Shared memory
CPU M
Bus
(a) (b) (c)
Cache
Private memory Shared
memory
CPU CPU M CPU CPU M CPU
Figure 8-26. Three bus-based multiprocessors. (a) Without caching. (b) With
caching. (c) With caching and private memories.
If the bus is busy when a CPU wants to read or write memory, the CPU just
waits until the bus becomes idle. Herein lies the problem with this design. With
two or three CPUs, contention for the bus will be manageable; with 32 or 64 it will
be unbearable. The system will be totally limited by the bandwidth of the bus, and
most of the CPUs will be idle most of the time.
The solution is to add a cache to each CPU, as depicted in Fig. 8-26(b). The
cache can be inside the CPU chip, next to the CPU chip, on the processor board, or
some combination of all three. Since many reads can now be satisfied out of the
local cache, there will be much less bus traffic, and the system can support more
CPUs. Thus caching is a big win here. However, as we shall see in a moment,
keeping the caches consistent with one another is not trivial.
Yet another possibility is the design of Fig. 8-26(c), in which each CPU has not
only a cache but also a local, private memory which it accesses over a dedicated
(private) bus. To use this configuration optimally, the compiler should place all the
program text, strings, constants and other read-only data, stacks, and local vari-
ables in the private memories. The shared memory is then used only for writable
shared variables. In most cases, this careful placement will greatly reduce bus traf-
fic, but it does require active cooperation from the compiler.
NKK-HUST
SMP (tip)
! Mt my tnh c n >= 2 b x l ging nhau
! Cc b x l dng chung b nh v h thng
vo-ra
! Thi gian truy cp b nh l bng nhau vi cc
b x l
! Cc b x l c th thuc hin chc nng ging
nhau
! H thng duoc diu khin bi mt h diu hnh
phn tn
! Hiu nng: Cc cng vic c th thuc hin song
song
! Kh nng chju li
NKK-HUST
NUMA (Non-Uniform Memory Access)
SEC. 8.3 SHARED-MEMORY MULTIPROCESSORS 607
system is called CC-NUMA (at least by the hardware people). The software peo-
ple often call it hardware DSM because it is basically the same as software dis-
tributed shared memory but implemented by the hardware using a small page size.
One of the first NC-NUMA machines (although the name had not yet been
coined) was the Carnegie-Mellon Cm*, illustrated in simplified form in Fig. 8-32
(Swan et al., 1977). It consisted of a collection of LSI-11 CPUs, each with some
memory addressed over a local bus. (The LSI-11 was a single-chip version of the
DEC PDP-11, a minicomputer popular in the 1970s.) In addition, the LSI-11 sys-
tems were connected by a system bus. When a memory request came into the
(specially modified) MMU, a check was made to see if the word needed was in the
local memory. If so, a request was sent over the local bus to get the word. If not,
the request was routed over the system bus to the system containing the word,
which then responded. Of course, the latter took much longer than the former.
While a program could run happily out of remote memory, it took 10 times longer
to execute than the same program running out of local memory.
System bus
CPU
MMU
Memory
Local bus
CPU Memory
Local bus
CPU Memory
Local bus
CPU Memory
Local bus
Figure 8-32. A NUMA machine based on two levels of buses. The Cm* was the
first multiprocessor to use this design.
Memory coherence is guaranteed in an NC-NUMA machine because no cach-
ing is present. Each word of memory lives in exactly one location, so there is no
danger of one copy having stale data: there are no copies. Of course, it now mat-
ters a great deal which page is in which memory because the performance penalty
for being in the wrong place is so high. Consequently, NC-NUMA machines use
elaborate software to move pages around to maximize performance.
Typically, a daemon process called a page scanner runs every few seconds.
Its job is to examine the usage statistics and move pages around in an attempt to
improve performance. If a page appears to be in the wrong place, the page scanner
unmaps it so that the next reference to it will cause a page fault. When the fault
occurs, a decision is made about where to place the page, possibly in a different
memory. To prevent thrashing, usually there is some rule saying that once a page
is placed, it is frozen in place for a time T. Various algorithms have been studied,
but the conclusion is that no one algorithm performs best under all circumstances
(LaRowe and Ellis, 1991). Best performance depends on the application.
! C mt khng gian dja chi chung cho tt c CPU
! Mi CPU c th truy cp t xa sang b nh ca
CPU khc
! Truy nhp b nh t xa chm hon truy nhp b
nh cuc b
NKK-HUST
B x l da li (multicores)
! Thay di ca b x
l:
! Tun tu
! Pipeline
! Siu v hung
! a lung
! a li: nhiu CPU
trn mt chip
666 CHAPTER 18 / MULTICORE COMPUTERS
For each of these innovations, designers have over the years attempted to
increase the performance of the system by adding complexity. In the case of pipelin-
ing, simple three-stage pipelines were replaced by pipelines with five stages, and
then many more stages, with some implementations having over a dozen stages.
There is a practical limit to how far this trend can be taken, because with more
stages, there is the need for more logic, more interconnections, and more control
signals. With superscalar organization, increased performance can be achieved by
increasing the number of parallel pipelines. Again, there are diminishing returns as
the number of pipelines increases. More logic is required to manage hazards and
to stage instruction resources. Eventually, a single thread of execution reaches the
point where hazards and resource dependencies prevent the full use of the multiple
Instruction fetch unit
Issue logic
Program counter
Execution units and queues
L1 instruction cache
L2 cache
(a) Superscalar
L1 data cache
Single-thread register file
Instruction fetch unit
Issue logic
Execution units and queues
L1 instruction cache
L2 cache
(b) Simultaneous multithreading
L1 data cache
P
C
1
P
C
n
R
eg
ister 1
R
eg
isters n
L
1
-I
L
1
-D
L2 cache
P
ro
cesso
r 1
(su
p
ersca
la
r o
r S
M
T
)
(c) Multicore
L
1
-I
L
1
-D
P
ro
cesso
r 2
(su
p
ersca
la
r o
r S
M
T
)
L
1
-I
L
1
-D
P
ro
cesso
r 3
(su
p
ersca
la
r o
r S
M
T
)
L
1
-I
L
1
-D
P
ro
cesso
r n
(su
p
ersca
la
r o
r S
M
T
)
Figure 18.1 Alternative Chip Organizations
NKK-HUST
Cc dang t chc b x l da li
18.3 / MULTICORE ORGANIZATION 675
4. Interprocessor communication is easy to implement, via shared memory locations.
5. The use of a shared L2 cache confines the cache coherency problem to the L1
cache level, which may provide some additional performance advantage.
A potential advantage to having only dedicated L2 caches on the chip is that
each core enjoys more rapid access to its private L2 cache. This is advantageous for
threads that exhibit strong locality.
As both the amount of memory available and the number of cores grow, the
use of a shared L3 cache combined with either a shared L2 cache or dedicated per-
core L2 caches seems likely to provide better performance than simply a massive
shared L2 cache.
Another organizational design decision in a multicore system is whether the
individual cores will be superscalar or will implement simultaneous multithreading
(SMT). For example, the Intel Core Duo uses superscalar cores, whereas the Intel
Core i7 uses SMT cores. SMT has the effect of scaling up the number of hardware-
level threads that the multicore system supports. Thus, a multicore system with four
cores and SMT that supports four simultaneous threads in each core appears the
same to the application level as a multicore system with 16 cores. As software is
developed to more fully exploit parallel resources, an SMT approach appears to be
more attractive than a superscalar approach.
CPU Core 1
L1-D
L2 cache L2 cache
L1-I
CPU Core n
L1-D L1-I
Main memory
(b) Dedicated L2 cache
I/O
CPU Core 1
L1-D
L2 cache
L3 cache
L2 cache
L1-I
CPU Core n
L1-D L1-I
Main memory
(d ) Shared L3 cache
I/O
CPU Core 1
L1-D
L2 cache
L1-I
CPU Core n
L1-D L1-I
Main memory
(c) Shared L2 cache
I/O
CPU Core 1
L1-D L1-I
CPU Core n
L1-D L1-I
L2 cache
Main memory
(a) Dedicated L1 cache
I/O
Figure 18.8 Multicore Organization Alternatives
NKK-HUST
Intel - Core Duo
! 2006
! Two x86 superscalar,
shared L2 cache
! Dedicated L1 cache
per core
! 32KB instruction and
32KB data
! 2MB shared L2 cache
18.4 INTEL x86 MULTICORE ORGANIZATION
Intel has introduced a number of multicore products in recent years. In this section,
we look at two examples: the Intel Core Duo and the Intel Core i7-990X.
Intel Core Duo
The Intel Core Duo, introduced in 2006, implements two x86 superscalar processors
with a shared L2 cache (Figure 18.8c).
The general structure of the Intel Core Duo is shown in Figure 18.9. Let us
consider the key elements starting from the top of the figure. As is common in mul-
ticore systems, each core has its own dedicated L1 cache. In this case, each core has
a 32-kB instruction cache and a 32-kB data cache.
Each core has an independent thermal control unit. With the high transistor
density of todays chips, thermal management is a fundamental capability, espe-
cially for laptop and mobile systems. The Core Duo thermal control unit is designed
to manage chip heat dissipation to maximize processor performance within thermal
constraints. Thermal management also improves ergonomics with a cooler system
and lower fan acoustic noise. In essence, the thermal management unit monitors
digital sensors for high-accuracy die temperature measurements. Each core can
be defined as an independent thermal zone. The maximum temperature for each
Thermal control Thermal control
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Power management logic
2 MB L2 shared cache
Bus interface
Front-side bus
Figure 18.9 Intel Core Duo Block Diagram
NKK-HUST
Intel Core i7-990X
The general structure of the Intel Core i7-990X is shown in Figure 18.10. Each
core has its own dedicated L2 cache and the four cores share a 12-MB L3 cache.
One mechanism Intel uses to make its caches more effective is prefetching, in which
the hardware examines memory access patterns and attempts to fill the caches spec-
ulatively with data thats likely to be requested soon. It is interesting to compare the
performance of this three-level on chip cache organization with a comparable two-
level organization from Intel. Table 18.1 shows the cache access latency, in terms of
clock cycles for two Intel multicore systems running at the same clock frequency.
The Core 2 Quad has a shared L2 cache, similar to the Core Duo. The Core i7
improves on L2 cache performance with the use of the dedicated L2 caches, and
provides a relatively high-speed access to the L3 cache.
The Core i7-990X chip supports two forms of external communications to
other chips. The DDR3 memory controller brings the memory controller for the
DDR main memory
2
onto the chip. The interface supports three channels that
are 8 bytes wide for a total bus width of 192 bits, for an aggregate data rate of
up to 32 GB/s. With the memory controller on the chip, the Front Side Bus is
eliminated.
Core 0
32 kB
L1-I
32 kB
L1-D
32 kB
L1-I
32 kB
L1-D
32 kB
L1-I
32 kB
L1-D
32 kB
L1-I
32 kB
L1-D
32 kB
L1-I
32 kB
L1-D
32 kB
L1-I
32 kB
L1-D
256 kB
L2 Cache
Core 1
256 kB
L2 Cache
Core 2
256 kB
L2 Cache
Core 3
256 kB
L2 Cache
Core 4
256 kB
L2 Cache
Core 5
256 kB
L2 Cache
12 MB
L3 Cache
DDR3 Memory
Controllers
QuickPath
Interconnect
3 8B @ 1.33 GT/s 4 20B @ 6.4 GT/s
Figure 18.10 Intel Core i7-990X Block Diagram
Table 18.1 Cache Latency (in clock cycles)
CPU Clock Frequency L1 Cache L2 Cache L3 Cache
Core 2 Quad 2.66 GHz 3 cycles 15 cycles
Core i7 2.66 GHz 4 cycles 11 cycles 39 cycles
2
The DDR synchronous RAMmemory is discussed in Chapter 5.
NKK-HUST
ARM11 MPCore
Interrupt Handling
The Distributed Interrupt Controller (DIC) collates interrupts from a large number
of sources. It provides
Masking of interrupts
Prioritization of the interrupts
Distribution of the interrupts to the target MP11 CPUs
Tracking the status of interrupts
Generation of interrupts by software
The DIC is a single functional unit that is placed in the system alongside
MP11 CPUs. This enables the number of interrupts supported in the system to
Snoop control unit (SCU)
L1 cache
CPU/VFP
Timer CPU
inter-
face Wdog
L1 cache
CPU/VFP
L1 cache
CPU/VFP
L1 cache
CPU/VFP
Timer CPU
inter-
face Wdog
Timer CPU
inter-
face Wdog
Timer CPU
inter-
face Wdog
Distributed
interrupt
controller
Configurable
number of
hardware
interrupt lines
Instruction
and data
64-bit bus
Coherency
control bits
Instruction
and data
64-bit bus
Read/write
64-bit bus
IRQ IRQ IRQ IRQ
Per CPU private
fast interrupt
(FIQ) lines
Optional 2nd R/W
64-bit bus
Coherency
control bits
Instruction
and data
64-bit bus
Coherency
control bits
Instruction
and data
64-bit bus
Coherency
control bits
Figure 18.11 ARM11 MPCore Processor Block Diagram
NKK-HUST
9.3. a x l b nh phn tn
! My tnh qui m ln (Warehouse Scale Computers
or Massively Parallel Processors MPP)
! My tnh cum (clusters)
SEC. 8.4 MESSAGE-PASSING MULTICOMPUTERS 617
As a consequence of these and other factors, there is a great deal of interest in
building and using parallel computers in which each CPU has its own private mem-
ory, not directly accessible to any other CPU. These are the multicomputers. Pro-
grams on multicomputer CPUs interact using primitives like send and receive to
explicitly pass messages because they cannot get at each others memory with
LOAD and STORE instructions. This difference completely changes the pro-
gramming model.
Each node in a multicomputer consists of one or a few CPUs, some RAM
(conceivably shared among the CPUs at that node only), a disk and/or other I/O de-
vices, and a communication processor. The communication processors are con-
nected by a high-speed interconnection network of the types we discussed in Sec.
8.3.3. Many different topologies, switching schemes, and routing algorithms are
used. What all multicomputers have in common is that when an application pro-
gram executes the send primitive, the communication processor is notified and
transmits a block of user data to the destination machine (possibly after first asking
for and getting permission). A generic multicomputer is shown in Fig. 8-36.
CPU Memory
Node
Communication
processor
Local interconnect
Disk
and
I/O
Local interconnect
Disk
and
I/O
High-performance interconnection network
Figure 8-36. A generic multicomputer.
8.4.1 Interconnection Networks
In Fig. 8-36 we see that multicomputers are held together by interconnection
networks. Now it is time to look more closely at these interconnection networks.
Interestingly enough, multiprocessors and multicomputers are surprisingly similar
in this respect because multiprocessors often have multiple memory modules that
must also be interconnected with one another and with the CPUs. Thus the mater-
ial in this section frequently applies to both kinds of systems.
The fundamental reason why multiprocessor and multicomputer intercon-
nection networks are similar is that at the very bottom both of them use message
NKK-HUST
Mang lin kt
(a)
(c)
(e)
(g)
(b)
(d)
(f)
(h)
Figure 8-37. Various topologies. The heavy dots represent switches. The CPUs
and memories are not shown. (a) A star. (b) A complete interconnect. (c) A tree.
(d) A ring. (e) A grid. (f) A double torus. (g) A cube. (h) A 4D hypercube.
Interconnection networks can be characterized by their dimensionality. For
our purposes, the dimensionality is determined by the number of choices there are
to get from the source to the destination. If there is never any choice (i.e., there is
only one path from each source to each destination), the network is zero dimen-
sional. If there is one dimension in which a choice can be made, for example, go
NKK-HUST
Massively Parallel Processors
! H thng qui m ln
! t tin: nhiu triu USD
! Dng cho tnh ton khoa hoc v cc bi
ton c s php ton v d liu rt ln
! Siu my tnh

NKK-HUST
IBM Blue Gene/P
624 PARALLEL COMPUTER ARCHITECTURES CHAP. 8
coherency between the L1 caches on the four CPUs. Thus when a shared piece of
memory resides in more than one cache, accesses to that storage by one processor
will be immediately visible to the other three processors. A memory reference that
misses on the L1 cache but hits on the L2 cache takes about 11 clock cycles. A
miss on L2 that hits on L3 takes about 28 cycles. Finally, a miss on L3 that has to
go to the main DRAM takes about 75 cycles.
The four CPUs are connected via a high-bandwidth bus to a 3D torus network,
which requires six connections: up, down, north, south, east, and west. In addition,
each processor has a port to the collective network, used for broadcasting data to
all processors. The barrier port is used to speed up synchronization operations, giv-
ing each processor fast access to a specialized synchronization network.
At the next level up, IBM designed a custom card that holds one of the chips
shown in Fig. 8-38 along with 2 GB of DDR2 DRAM. The chip and the card are
shown in Fig. 8-39(a)(b) respectively.
1 Chip
4 CPUs
2 GB
4 processors
8-MB L3 cache
2-GB
DDR2
DRAM
32 Cards
32 Chips
128 CPUs
64 GB
32 Boards
1024 Cards
1024 Chips
4096 CPUs
2 TB
72 Cabinets
73728 Cards
73728 Chips
294912 CPUs
144 TB
System Cabinet Board Card Chip:
(b) (c) (d) (e) (a)
Figure 8-39. The BlueGene/P: (a) chip. (b) card. (c) board. (d) cabinet.
(e) system.
The cards are mounted on plug-in boards, with 32 cards per board for a total of
32 chips (and thus 128 CPUs) per board. Since each card contains 2 GB of
DRAM, the boards contain 64 GB apiece. One board is illustrated in Fig. 8-39(c).
At the next level, 32 of these boards are plugged into a cabinet, packing 4096
CPUs into a single cabinet. A cabinet is illustrated in Fig. 8-39(d).
Finally, a full system, consisting of up to 72 cabinets with 294,912 CPUs, is
depicted in Fig. 8-39(e). A PowerPC 450 can issue up to 6 instructions/cycle, thus
NKK-HUST
Cluster
! Nhiu my tnh duoc kt ni vi nhau bng
mang lin kt tc d cao (~ Gbps)
! Mi my tnh c th lm vic dc lp (PC
hoc SMP)
! Mi my tnh duoc goi l mt node
! Cc my tnh c th duoc qun l lm vic
song song theo nhm (cluster)
! Ton b h thng c th coi nhu l mt my
tnh song song
! Tnh sn sng cao
! Kh nng chju li ln
NKK-HUST
PC Cluster ca Google
hold exactly 80 PCs and switches can be larger or smaller than 128 ports; these are
just typical values for a Google cluster.
128-port Gigabit
Ethernet switch
128-port Gigabit
Ethernet switch
Two gigabit
Ethernet links
80-PC rack
OC-48 Fiber OC-12 Fiber
Figure 8-44. A typical Google cluster.
Power density is also a key issue. A typical PC burns about 120 watts or about
10 kW per rack. A rack needs about 3 m
2
so that maintenance personnel can in-
stall and remove PCs and for the air conditioning to function. These parameters
give a power density of over 3000 watts/m
2
. Most data centers are designed for
6001200 watts/m
2
, so special measures are required to cool the racks.
Google has learned three key things about running massive Web servers that
bear repeating.
1. Components will fail so plan for it.
2. Replicate everything for throughput and availability.
3. Optimize price/performance.
NKK-HUST
9.4. B x l d hoa tnh ton da nng
! Kin trc SIMD
! Xut pht t b x l d hoa GPU (Graphic
Processing Unit) h tro x l d hoa 2D v
3D: x l d liu song song
! GPGPU General purpose Graphic
Processing Unit
! H thng lai CPU/GPGPU
! CPU l host: thuc hin theo tun tu
! GPGPU: tnh ton song song
NKK-HUST
B x l d hoa trong my tnh
NKK-HUST
GPGPU: NVIDIA Tesla
!Streaming
multiprocessor
!8 Streaming
processors
NKK-HUST
GPGPU: NVIDIA Fermi
7

Hardware Execution
CUDAs hierarchy of threads maps to a hierarchy of processors on the GPU; a GPU executes
one or more kernel grids; a streaming multiprocessor (SM) executes one or more thread blocks;
and CUDA cores and other execution units in the SM execute threads. The SM executes
threads in groups of 32 threads called a warp. While programmers can generally ignore warp
execution for functional correctness and think of programming one thread, they can greatly
improve performance by having threads in a warp execute the same code path and access
memory in nearby addresses.

An Overview of An Overview of An Overview of An Overview of the Fermi Architecture the Fermi Architecture the Fermi Architecture the Fermi Architecture
The first Fermi based GPU, implemented with 3.0 billion transistors, features up to 512 CUDA
cores. A CUDA core executes a floating point or integer instruction per clock for a thread. The
512 CUDA cores are organized in 16 SMs of 32 cores each. The GPU has six 64-bit memory
partitions, for a 384-bit memory interface, supporting up to a total of 6 GB of GDDR5 DRAM
memory. A host interface connects the GPU to the CPU via PCI-Express. The GigaThread
global scheduler distributes thread blocks to SM thread schedulers.

Fermis 16 SMare positioned around a common L2 cache. Each SMis a vertical
rectangular strip that contain an orange portion (scheduler and dispatch), a green portion
(execution units), and light blue portions (register file and L1 cache). Jan2014 Computer Architecture 538
NKK-HUST
NVIDIA Fermi
8

Third Generation Streaming
Multiprocessor
The third generation SM introduces several
architectural innovations that make it not only the
most powerful SM yet built, but also the most
programmable and efficient.
512 High Performance CUDA cores
Each SMfeatures 32 CUDA
processorsa fourfold
increase over prior SM
designs. Each CUDA
processor has a fully
pipelined integer arithmetic
logic unit (ALU) and floating
point unit (FPU). Prior GPUs used IEEE 754-1985
floating point arithmetic. The Fermi architecture
implements the new IEEE 754-2008 floating-point
standard, providing the fused multiply-add (FMA)
instruction for both single and double precision
arithmetic. FMA improves over a multiply-add
(MAD) instruction by doing the multiplication and
addition with a single final rounding step, with no
loss of precision in the addition. FMA is more
accurate than performing the operations
separately. GT200 implemented double precision FMA.
In GT200, the integer ALU was limited to 24-bit precision for multiply operations; as a result,
multi-instruction emulation sequences were required for integer arithmetic. In Fermi, the newly
designed integer ALU supports full 32-bit precision for all instructions, consistent with standard
programming language requirements. The integer ALU is also optimized to efficiently support
64-bit and extended precision operations. Various instructions are supported, including
Boolean, shift, move, compare, convert, bit-field extract, bit-reverse insert, and population
count.
16 Load/Store Units
Each SMhas 16 load/store units, allowing source and destination addresses to be calculated
for sixteen threads per clock. Supporting units load and store the data at each address to
cache or DRAM.

Dispatch Unit
Warp ScheduIer
Instruction Cache
Dispatch Unit
Warp ScheduIer
Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
SFU
SFU
SFU
SFU
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
Interconnect Network
64 KB Shared Memory / L1 Cache
UniformCache
Core
Register FiIe (32,768 x 32-bit)
CUDA Core
Operand Collector
Dispatch Port
Result Queue
FP Unit INT Unit
Fermi Streaming Multiprocessor (SM)
8

Third Generation Streaming
Multiprocessor
The third generation SM introduces several
architectural innovations that make it not only the
most powerful SM yet built, but also the most
programmable and efficient.
512 High Performance CUDA cores
Each SMfeatures 32 CUDA
processorsa fourfold
increase over prior SM
designs. Each CUDA
processor has a fully
pipelined integer arithmetic
logic unit (ALU) and floating
point unit (FPU). Prior GPUs used IEEE 754-1985
floating point arithmetic. The Fermi architecture
implements the new IEEE 754-2008 floating-point
standard, providing the fused multiply-add (FMA)
instruction for both single and double precision
arithmetic. FMA improves over a multiply-add
(MAD) instruction by doing the multiplication and
addition with a single final rounding step, with no
loss of precision in the addition. FMA is more
accurate than performing the operations
separately. GT200 implemented double precision FMA.
In GT200, the integer ALU was limited to 24-bit precision for multiply operations; as a result,
multi-instruction emulation sequences were required for integer arithmetic. In Fermi, the newly
designed integer ALU supports full 32-bit precision for all instructions, consistent with standard
programming language requirements. The integer ALU is also optimized to efficiently support
64-bit and extended precision operations. Various instructions are supported, including
Boolean, shift, move, compare, convert, bit-field extract, bit-reverse insert, and population
count.
16 Load/Store Units
Each SMhas 16 load/store units, allowing source and destination addresses to be calculated
for sixteen threads per clock. Supporting units load and store the data at each address to
cache or DRAM.

Dispatch Unit
Warp ScheduIer
Instruction Cache
Dispatch Unit
Warp ScheduIer
Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
Core Core
SFU
SFU
SFU
SFU
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
LD/ST
Interconnect Network
64 KB Shared Memory / L1 Cache
UniformCache
Core
Register FiIe (32,768 x 32-bit)
CUDA Core
Operand Collector
Dispatch Port
Result Queue
FP Unit INT Unit
Fermi Streaming Multiprocessor (SM)
! C 16 Streaming
Multiprocessors (SM)
! Mi SM c 32 CUDA
cores.
! Mi CUDA core
(Cumpute Unified
Device Architecture) c
01 FPU v 01 IU
NKK-HUST
GPGPU: NVIDIA Kepler

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An Overview of the GK110 Kepler Architecture
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NKK-HUST
H%t

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