Reg. No.

:
Question
Paper Code :
Time : Three hours
esti$atotsr.'". ,,
Larggimprovements in power dissipation are possible only at higher levels
ofd""inf straction. Why?
-Whatt'r61't
the objectives of power minimization techniques related. to
rneg.rory that can be achieved using software?
'=e.,
#
(Regulation 2009)
"1r
",r,,t:4.-
Maximum : 1oo marks
jr
'*+.**
An swer Al,ft'.luestfri4q,
' tt
*"
tr
..
PART A -
$0,a<,4
; 2O'lnart<qj'
. . ; "
i ", . . i ; '
l. What are the sources of po*"*
"o$Sirngti.ht
in VLSI circuits?
i
to..,,r,o' '
;
2. List any four basic princjples o'fr{prw pcirver;fit St design.
". i u'
i
o, - ^-
t r
i
*", *: f '
3. state the effect of charirrel
lpttgffi dhyporver dissipation in VLSI circuits.
'.
t#
-
jivl
4. what are the techniqueg #itu**e%r reducing power consumption in
multipliers?
"'
.,.,
:,
5. How does the design of supply clock influence power dissipation?
,'i'tau,
6. Define sigiial Ae{i,yity with respect to a circuit node.
7. What are- flre'dr.awbacks of zero-delay mod.el used for determination of
: . : {,
: , , 11i , .
averggd p'ower in
I/LSI
circuits?
. : '
8. DiStingBishtet$l,een power estimation at circuit level and high level power
9':/
10.
(b) (il
PARf B - (5
"
16
='80
marks)
Or
Discuss the dynamic logic and static
respect to power
dissipation.
k#-"its with
(6)
13.
(ir) Explain h a94t about operation reduction and operation
substitution with examples.u*"
(E +
S)
il
*"""u'
(a) Explain any two techniquesfrviB,
"trtq"-pre
for reducing power
consumption in memories.
'$# "t.
o
-ot, '
S*tf*"u''.
"%*f
(b) Draw the resonant ari$er
ffiq
ifu g"r"r.ting
supply crock and
compare it with other nqetHo$;*[ls$
sive
the imporLnce of clock
generation with reSppt topowei disfpation
f l '
"t ' ", -
' t ' ' t -
o"
(a) (il Draw tfie fl"F"t
q[]!:f
MEhte-Carto
based estimation of glitching
power for secigent$
"it"F
and expLain.
S
,"i (8)
(ir) write a note d'iqpow-g;fbsumation
based. o"i"iilror*"tion theory
appr oach.
\ *^
. , , , , '
l At
t
UL-*-
Or
L4.
15.
(b) Explairr'..lhe method of estirnating average power in combinational
an$se3rr"Cn#at circuits using sta.tistical techniques.,
.S
",
.
"
"l :,Efl l r"' '
i .... pe.":
(a)
.D,iseuqp-
iifaetairi trre. various revels of abstraction at which power
.i
tt":'Fte-*ot"*"" estimated bJ software'
*", "
(b)
',Larsif
r*p.1o1r"*.rrts in power dissipation are possibre at higher levels
",
on'{gqign"'abstraction.
JustiS the above statement and discuss the
".
o-t'dgqlgn"'bbstraction.
JustiS the-above statlment and discuss the
,
''
teoftniques used.
\
I r.^
'lii,li
"::1 i. L
lt
i."111
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77907
Reg. No. :
Questi on
Paper Code : 98081
M.E. DEGREE EXAMINATION, NOVEMBERID
Electiue
VLSI Design
YL9252 - LOW POWER VLSI DESIGN
(Common to M.E. Applied Electronics)
(Regulation
Time : Three hours 100 Marks
Answer ALL
PART A
Define subthreshold swing.
2. What is body effect?
3.
4.
o.
What is meant by tra
Draw a 6 transistor SRAM ceIL
Define intrinsic delav.
6. Com R type row decoder and NAND type row decoder in memories.
computing?
nction A* + BX + C using two multipliers and two ad.ders.
1.
7.
9.
Imn"lemeni
ttu.
De
'-'
.,,
"-%,"
*rffl
iO***Wdffi?f*o an algorithm to compute signal probabilities.
"w
_%,u
%%,
'r
e"**fl
PARTB- ( 5x
16=80Mar ks)
11. (a) ( t - '
Derive an expression
for short circuit power
dissipation
inverter.
ffi
(ii)
write a short note on drain induced
barrier roweri
Or
(i)
"'rFxplain
basic principles
of low power
design.
(iip
Discuss the various sources
of power
d
devices.
(8)
(8)
12. (a) (,
Discuss
the various features
of technology
J
power
(8)
Or
(b) (il
Explain
the concept
of state assignment
for finite state machine to
reduce power
dissipation
wi
5ample. (10)
(ii)
Factoring
out a common
n can achieve power
saving.
Justi$r.
(6)
circuits
and sense
(10)
(6)
13. (a) (t
How can power
be red
amplifier
circuits?
rchniques
fo, J
dissipation.
(b)
(ii)
(b) (il
(ii)
14. (a) (t
,.
".f
l.*
L"l f,
;'o '
(ii)
0 t l
\ _, , ,
Differentiate
MT
Explain
the
Design
a
How do
diagrams?
Discuss
m
circuits.
the- principle
of pre-computation
logic for reducing power
dtable example.
/o\
ff
levet converter. i.t'ttt.: (10)
l ogi c.
*- *.
j Tu' *i
*:
( 6)
probability
using binary decision
(s)
average power
in combinational
(8)
(8)
??*er
15. (a)
ting
Or
Explain in detail about Monte carlo method
for estimating glitch power.
l 1..*
t l
Or
the
b-
i&
,w
s"
st t*
t}':
i,+
@mpu
W*-
,aw
ds 5f
(b)
E*fr
tion.
98081
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:;;:,::..:::
l
are? Expiain.
costs
33
Reg.
No.:
Q
0205
D.A{.Tech. DEGRES SXAh{INATION,
TNtryJULY 2009
THIRD
SEMESTFR
VLSI DESIGN
VL5OO2 LOW POWER W.,SI DESIGN
(Common
to Applied Siectronics)
Tlrroe hor:re
(REGUI"ATION
2007)
Answer ALL questions:
PART A -..,-
(10 x 2
=
h}marks)
Frequency influencps tbe Power
Maximum : 100 narks
Dissipation ow the
$witching
in a logic
What are tbg sources of Fower Dissipation"?
lltirat is a G.ate Dela;'
podel.?
Whqt is
Bus lnvert Encoding?
What is
O-MOS Floating Node?
i
I)raw the Adiabatic logic Inverter for for:r phase operation.
.
What is Glitching Power?
Write the eguation for Capacitive Power Dissipation of a bircuit.
f , .
:
PART ts
-
(E
x
tr6
=
g0
marks)
l1'
.
(a)
State aud explain the basic principles
and figure-of-merits
oj'Low
Design.
'(b)
I)erive an expression for the dyeanric
Power Dissipatinn
in a
Inverter.
--F
,Ot
72.
'Discuss
in detail various limits of l-,ow
power
Design.
. i
13. ' Explsin i.r:. detail about
p^.ecornpuLation
logr. optimization:
Cr
!t1,,'Explain
the variou.e
circrujt" tecl.rnl
,iies- for reclucing
p^orv*r
Consumption
il
Mui ti pl i ers.
A* r
IPL,
DpL
r
DevJ(,
SDJr-r
gRDl -r"edpu
-:rv
t
Ilorve
(t
CMCI
i c
Wwer
in V/riter Driver
circuits and Sense
I i l ,
l o.
t T.
Explain tbe methods of reduci.g
Amplifier eircuits"
1*)
RfP
how a Sigual lhohsbility
ie calculated
using Bio"ry Decision
Diagram.
(b)
Exptain
in dei;ul how l:lr',
:o$
#;ri
T:i)
ver Estimatio:
lffi
.qY.*"r*.$":s
H"s$35
(8)
(8)
Bo-slt
L8.
1rr.
Pt
ga,ttr
[*lffi***"W*r?$/
\E-TIEA
Gu*t u.,r"t ros
oo
o*.":$*;;':5
Iogc Simrrlation
anM.iftr d)f,rchitldture
L,evel' Analysie.
Or
Software l)enign
Cptimization
methods.
. I
fo0**"'o
Y
(a)
Discuss
in detail the Power
optinization
using operation
Reduction
and
'oprrn.til::
.!ubgti.tu.;:.i.,)::;.
i1*;
(b)
.
what is meant
by Technorory
Mapping?
Exprain
with an exampre. (4)
s{
t?->
t t .
20. Iixllain
in detgil
9$thn*lion
a
gJ, wd,
wc)
* Atchr:fadh^'tal
;;;
i*i*t"-ry
A cD'uiui
+'l,.l&n
^chtuta'!
t't'"t
t
' !
..
."' ,,
/
our.xo.,'
N
0036
M' E'&r'
Tech'
I)l:"
G REII
EXAMINATI'N
N''TEMBER,,E'EMBER
2008.
THIRD
SEME:STER
APPI,IED
ELECTRONICS
]./I,'OA}I,OW
POWER
WSI
DESIGN
(Common
to VLSI
cl.esign,l
(REGUI,ATION
2OO7)
15me
: Three
hours
Maximum
: 100
noarks
Answer
ALL questions.
'
I'}ART
A
-
(10
.{
!
=. e.{'t
nrarks)
tru,,J**'nho\
..ai
od*,
1.'
List
the
five
levers"of
Higlarchv
of
fjpit,
g-lqrpDissipation.,^
t#;
s:lij*:
*
qtou'srds o)
.o'-sl/t<rr'9,
r"tr*tliJ#;:
-.,
i$r
r.regs'p'E
*
"H::
&"
-
what
is
rhe
nu'iJprin.ipr.(oir,o*
po*r,
il.is.,rs
[*[
T] :sJ,*;"ff-\
. ro*or*
*"r*rrr;ilrr*-
4'
List
few
circuid
hchniques
for reducrng power
consurnption.
5.
I)ra;v
i;he
6T SiiAIvI
ceil.
6"
\!hat
is Low
S*ing
Bus
System?
7
",il"';Tq:'
:i'oglf**
yg",1l*.'::t',1
.5
rlo o.va no o\
r*.iir,"o"
;;TiT:;",{,*9.
8'
Define
Sample
Oorrelation.
at o d1*;i+r"
d
9'
ffIj,Jehavioral
Level
can produ.ui
* large
improvement
in
power
lnb+l;L;l\
of tlr.L
P*do- .S+pht
\
r ' t ' r
d:
11*,'."'Explain irr detail the Physics of Power Dissipation in Submicron MOSfnf.
tt\
Or
L2.
[a]'
Derive an expression for the short circuit power dissipation in a CMCS
Inverter.
(S)
G) Derive the expression for power dissipated in a \ILSI circuit d-ue
to
:
parasitic capacitor.
WSt
fil
.i 13.
,.Explain in detail the Circuit Level Low
pow -"6'
-l zi
r;;::;;:ff
(b)
iixplain
'ihe
Deiay Balance,j-.l'{ultiplier
Oell and its impact on the pgwqr.
consumption of a parallel srray multiplier
fdi
Explain the techniques
of reducing
power
consumption i
. Or
\
Discuss in detail the sources of software
power
Dissipatioo.[ss.A
)
(6)
Explain in detail Cod+sign for Low
power.
(10)
, , }
,k
tr,.
\
.
1K
n Mernories.
t)
16'9
(a)
V/hat is Adiabatic lcgtc lnverter? Draw and explain its operation.
(b).
How rloes the Cor.nplernenfary
Acliahstie Con:,putaticn Cif,br frr--:n
static cMos Gate irr
power
Dissipation?
Explain in detail.
,n.
^
Explain in detail.the Logic
power
EBtimation Technioues.
r
Soqrcg uf
;n*u?
dlsxtption, prob"trrn S'lnk-rng,t
,d.nqru,r-nd,
.!tgu\ Csrtcthhl
4zm?ottl t"twtah'rl,
Spa*rOtc.*91-$F0h,
gpd#io
"lo*pr"",f
CsryroJtirn;"*UU,i$t
tgl
bi
Tith
the flowchart explain i;he Monte Carlo based tecLirique to estimate
\"/'
the average power. in sequeutial
circuits
(g)
J)
Explain in detail about the
power
Estimatior.r using Entropy. (B)
19 Frplain in^ dct'ail' tlic i.cila','icr.=.i
Level Traiisfcuns
fo. irnpr',rvirrg Fower
'
Dissipation.
l,H\ ) fb"a"
&fteyar.n, lnd
onden olt(a,a*
j
#roiar, actu^
-
t
/
nnga.l+wdtfv\-wa.e , Sor,&"1 r.cerr>siu!^ d,t
ff{"au
Or
(8)
t - L-
r,ii.tr
(s)
20.
(a)
'
(b)
I N0036 |
l ;
2
Reg. No. :
fime: Three hours
AnswerALL
PART A
2.
3.
1.
4.
D.
What is punch through?
What is meant by Reve
What is multilevel
What are the
algorithm?
How is
marks)
nnel effect?
of performance driven circuit optimization
reduced by using clock gating?
t'"
/*i I
6. What are"ttib sHlidnt features of adiabatic logic circuit?
-\***ts'
7.
M.E./lVLTech. DEGREE EXAMINATION, JlJfiffi\e"fu1
i t *F 1
Common to M.E. Applied Electronics / M.E. fhsl #.d"
"'"..^*./
Electiue
11. (a) (r)
PARTB- ( bx16=80mar ks)
Derive the expression for subthreshold
current
MOSFET.
Explain the MIS structure and derive the
of depletion region.
for
(ii)
#--h"
or
f #
- . 1
\
i"Jl
( b) . ' ( 0
Deduce the expression for short circuit noi
unloaded inverter.
(ii)
Explain the circuit limits
of low
12. (a)
Explain the power
dissipation
algorithm. Apply the same
following function F
=
{fr, fr}
f i =ad+bcd
and
f z=a+bc+
(i)"-"'"Explain
circuit
example.
(ii)'-
Write short
13. (a) (t
Explain
gn.
(b)
logic optimization
the power
for the
for CMOS gate
with an
(10)
(6)
method in sense amplifier circuits of
organization of SRAM.
Or
(10)
(6)
reduced swing clock technique for power
reduction in
(8)
SRAM.
(ii)
D
(b) (')
(ii)
the power reduction effrciency of Adiabatic logic. (8)
L4. (?
_
A)"*"ryphin the transition Density signal model and propagation
of
t-'"
""a
jfiansition density.
-
(f
0)
d--"=J-/
calculate the transition density and static probability
of y =
ab + c
,
\ "- i
j
i f P( o) =o. 2, P( b) =0. 3, P( c) = 0. a, D( a) =r , D( b) =2 and D( ") =3.
(6)
{'o*hu"*'r
iT
"*l
,#"Y
\ =
#J
''"--*-"
I
"\"4
f
\ c/
\ U
nel
(8)
depth
(8)
of an
(8)
(8)
r
dhiltkl.
\
lY ,t'"1
Or
31143
lSr
(b) (il Explain Monte Carlo power simulation.
(ii) Write short notes on Gate-level power analysis.
(8)
15. (a) Write short notes on:
(1) Power optimization using operation reductj{\*\o/
(8)
(ii)
Architecture driven voltage scaling.
\
#l
(8)
w
or
/\ th,
(b) (r) Explain the first-order differedps--."ptff#h- for low power
\ f
dissipation.
l**-\- {f
(8)
orssrpaf,ron
d*\
{"f
(n,
f f l \ \
(ii) Write short notes on conskahed} l$ast square technique for
nonadaptive frlters.
f"*t3'*/
(8)
' j
i
''
{*o..
1*
t
! t."".
i
i.,/
..'''"L....:\-
/>
=;
f \ / i
". l*l i
aq"i
i*,.
I
! . r '
d' \
ui
=-*./*}
L-ot,\
,,
t "
' " Lr
f l ' \ -, \
*o"-
t i
i
'
".,"\""n !
'-b-*t'""
t
31148
Reg. No. :
u 0046
M. E ;/M.Tech:
DEGREE
EXAMINATION,
NOVEMBER/DE
OEMBER
z0 1 0
.
THIRD SEMESTER
APPLIED ELECTRONICS
VL5OO2
LOW POWER VLSI DESIGN
(REGULATION
2007)
fime : Three hours
Maximum
: 100 marks
Answer ALL questions.
. a
1.' What is short channel effeet?
2' Give the expression for the energy transferred
out of the power-supply
during
a low-to-high
transition,
at the gate
output.
3' What are the four componentg
of performance
driven circuit optimization
algorithms?
4. What is transistor reordering?
5. What is clock gating?
"
6. Draw the Boolgan decision diagram for the logic expression
y
=ffi.
:
7. List the three steps invorved in Monte carro
power
simulation.
8. Defi.ne Ttansition
Density.
9. what is the use of DCM technique in the realization
of FIR frrters?
10. List the four practices
that minimize
^"*o"y
bandwidth
reguirements.
g
D
& o
t
5
7 t o t ,q
Or
L2. (a) Derive an expression for the power dissipation due to the charging and
-t' o'
11.
,"5tplain
the physics of power fieeipation in
(a)
Iong channel MOSFET.
(b)
Submicron MOSFET.
discharging of a capacitance in a CMOS Inverter.
(b},t"'Di""use
the basic principles of Inw Power d,esign.
(8)
(8)
(8)
(8)
techniques for , reducing power
13. (a)
,
What is Factoring? What is its effect in powersaving?
Explain. (10)
(b)
Write a note onTechnologyMapping. (g)
Or
l
14;"'e"l)i"" ss in
'detail'
about the
rcircuit
level
circuits
(8)
(8)
#
.
eonsumption.
15.)(a) Explain the concept of red.ucing
employed for SRAM circuits.
Or
power
in sense amplifi.er
(b)
How low core voltiges are achibved from a single supply?
16. Explain in d.etail about
:,
(a)
Low SwingBus.
O)
Charge Recycling Bus.
17. (a)
Defrne etatic probability. Brplain the propagationrof
static probability in
logic'circuits. (8)
(b)
Compute the transition density and static probability of y =
ab + c given
P(o)
=
o.z, P(b)
=
0.3
,
P(c)
=
s.4
,
D( a) =l , D( b) = 2, D( e) =s
'
'
:
ff'here
P(a) P(b) PG) are the inpur sraric
rprobabitities
and
O(") A(a) A(c) are the transition density of the inputs). (g)
one additional degree of freedom
itul
-
t
"m*J
,
(8)
Or
18. Prove that Lag-one signal Model provides
over the memoryless'signal model.
19. Explain the first.order differenceg algorithm and second-order
.differences
algorithm for improvement in power dissipation targeted for digital filters. (1.6)
20. Explain in detail about
,(a)
Software Power Estimation.
,(b) ,Software
Power Optimization.
. : ,
3
Reg. No. :
Questi on
Paper Code : 9L852
M.E. DEGREE EXAMINATION, JANUARY 2012,
Elective
\T,SI Design
YL 9252 - LOW POWER VLSI DESIGN
(Regulation 2009)
Time : Three hours Maximum : 100 marks
Answer ALL questions.
PARTA- ( 10 x2=20 mar ks)
1. Why is power dissipation considered as the most critical factor in development
of microelectronics technology?
2. What is DIBL?
3. Minimum area is not always associated with minimum power dissipation for
CMOS circuits. Justifv this statement.
4. Name two techniques for reduction of power in multipliers.
5. Define Gate reorsanization.
6. What is clock gating?
7 . List the steps involved to estimate maximum and minimum average power of i
circuit.
8. What are glitches? How does it affect power requirement?
9. Name the various levels of design abstraction where power dissipation can be
reduced.
10. Compare gate level and architecture level power estimation.
PARTB- ( 5x16=80mar ks)
11. (a) Elaborate on the various factors that contribute to power dissipation in
CMOS circuits.
Or
(b) Discuss the different limits that are to be applied at various levels for
design of low power VLSI circuits.
L2. (a) Explain the optimization techniques for reduced power consumption in
muitiplier circuits.
Or
(b) Explain the muitilevel, logic optimization procedure for low power.
13. (a) Describe in detail the various techniques used for reducing power
consumption in memories.
Or
(b)
With circuit schematic compare the circuit performance and power
dissipation of ratioed logic, DCVS logic, pass transistor logic, Domino
logic and DCSL logic.
14.
(a) Discuss the Monte Carlo based method for power estimation of
combinational and sequential logic circuits.
Or
(b) Explain the simuiation based approach for determining maximum
dynamic power in static CMOS.
15.
(a) With an example, enumerate
power optimization using operation
reduction, operation substitution and precomputation.
Or
(b) (i) What are the various sources of power dissipation in a CPU that
can be influenced by sofbware? Explain.
(8)
(ii) Discuss how the memory access costs can be minimized using
software techniques with example.
(8)
R---
91852