DOC112: Computer Hardware Lecture 08

Slide 1
Lecture 8:
Sequential Digital Systems and Synchronous
Counters
DOC112: Computer Hardware Lecture 08
Slide 2
In this lecture we will:
Introduce the main ideas of a Synchronous
Digital System (SDS).
Eamine how sim!le fli!"flo!s may #e used to
define a generic and com!letely general SDS.
Eamine #inary counters in detail and how to
design them.
Show how to design a controlled counter which
includes $don%t care$ states.
DOC112: Computer Hardware Lecture 08
Slide 3
&he D ty!e 'li!"'lo!
Last lecture we saw that a fli! flo! is a one"#it memory
It can #e $read$ at any time
It is $written$ when the cloc( in!ut changes )alue
&he edge may #e either rising or falling
DOC112: Computer Hardware Lecture 08
Slide 4
&he D"* fli! flo!
&he D"* fli! flo! is a ()ery) sim!le eam!le of a
synchronous digital system.
It can #e in one of two !ossi#le states+ and its
change of state is controlled #y a single cloc(
signal.
It can #e re!resented #y a finite state machine
diagram.
D
Q
C
0 1
1
0
0
1
DOC112: Computer Hardware Lecture 08
Slide 5
&he ,"- fli!"flo!
Digital designers also use the so called ,"- fli!"
flo! which has two data in!uts (and of course+
a cloc( in!ut)
This trasitio ta!le de"ies the operatio o" the "lip#"lop$
J K Function Next Q
0 0
0 1
1 0
1 1
Unchanged Q
Reset Zero
Set One
Toggle Q
DOC112: Computer Hardware Lecture 08
Slide %
&he &ransition Diagram of the ,"-
'li! 'lo!
E)en though the fli!"flo! has two in!uts+ it has
only two states (not four).
It has two in!uts and four !ossi#le transitions
J K Function Next Q
0 0
0 1
1 0
1 1
Unchanged Q!no"#
Reset Zero
Set One
Toggle Q!no"#
DOC112: Computer Hardware Lecture 08
Slide &
Sequential Digital Circuits
. fli!"flo! is an eam!le of a sequential circuit. It
goes through a sequence of states controlled #y
its in!uts.
.nother eam!le is the counter in a digital watch.
It will go through a sequence of states: dis!lay/
"0 dis!lay1 "0 dis!lay2 etc. States will change
at eactly 1 second inter)als
DOC112: Computer Hardware Lecture 08
Slide 8
Synchronous Circuits
Synchronous circuits are those where state
changes occur at eact times controlled #y a
cloc(.
Synchronous circuits are #y definition
sequential. 3ot all sequential circuits are
synchronous.
4ith the sim!le D ty!e fli!"flo! and our
(nowledge of com#inational digital circuits+
we can construct a general model with which
any synchronous circuit can #e im!lemented5
DOC112: Computer Hardware Lecture 08
Slide '
(oth the state se)ueci* +iput, ad output cotrol
lo*ic are com!iatioal circuits$
Synchronous Digital Circuits
DOC112: Computer Hardware Lecture 08
Slide 10
Synchronous Digital Circuits
&he num#er of out!uts of the circuit de!ends on
the !ro#lem.
&he out!uts de!end only on the State #its *i.
*6(7(t81) 9 D6(7(t) D"ty!e 'li!"'lo! law
D6(7 9 '( I617+ I627+ ..+ *617+ *627+ ...) In!ut logic
:ut6(7 9 ;(*617+ *627+ ...) :ut!ut logic
DOC112: Computer Hardware Lecture 08
Slide 11
Synchronous <inary Counters

4e will loo( at #inary counters as an eam!le
of synchronous sequential circuit design.

Sim!le #inary counters ha)e =ust a cloc( in!ut.

&heir out!ut is a re!eating sequence of #inary
num#ers. &he state fli!"flo! out!uts can #e used
directly as out!uts (there is no out!ut logic).
DOC112: Computer Hardware Lecture 08
Slide 12
Synchronous <inary Counters
-or a two#!it couter. there are "our states. 0 +00,. 1 +01,.
2 +10,. ad 3 +11,
There are % complete couti* se)ueces:

0#/1#/2#/3#/0 etc

0#/1#/3#/2#/0 etc

0#/2#/3#/1#/0 etc

0#/2#/1#/3#/0 etc

0#/3#/1#/2#/0 etc

0#/3#/2#/1#/0 etc

0d more i" ot all the states are used
DOC112: Computer Hardware Lecture 08
Slide 13
. &wo"<it <inary >! Counter
&he sequence is: / "0 1 "0 2 "0 ? "0 /
DOC112: Computer Hardware Lecture 08
Slide 14
&wo"<it <inary >! Counter " Design
&he first ste! is to construct the truth ta#le of a
synchronous circuit " its &ransition &a#le.
&he transition ta#le shows the state out!ut )alues
after the cloc( !ulse (net) as a function of the
in!ut and state out!ut )alues #efore the cloc(
!ulse (now).
Since for a D ty!e fli!"flo! the out!ut (*) after the
cloc( !ulse is equal to the in!ut (D) #efore the
cloc( !ulse+ the transition ta#le #ecomes a
sim!le in!ut@out!ut truth ta#le.
DOC112: Computer Hardware Lecture 08
Slide 15
&wo"<it Counter &ruth &a#le and
-arnaugh Aa!
D1 $ Q1 % Q& ' Q1 % Q&( $ Q1 Q&
D& $ Q&(
!no"# !next#
Q1 Q& Q1 Q&
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
DOC112: Computer Hardware Lecture 08
Slide 1%
&wo"<it Counter" &he 'inal Circuit
DOC112: Computer Hardware Lecture 08
Slide 1&
Design of a controlled ?"#it
counter with don%t care states
4e are gi)en the following
descri!tion of a synchronous
sequential ?"#it #inary
counter:
C
Cloc)
Q*
Q&
Q1
Controlled
counter

1he iput C20 the couter couts up e3e
um!ers: 000 #/ 010 #/ 100 #/ 110 #/ 000 #/ etc

1he iput C21 the couter couts dow odd
um!ers: 000 #/ 111 #/ 101#/ 011#/ 001#/ 000
DOC112: Computer Hardware Lecture 08
Slide 18
Bro#lem &ime: 4hat does the state
transition diagram loo( li(eC

1he iput C20 the couter couts up e3e um!ers:
000 #/ 010 #/ 100 #/ 110 #/ 000 #/

1he iput C21 the couter couts dow odd um!ers:
000 #/ 111 #/ 101#/ 011#/ 001#/ 000
DOC112: Computer Hardware Lecture 08
Slide 1'
Bro#lem &ime: 4hat does the state
transition diagram loo( li(eC

1he iput C20 the couter couts up e3e um!ers:
000 #/ 010 #/ 100 #/ 110 #/ 000 #/

1he iput C21 the couter couts dow odd um!ers:
000 #/ 111 #/ 101#/ 011#/ 001#/ 000
DOC112: Computer Hardware Lecture 08
Slide 20
Controlled ?"#it counter
&he s!ecification shows that not all states are
included in the counting sequences.
Dowe)er+ these $don%t care$ states must
included in the design.
4e must chec( to see that the circuit is safe
when we switch it on.
DOC112: Computer Hardware Lecture 08
Slide 21
Controlled ?"#it counter
Bossi#le ways of dealing with unused states:
1. If the counter finds itself in one of the unused
states+ it should return to a (nown state after
one cloc( !ulse.
2. &he counter can return to any state.
DOC112: Computer Hardware Lecture 08
Slide 22
Controlled ?"#it counter " Design
Ste! 1
&he transition ta#le
is !roduced.
&he don%t care
out!uts E indicate
a state which is
not !art of the
counting
sequence:

C Q1 Q& Q* D1 D& D*
0 0 0 0 0 1 0
0 0 0 1 4 4 4
0 0 1 0 1 0 0
0 0 1 1 4 4 4
0 1 0 0 1 1 0
0 1 0 1 4 4 4
0 1 1 0 0 0 0
0 1 1 1 4 4 4
1 0 0 0 1 1 1
1 0 0 1 0 0 0
1 0 1 0 4 4 4
1 0 1 1 0 0 1
1 1 0 0 4 4 4
1 1 0 1 0 1 1
1 1 1 0 4 4 4
1 1 1 1 1 0 1

DOC112: Computer Hardware Lecture 08
Slide 23
Controlled ?"#it counter " Design
Ste! 2: &he -arnaugh ma! minimisation.
D* $ CQ
&
'CQ
*
('CQ
1
D1 $ C(Q
1
(Q
&
'C(Q
1
Q
&
('CQ
*
('CQ
1
Q
&
D& $ Q
&
(Q
*
('Q
1
Q
&
(
DOC112: Computer Hardware Lecture 08
Slide 24
Design Strategy
If the counter can return to any state from an
un(nown state+ then:
Fetain the donGt care states
Chec( to see that the circuit is safe after
design.
DOC112: Computer Hardware Lecture 08
Slide 25
Controlled ?"#it counter " Design
Ste! ?: &he Fealised &ransition &a#le (1s and /s)
D1 $ C(Q
1
(Q
&
'C(Q
1
Q
&
('CQ
*
('CQ
1
Q
&
D& $ Q
&
(Q
*
('Q
1
Q
&
(
D* $ CQ
&
'CQ
*
('CQ
1
DOC112: Computer Hardware Lecture 08
Slide 2%
Controlled ?"#it
counter " Design
Ste! H: Broduce the correct
transition ta#le (without
don%t cares) I the transition
diagram.
Indicate the state transitions
#y State 3um#ers (/ to J).
S!ecifications satisfied
#ecause for either control
in!ut case the counter will
e)entually reach State /.
C Q1 Q& Q* D1 D& D* S
!tn#
S
!tn'1#
0 0 0 0 0 1 0 0 &
0 0 0 1 0 0 0 1 0
0 0 1 0 1 0 0 & +
0 0 1 1 1 0 0 * +
0 1 0 0 1 1 0 + ,
0 1 0 1 1 1 0 - ,
0 1 1 0 0 0 0 , 0
0 1 1 1 0 0 0 . 0

1 0 0 0 1 1 1 0 .
1 0 0 1 0 0 0 1 0
1 0 1 0 1 0 1 & -
1 0 1 1 0 0 1 * 1
1 1 0 0 1 1 1 + .
1 1 0 1 0 1 1 - *
1 1 1 0 1 0 1 , -
1 1 1 1 1 0 1 . -
DOC112: Computer Hardware Lecture 08
Slide 2&
?"#it counter &ransition &a#le
for C9/
C Q1 Q& Q* D1 D& D* S
!tn#
S
!tn'1#
0 0 0 0 0 1 0 0 &
0 0 0 1 0 0 0 1 0
0 0 1 0 1 0 0 & +
0 0 1 1 1 0 0 * +
0 1 0 0 1 1 0 + ,
0 1 0 1 1 1 0 - ,
0 1 1 0 0 0 0 , 0
0 1 1 1 0 0 0 . 0

DOC112: Computer Hardware Lecture 08
Slide 28
C Q1 Q& Q* D1 D& D* S
!tn#
S
!tn'1#
1 0 0 0 1 1 1 0 .
1 0 0 1 0 0 0 1 0
1 0 1 0 1 0 1 & -
1 0 1 1 0 0 1 * 1
1 1 0 0 1 1 1 + .
1 1 0 1 0 1 1 - *
1 1 1 0 1 0 1 , -
1 1 1 1 1 0 1 . -
?"#it counter &ransition &a#le for
C91
DOC112: Computer Hardware Lecture 08
Slide 2'
Ste! K. <uild the circuit. Dere we will assume
that any #asic gate (.3D+ :F+ 3.3D+ 3:F+
E:F+ E3:F+ In)erter) can #e used. 'rom the
-"ma!s we ha)e:

D1 2 C561562 7 C561625 7 C6162 7 C635

2 C5+6162, 7 C+6162 7 635,

D2 2625635 7 61625

2 625!61 7 635#

D3 2C61 7 C635 7 C62

2 C+61 7 62 7 635,

2 C+ !61 7 635# 7 62,

Co//on ter/s are
0rac)eted as the1
can 0e shared
0et"een ex2ressions
3#!it couter Trasitio Ta!le
DOC112: Computer Hardware Lecture 08
Slide 30
Controlled ?"#it counter " circuit