EE535 Lab CSU GY Robinson Laboratory Handout # 2 1 of 10

Lasi_inst_2.doc lasi_inst.pdf 08/26/03

Introduction to LASI and a Short Tutorial ver. 7.0
(modified from EE 333 Lab Instructions by Professor G. Tuttle at Iowa State University)

Installing the software

LASI is already installed on the PCs in the campus ECE labs. If you want to run LASI on your own Windows machine,
the program is freeware and installation is fairly simple, just follow the instructions at the LASI web site. For use at
CSU or at home, you must also setup your drawing data folder for EE534/5. Do this before proceeding with this
tutorial. See full installation instructions at

www.engr.colostate.edu/EE534/lasi/lasi_list.html

General information and commentary
LASI is short for LAyout System for Individuals(ists). LASI is a PC-based computer-aided design (CAD)
program used for design of the physical layout of integrated circuits. LASI is used to create and arrange
polygons (pushing polygons) which correspond to the regions (i.e., drain, metal interconnect, etc.) that
compose each device (i.e., MOST, resistor, etc.) in an IC. LASI is basically a two-dimensional drawing
program. The drawing created is called a layout.
When you do your layout, the patterns must be defined according to the rules of some particular fabrication
process. We could define our own process rules, but for the purposes of EE534/5, it makes more sense to use
one of the sets that comes with the LASI program and is widely used in industry. If you look in the LASI7
folder or use the START menu to look at the options under Programs -> LASI 7, you should see items like
Wcn20, W2uchip, Wmosis. These are the different processes that we could use. For all the CMOS layouts in
EE535, we will use the MOSIS process and this tutorial is written with this assumption. Notice that the files
that you copied from the EE534_setup folder on the t: drive included a file Mosis.drc. This file contains the
layout rules for the MOSIS fabrication process and this file will be used to check your layouts.

When you start LASI, the program comes up in the drawing mode, where you define the patterns that make up
the layout. A dialog asks you to name (i.e., Load) a new cell or open an existing one. For now, click on List ,
double click on MIRRORS, and hit OK
. (You are looking at the layout of a
current mirror circuit).

The program window is organized in
the following manner:

1) Program commands along the top
-- these provide system functions
like "save", "help", "sys", etc. or
functions that control the view of
the layout.
2) Drawing commands (or buttons)
on the right -- for creating and
editing the patterns
3) Program information along the
bottom.
4) Drawing area in the center.




EE535 Lab CSU GY Robinson Laboratory Handout # 2 2 of 10

There is an on-line help system that can be accessed thru the Help menu. The information in the help system is
sometimes a bit difficult to decipher, but it is the best place to start. To get help about a command or menu
selection, hold down the F1 key while left clicking on the command button or menu selection of interest.

The construction of a circuit layout is done through a hierarchy of cells. You will be creating a number of cells
and each cell will be assigned a rank between 1 and 15. One cell can contain other cells of lower rank, but
cannot contain cells of equal or higher rank. For example, suppose that your goal is to construct a OP AMP.
One way to proceed would be to start by defining two rank 1 cells -- a PMOS and an NMOS transistor. Then
you could define a rank 2 cell a current mirror -- that would be built up using the PMOS and NMOS transistor
cells you had defined earlier. The next logical progression would be a rank 3 cell -- the OP AMP -- that would
be built up of a collection of rank 1 & 2 cells. The basic idea is to construct a set of building blocks that can be
used over and over again in the process of putting together the circuit. This is how digital designers are able to
build such huge ICs -- if it were necessary to hand-craft each and every transistor of a one-million gate
circuit, it would take forever. For EE534/5, we will use only rank 1 and rank 2 cells.

The patterns that are put in place to define the transistors and circuits are aligned to a grid pattern. When you
load a new cell, you should see the grid. If not, check the Grid drawing command along the right side of the
screen is on (button depressed). Make sure the R button in the lower right corner is depressed, to turn on the
marker of the origin of the grid. Then hit Fit at the top of the screen. This will put the origin of the grid axis at
the center of the drawing window. Then click on Xpnd at the top of the screen 3 to 4 times until you can
clearly see the grids points.

The MOSIS process starts with the grid spacing set to a 0.8 m. This is also the minimum feature size for the
EE535 MOSIS process. You shouldn't need to change this, although when drawing large polygons, you can set
the grid spacing to 4 or 8 m by clicking repeatly on the Wgrd and Dgrd buttons. Make sure to return both
grid spacings to 0.8 m, as indicated in the lower left corner of the screen, before continuing your layout. Now
just scale all the dimensions of your layout in units of , so that all lenghts will be integral multiples of the
grid spacing.

Each of the fab processes has design rules that go along with it. The design rules specify the minimum that can
be used for some of the features or the minimum separations between features. For instance, in the MOSIS
process, the minimum width of a polysilicon line (and hence the minimum drawn gate length) is 2 or 1.6 m.
You will need these rules close at hand when you are doing your layout, so use your hard copy of the MOSIS
layout rules (document mosis_dr.pdf) which you should download from the EE534 LASI web site at
http://www.engr.colostate.edu/EE534/lasi/lasi_list.html

If you would like to see what can be done with LASI, go to Start -> Programs -> LASI 7 -> W2uchip and at
the opening dialog box, hit the List button and go to the bottom of the list and select the cell named
2UCHIP(5). The number 5 indicates the rank of the cell. Select Zoom from the top menu and click at two
points in the layout to see more details. Fit will restore the full cell to the screen.
The W2chip is the layout of a CMOS chip that contains several class project designs (digital not analog
unfortunately) and which were fabricated into working ICs as a tiny chip at the MOSIS wafer foundry.





Miscellaneous bits of information that might prove useful

You can't see all of the commands in the command list of the drawing window -- there are too many to view all
at once. Click the Menu button at the top right-hand corner to get Menu 2. Note that only some of the menu
items change. You can also toggle between the command menus by clicking the right mouse button anywhere
in the drawing area.

EE535 Lab CSU GY Robinson Laboratory Handout # 2 3 of 10

When you are defining the parts of a cell, you will be creating patterns for the various layers that make up the
transistors. The layer definitions should accessible through the layer table, which you can see by
clicking on the Layr drawing command (on Menu 1). If the layer table is grayed out, one of two things may be
happening:
1. You may not be working in layer table mode. Check the information at the bottom of the screen -- you
should see a comment like "Using Layer Table". If you don't see the comment, hit Layer Mode
button. The layer table should turn on (as shown below) and you should be put back into "layer table
mode". Hit OK to close the Layer Table.

2. If comment below the screen reads "Using Layer Table" and clicking on the Layer Mode button
leaves the layer table is empty, you may not be working out of a valid EE534 MOSIS folder, so the
definitions for the MOSIS process aren't available. Make sure that your directory paths are set up
correctly and that you installed all of the files from the EE534_setup folder on the t: drive into your
data folder. When correctly installed, the cell named Layers should be included in your list of cells
and looks like (List -> Layers -> Fit):


Editing your drawings will probably be the most time-consuming part of the project. If your experience is
anything like mine, your first cell when end up as a misshapen, nearly-unrecognizable blob. And so you will
need to edit it. The editing process will take some patience and some practice. Don't be afraid to experiment.

Remember that when you make your design, you should include body contacts for the transistors. You need
one body contact in each of the n-wells (where the pMOS transistors reside). In principle, only one body
contact is needed for all the nMOS transistors, since they all sit in the p-type silicon substrate. However,
conservative design practice suggests that you should include many more -- perhaps one for each "cluster" of
nMOS transistors. (We'll leave the definition of cluster to be somewhat open-ended.) Each pMOS transistor
does not have to have its own n-well. It might be possible to arrange your layout so that all the pMOSs are close
together and can share a single n-well.

EE535 Lab CSU GY Robinson Laboratory Handout # 2 4 of 10

Finally, there is no single correct way to layout your circuit. As long your design meets all the design rules,
and your circuit is wired together properly, the layout is "correct". Of course, some ways of arranging the
transistors will be more efficient in terms of total chip area used (less is better), or lengths of interconnects
(shorter is better).

A quick tutorial - creating an nMOS cell

Below is described a sequence of steps that one might use to create a cell that consists of a single nMOS transistor.
(Note: the colors and fill patterns in the figures below are intended to match what you will see in LASI, but depending
on your printer, may appear somewhat different from the LASI screen displays). The transistor has a W/L ratio of
4.8m/1.6m. The cryptic DR numbers included in the steps below refer to particular design rules. See
the MOSIS design rule list (document mosis_dr.pdf) you down loaded from the EE534 LASI web site.
The process for creating a pMOS transistor is identical, except that you must start with an n-well and,
of course, the active region would be p+ instead of n+.

1. When you first start LASI, the program will present you with a dialog where you can name a
new cell or open an existing one. If the program is already running, you can bring up this
dialog by clicking on the Load menu at the top of the window. Since we are starting from
scratch, we need a new cell. Name it something clever like "n4_8x1_6" and set the rank to 1.

2. Check that the Grid is on. When you load a new cell, you should see the grid. If not,
check the Grid drawing command along the right side of the screen is on (button
depressed). Make sure the R button in the lower right corner is depressed, to turn on
the marker of the origin of the grid. Then hit Fit at the top of the screen. This will put
the origin of the grid axis at the center of the drawing window. Then click on Xpnd at
the top of the screen 3 to 4 times until you can clearly see the grids points. Click on
Draw on the top menu to redraw the screen (do this frequently to ensure that screen is up to
date)

3. Now we want to define the source and drain regions. Select the Layr command on Menu 1,
and from the layer table check the active layer ACTV and hit OK. We want to draw the n+
active region in the drawing area. Usually, the patterns will be in the
form of rectangular boxes, and there should be some text at the
bottom of the screen stating Obj=BOX. If you don't see that, then
select the Obj command and double click on BOX. Next click on
the Add command. Move the cursor to the point where you want
one corner of the n+ region and click the left mouse button. Move
the mouse to the other corner of the region and click the mouse button again. The result should
be a box in the drawing area. Now hit the all-put command Aput to nail down the polygon
just drawn. The ACTV layer should be green in color.

The n+ region is called the "active" region for the NMOS transistors. The MOSIS design rules
decree that the active region must be bigger than 3 x 3 (DR 2.1, and that an active region
must be at least at 3 away from other active regions (DR 2.2). These rules are easy to meet. Here we chose
vertical (y) dimension to be W=6=4.8m, where W is the width of the channel. The x-dimension should be at
least 18.

4. Now we want to define the gate for the NMOS. Again, select the Layr
command, but this time choose POL1 from the layer table. (Poly stands for
polysilicon, which is the material that modern MOSFETs use for the gate.)
Check the info bar at the bottom of the screen to make certain that Obj=BOX
and Layr=POL1. Use the Add command to draw a gate across the n+ region
you defined in step 3 above. Now hit Aput. The POL1 layer is red in color.


EE535 Lab CSU GY Robinson Laboratory Handout # 2 5 of 10

The POL1 patterns region can have a minimum dimension of 2 (DR 3.1) -- meaning that the minimum drawn
gate length L for our transistors will 2. Also, the poly gate must overlap the sides of the active region by at
least 2 (DR 3.3) and must be at least 3 from ends of the active region (DR. 3.4). Note that if you are making
CMOS-based circuits, the POLl will also serve as the gate for the PMOS and you can connect the two directly
using the polysilicon layer. Here make the gate a narror vertical strip centered in the active region, with the
narrow dimension of L= 2 = 1.6 m.

Note the sequence of operations ( Layr, Add, & Aput ) needed each time you draw a new layer.


5. Next we need to tell LASI that the active layer we created in step 3 is to be n+
not p+. Choose Layr and pick the n-select layer NSEL. Then Add the
NSEL box around the outside of the active region, spaced at a distance of 2
everywhere. Hit Aput . The NSEL layer in a unfilled green pattern.

The select region must overlap the active region by 2 (DR 4.2).



6. Now we need to define contact regions. The first thing we must do is cut contact holes through the oxide that
covers the source, drain, and gate. Select the Layr command, and this time choose the contact layer CONT
from the pop-up menu. Check to make certain that the object is a box. Use
the Add command to draw the contact holes within the source and drain
regions on each side of the gate, and one contact hole below the gate by 1,
as shown. The CONT regions are solid blue.

The contact holes must be exactly 2 x 2 (DR 5.1 & 6.1). So if you have a
very wide transistor you probably will want to cut several contact holes along
the width of the source and drain regions. The contact openings must be
spaced by at least 2 (DR 5.3 & 6.3).

Notice that the poly is not touching the lower contact . I did not anticipate in step 4 where contact is to be made
to the poly layer. For the poly contact, the poly must overlap the contact region by 1 (DR 5.2). Thus, in the
spot where the poly (gate) contact is located, there must be a poly area of at
least 4 x 4. If the gate is narrow, it may then be necessary to "bulge" or
"dumbbell" the gate at the end where the contact will be located.

Thus, we Layr, Add, & Aput the additional POL1 region to enlarge
the poly layer to cover the lower contact.


7. Next, we want to add metal over the contact holes. Use the Layr
command and choose the metal 1 layer MET1 from the layer table. Then use Add to draw metal 1 over the
gate, drain, and source contacts. The metal 1 is cross-hatched blue in
color.

Metal 1 should completely overlap the contact holes by at least 1 on each
side (DR 7.3 & 7.4). The minimum width of a metal line is 3 (DR 7.1)
and there must be at least 3 of separation between metal lines (DR 7.2).


8. At this point, the n4_8x1_6 cell is almost done, and you could Save it.


EE535 Lab CSU GY Robinson Laboratory Handout # 2 6 of 10

9. This would be a good time to add a body contact (i.e., the substrate terminal) for the nMOST. In order to make
a good electrical contact to the p-type substrate, we should first introduce a small p+ region into the substrate.
We use the p-select layer PSEL to tell LASI that the active region will be p+. Do the following:

Layr -> ACTV, Add, & Aput the active region shown to the left
of the n-select region.
Layr -> PSEL, Add, & Aput the p-select region around the
active region. The PSEL is a yellow open rectangle.
Layr -> CONT, Add, & Aput the contact for the body
connection.
Layr -> MET1, Add, & Aput the metal 1 region over the
contact.


The body contacts must follow the same design rules as the contacts to the active regions. Note that we are
allowed to butt the PSEL region up against the NSEL region, as long as the active regions enclosed by each
are at least 4 apart


10. In complex circuits, it may not be possible to interconnect all of your devices using just a single layer of metal.
In those cases, there is a second layer of metal (called metal 2 layer MET2 ) available for interconnections.
After the first layer of metal, the entire wafer is coated with a thin layer of dielectric material (probably silicon
dioxide or something similar). The second layer of metal goes on
top of this dielectric. But in order to use the second layer of metal,
we must cut holes in the dielectric so that we can get access to the
first layer of metal. These holes are called vias and serve the exact
same purpose as the contact holes that we created in step 6. To
create vias for the second layer of metal, use the Layr command to
select VIA1. Then use the Add command to draw in the desired
vias.

The vias appear as filled white areas on the screen, but black when
printed (white and black are reversed in the printing process, other colors are preserved). Metal 2 is cross-
hatched white on the screen, but black in the printed version. Note the cross-hatching is in the opposite
direction to metal 1, so that even with a black-white printer you can distinguish metal 1 from metal 2.

Just like the contacts, the vias must be exactly 2 x 2 (DR 8.1). The MOSIS design rules also call for a
minimum of a 1 overlap of the vias by both the upper metal MET2 layer and the lower metal MET1 layer.


EE535 Lab CSU GY Robinson Laboratory Handout # 2 7 of 10


11. You should do a design rule check (DRC). Any good layout program will have a DRC feature that will go
through and check your cell layout to make sure that all of the dimensions, separations, and overlaps meet the
tolerances specified by the fabrication process. LASI has a built-in utility called LasiDrc which checks against
the rules in the file Mosis.drc . To perform the DRC on your layout, do the following, but be sure to Save
your layout first, since LasiDrc checks the current stored layout file not what is on the screen.

a. Start by clicking on Sys in the top menu to bring up the system dialog box. In the box, click on LasiDrc.
A small control window
will appear on top of the LASI screen.



b. Click on Setup and fill in the dialog box as shown:

Use the List button and select
<- your cell.
<- Use Browse & be sure that the
Mosis.drc file is the Check File.

<- set these boxes as shown
1 28 0.8




<- remaining boxes can be left as is
since they are not important.





<- hit OK to close the dialog box.



c. Click on Go in the LasiDrc7 control window. You can watch the progress of the check. If the DRC finds an
error, the program will pause momentarily and display a tiny picture of the layout. After the pause, the check
will continue, pausing at each error until it has completed the entire circuit. At the end, a dialog box will tell
you how many errors were "flagged". Note the number. Hit OK.

d. In the LasiDrc7 control window, hit Run and then Ok. The Lasidrc.rpt text file will open using Windows
Notepad. The errors are listed in detail. Look for Area(s) Flagged: . to determine which MOSIS rule was
violated.

e. To see a crude map of where the error(s) are in the layout, hit Map in the LasiDrc7 control window.
Select one of the pcx files (one file for each rule violation). The location of each error is highlighted in white.

f. Correct your layout as needed until LasiDrc runs without errors. Save before each re-run of LasiDrc.

EE535 Lab CSU GY Robinson Laboratory Handout # 2 8 of 10


12. To complete your cell, you might want to add some text that describes your transistor. To do this, select the
text layer command Tlyr on Menu 2. Select the outline text OTLN
and, if you want to change the text size, click on Tsze and select a
word size (1.5 is 1.5 grid spacings high). Then, click on Text and
move the cursor to the place where you want the text and click the
mouse button. In the space provided, type for example, the name of
your cell. Hit Ok and Aput.

There it is. You've created a transistor. Save it.



Editing objects & text

Naturally, you may want to alter your basic cell design (e.g. to change the W/L ratio) or simply correct mistakes.

Moving objects
Use the Get command to select the side of an object, an entire object, or a group of objects. The selection is
done by using the cursor to create a box around the object to be edited. If you select only one side, you will be
changing the size of the object by moving only that side. If choose an entire object or a group of objects, you
will move those things to a new location without changing their size. The selected object(s) will be highlighted
when selected.

Next, select the Mov command. Move the mouse to the selected object and click on it. Then move the mouse
to the new location and click again. The object should move by the same amount that you moved the cursor.

Finally, use the Put command to deselect the objects that you no longer want to move. Alternatively, you can
use the Aput command to deselect all objects.

An alternative to Get is the full get command Fget which will select all of a box or object rather than just one
side of an object. This command is handy when two objects overlap and you can grab only one side of an
object but wish to select the entire object.

Deleting objects
Use GET or Fget to select the undesired object. Then use Del to get rid of it. Be careful so that you do not
accidentally select something that you really wanted to keep. If you do, just hit Aput to turn off the select
function.

Redrawing the figures
As you edit the layout, the figures are not automatically redrawn. After a bit of editing, it may appear that
portions of your layout have disappeared. Use Draw on the top menu to redraw the layout. All of the missing
parts and the grid should appear.

Saving or Copying your layout
Click on Save on the top menu and then OK to save the current cell. If you want to create a new cell that is
an exact copy of the existing cell, then enter a new cell name and hit OK, OK. The new cell is placed in the
current data folder (i.e., the data folder that contains the existing cell) and LASI opens in the new cell.

To safely copy cells from your current data folder to a different data folder (i.e., from CSU to home PC), use the
Export and Import commands. LASI uses a special file format (file extension .TLC). Move only the TLC files
between data folders. LASI does not use the conventional Windows LOAD and SAVE commands for data files.
Do not use Win 95/98/NT Copy & Paste to move individual files from your data folder to elsewhere!

EE535 Lab CSU GY Robinson Laboratory Handout # 2 9 of 10

Undo
Using the Undo command takes you back to the cell as it was the last time the you saved it. Note that the undo
in LAS1 behaves somewhat differently than the undo commands in other programs. The behavior of the undo
suggests that it is a good idea to save your drawing frequently.

Editing text
First make sure that the T button is depressed in the lower right corner, and hit Draw. This will turn on the
text marker, the small diamond-shaped reference mark at start of text string. To delete existing text, use the text
get command Tget and left click on each side of the text marker so as to enclose the marker. The text should
become highlighted. Hit Del .

To edit existing text, hit Text and left click on the center of the text marker. The text dialog box should come
up and you can edit the existing text.

If you wish to change the size of some existing text or all of the existing text, hit Tget and then left click at
two points than encompass all the text markers of interest. Next hit Csiz and change the size of the highlighted
text.


Advanced operations - Creating a higher rank cell from lower rank cells

For example we wish to layout a CMOS current mirror circuit, consisting of two identical nMOS transistors
and one resistor.
First layout a nMOST cell at rank 1 as in the above tutorial but with minimal metal layers over each
contact and without the substrate (body) contact. Call it N_MOST. Save it.

Second, create a rank-1 cell containing the layout of the resistor, again with minimal metal layers over
each contact. Call it R_1. Save it.

Then create a rank-2 cell which will be the current mirror, to be called MIRROR. This cell will need
to contain two copies of your N_MOS cell and one copy of your R_1 cell. To "copy" a rank 1 cell
into a rank 2 cell do the following:

1. Hit the command button OBJ and the dialog box should now list N_MOS and R_1 along with
the usual BOX and POLY/PATH selections. Double click on N_MOS and then hit Add.

2. A dotted box should now be attached the cursor. The box indicates the size and placement of the
N_MOS cell. Click in the drawing area to place the first N-MOS cell in the desired location. Move
the cursor and place the second N_MOS cell.

3. Hit the cell put command Cput to nail down the two rank-1 cells. If you need to go back and
move a cell, use the cell get command Cget and Mov and Aput.

Repeat the same steps to place the R_1 cell in MIRROR.

Now add a body contact for the nMOS transistors in the rank-2 MIRROR layout, following the
procedure in step 9 of the tutorial.

Finally add metal 1 to interconnect the two transistors and resistor in the MIRROR layout. Use vias
and metal 2 if necessary.

Your circuit is finished. Save it.
EE535 Lab CSU GY Robinson Laboratory Handout # 2 10 of 10


Note that if it is necessary to go back and edit the transistors (e.g. increase W), you can load cell N_MOS, edit
it, and all changes made will also be made to both n_MOS cells in MIRROR.


Advanced operations - Layout of Resistors using Path

Resistor can be laid out using the Box method above. Since a resistor is usually laid out in a folded or serpentine
fashion, it may be easier in LASI to draw the resistor layer using Path rather than Box as the drawing technique:
Go to Obj then choose POLY/PATH.
Hit Wdth and then enter the width of the resistor in microns in the Path Width box and set the Path End to
Endline.
Click on Add.
Now click in the drawing area at each vertex of the folded resistor. This will take some practice. Turn on the
display of the centerline and vertices of the path by depressing the C and V buttons and hitting Draw in the
top menu. To terminate the path, hit Aput.
An example:













Be sure to return to the box drawing mode by hitting Obj and BOX.


LASI can also readily calculate the resistance in ohms of your folded resistor layout. For automatic correction of end
effects and corner effects, the resistance command Res used below must be already set up with the proper values of
sheet resistance, path width, etc. Otherwise, you can use the Manual button and obtain a rough estimate of the
resistance. Do the following
Use Get to select all or some part of your resistor you laid out with
the path (not box) command above.
Select Res and scroll through the Auto R Param No. by using
the < > buttons. Definitions are:

R/sq = sheet resistance (ohms/sq)
End = correction for both ends (ohms)
Wdth = width (microns)
Cnr = correction for each corner (ohms)

Select which Auto R Param No fits your layout, and hit Continue.
The resistance is calculated and displayed in the box below the
drawing area. The white dotted line shows the path which was used
for the calulation. You may need to hit Add and Aput to clear the
Res box.

vertex 1
vertex 2
vertex 3