A

PROJECT REPORT
ON
PERFORMANCE ANALYSIS OF ONE BIT
FULL ADDER USING DOMINO LOGIC
Submitted in partial fulfillment of the requirements for the
Award of the Degree
of
BACHELOR OF TECHNOLOGY
In

ELECTRONICS AND COMMUNICATION ENGINEERING

By
T. Ganesh (21C35A0437)
D. Ashritha (21C35A0410)
Musheer Ahmed Khan (20C31A0483)
K. Rohith (21C31A0419)
G. Ganesh (20C35A0473)

Under the Guidance of

Mr.K.Srikanth
Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

BALAJI INSTITUTE OF TECHNOLOGY & SCIENCE
Laknepally (v), Narsampet (M), Warangal (D) - 506331, Telangana, India
Accredited by NBA, NAAC A+ Grade & ISO 9001:2015 Certified Institution
(Affiliated to JNT University, Hyderabad and Approved by the AICTE, New Delhi)
November 2023
BALAJI INSTITUTE OF TECHNOLOGY & SCIENCE
Laknepally (v), Narsampet (M), Warangal (D) - 506331, Telangana, India
(AUTONOMOUS)
Accredited by NBA, NAAC A+ Grade & ISO 9001:2015 Certified Institution
(Affiliated to JNT University, Hyderabad and Approved by the AICTE, New Delhi)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

CERTIFICATE

This is to certify that this Project Work entitled "PERFORMANCE ANALYSIS OF

ONE BIT FULL ADDER USING DOMINO LOGIC" is a bonafide work carried out
by T. Ganesh (21C35A0437), G. Ashritha (21C35A0410), Musheer Ahmed Khan
(20C35A0483) K. Rohith (21C35A0419) and G. Ganesh (20C35A0473) in partial
fulfillment of the requirements for the award of the degree of Bachelor of Technology
from JNTUH, Hyderabad during the period 2022-23 under our guidance and
supervision.

Internal Guide Head of the Dept.

K.Srikanth Dr.R.Mohandas
Assistant Professor, Associate Professor,
Dept. of ECE Dept. of ECE

EXTERNAL EXAMINER
 DECLARATION

We, T. Ganesh (21C35A0437), G. Ashritha (21C35A0410), Musheer Ahmed

Khan (20C35A0440), K. Rohith (20C35A0419) and G.Ganesh (20C1A0473) hereby
declare that the project entitled “Performance Analysis Of One Bit Full Adder Using
Domino Logic”, submitted in the partial fulfillment of the requirements for the award of
B.Tech in Electronics and Communication Engineering to Balaji Institute of Technology
& Science, Narsampet, affiliated to JNTUH, Hyderabad is a authentic work and has not
been submitted to any other university or institution for award of the degree.

T. Ganesh (21C35A0437)
G. Ashritha (21C35A0410)
Musheer Ahmed Khan (20C31A0483)
K. Rohith (21C35A0419)
G.Ganesh (20C31A0473)

i
 ACKNOWLEDGEMENT

It is a great pleasure to express our deepest sense of gratitude and indebtedness, to

our Internal guide K.Srikanth, Assistant Professor, Dept. of ECE, BITS, Narsampet, for
having been a source of constant inspiration, precious guidance and generous assistance
during the project work. We deem it as a privilege to have worked under his able
guidance. Without his close monitoring and valuable suggestions this work wouldn’t
have taken this shape. We feel that this help is un-substitutable and unforgettable.

We wish to express our sincere thanks to Dr.V.S.Hariharan, Principal, BITS,

Narsampet for providing the college facilities for the completion of the project.

We are profoundly thankful to Dr.R.Mohandas, Head of ECE Dept, for his

cooperation and encouragement.

We are greatly thankful to our Project coordinator Mr.V.Karthik Kumar, Asst.

Prof., Dept. of ECE, BITS, Narsampet for his support throughout our project.

Finally, we thank all the faculty members, supporting staff of ECE Dept. and
friends for their kind co-operation and valuable help for completing the project work.

T.Ganesh (21C35A0437)
G.Ashritha (21C35A0410)
Musheer Ahmed Khan (20C31A0483)

K. Rohith (21C35A0419)
G.Ganesh (20C31A0473)

ii
 ABSTRACT

In modern VLSI area efficient devices are most used most of the devices are
becoming portable. The Domino logic technique is often employed in designing the area
efficient and high-speed devices. In this Project, One- bit full adder circuit using CMOS
based logic and domino- based logic on Tanner EDA Tool has been designed based on
250nm technology having the supply voltage of 3V. This Project is mainly centralized on
the design of area efficient and fast speed devices. This work evaluates the performance
CMOS and Domino logic based on full adder circuit in terms of delay and power
consumption. It was found that Domino logic based one - bit full adder circuit occupied
28.57% lesser area and introduces 47.36% less delay as comparison to one -bit full adder
circuit based on CMOS logic.

Keywords: CMOS, Domino, Full adder, Performance Parameters.

iii
 LIST OF FIGURES

Figure No. Title Page No

1.1 VLSI Design Flow 04

1.2 Physical Design Process 09
1.3 Half Adder 13
1.4 Full Adder 14
3.1 CMOS Logic 18
3.2 CMOS Inverter 19
3.3 CMOS NAND 20
3.4 CMOS NOR 21
3.5 Domino Logic 22
3.6 CMOS Full Adder 23
3.7 Domino Full Adder 25
5.1 Inverter Design using CMOS 35
5.2 Results of CMOS Inverter 35
5.3 Full Adder Design using CMOS 36
5.4 Results of CMOS Full Adder 36
5.5 Full Adder Design using Domino Logic 37
5.6 Results of Domino Full Adder 37

iv
 LIST OF TABLES

1.1 Truth Table of Half Adder 13

1.2 Truth table Of Full adder (1 Bit) 14
3.1 CMOS Inverter 19
3.2 CMOS NAND 21
3.3 CMOS NOR 21

v
 LIST OF ACRONYMS

1 ALU Arithmetic and Logical Unit

2 CMOS Complementary Metal-Oxide Semiconductor
3 NMOS N-channel Metal-Oxide Semiconductor
4 PMOS P-channel Metal-Oxide Semiconductor
5 GDI Gate Diffusion Input
6 PTL Pass Transistor Logic
7 S-EDIT Schematic Edit
8 T-EDIT Simulation Edit
9 W-EDIT Waveforms Edit Layout Edit
10 L-EDIT Layout Edit
11 EDA Electronic Design Automation

vi
 CONTENTS

Declaration i
Acknowledgement ii
Abstract iii
List of Figures iv
List of Tables v
Lists of Acronyms vi

CHAPTER NO TITLE. PAGE NO.

1
1. INTRODUCTION
1.1 INTRODUCTION 1
1.2 IMPORTANE OF HYBRID ADDER 2
1.3 VLSI DESIGN CYCLE 4
1.3.1 System Specification 4
1.3.2 Functional Design 4
1.3.3 Logic Design 5
1.3.4 Circuit Design 5
1.3.5 Physical Design 5
1.3.6 Design Verification 5
1.3.7 Fabrication 6
1.3.8 Packaging, Testing And Debugging 6
1.4 PHYSICAL DESIGN CYCLE 6
1.4.1 Partitioning 6
1.4.2 Placement 7
1.4.3 System Level Placement 8
1.4.4 Board Level Placement 8
1.4.5 Chip Level Placement 8
1.4.6 Floor Planning 8
1.4.7 Routing 9
1.5 VLSI DESIGN STYLES 10
1.6 SIMULATION 10
1.7 TYPES OF SIMUATION 10
 1.7.1 Device Level Simulation 11
1.7.2 Circuit Level Simulation 11
1.7.3 Switch Level Simulation 11
1.7.4 Gate Level Simulation 11
1.7.5 RTI Simulation 11
1.7.6 System Level Simulation 11
1.8 ADDERS 12
1.9 ADDERS ARCHITECTURE 12
1.10 TYPES OF ADDERS 12
1.10.1 Half Adder 12
1.10.2 Full Adder 13
2. LITERATURE SUREY 14
3. BLOCKDIAGRAM & WORKING PRINCIPLE
3.1 CMOS Logic 18
3. 2 Types of CMOS logic gates 19
3.2.1 CMOS Inverter 19
3.2.2 CMOS NAND 20
3.2.3 CMOS NOR 20
3.3 Domino Logic 22
3.4 CMOS Full Adder 23
3.5 Domino Logic Full Adder 25
4. INTRODUCTION TO TANNER TOOL
4.1 WHAT IS TANNER TOOL 26
4.2 SCHEMATIC EDIT TOOL (S-EDIT) 26
4.2.1 Beginning a Design 26
4.2.2 Browser 26
4.3 T-SPICE PRO CIRCUIT ANALYSIS 27
4.3.1 Schematic Data Files(.sdb) 27
4.3.2 Simulation Input Files (.sp /.spc) 27
4.3.3 Simulation Output Files (.out) 27
4.4 CIRCUIT SIMULATOR(T-SPICE) 27
4.4.1 DC Operating Point Analysis 28
4.4.2 DC Transfer Analysis 29
4.4.3 Transient Analysis 29
 4.4.4 AC Analysis 29
4.4.5 Noise Analysis 30
4.5 WAVEFORM EDIT 30
4.6 LAYOUT (L-EDIT) 31
4.6.1 L- Edit : An Integrated Circuit Layout Tool 31
4.6.2 Cells: The Basic Building Blocks 32
4.6.3 Hierarchy 32
4.6.4 Design Features 32
4.6.5 Floor Plans 33
4.6.6 Memory Limits 33
4.6.7 Hard Copy 33
4.6.8 Variable Grid 33
4.6.9 Error Recovery 33
5. RESULTS AND ANALYSIS
5.1 DESIGN UNIT 35
5.1.1 CMOS inverter 35
5.1.2 CMOS Full Adder 36
5.1.3 Domino Logic Full Adder 37
6. ADVANTAGES AND APPLICATIONS
6.1 Advantages 38
6.2 Applications 38
7. CONCLUSION AND FUTURE SCOPE
7.1 Conclusion 39
7.2 Future Scope 39
REFERENCES
 CHAPTER 1
INTRODUCTION

1.1 INTRODUCTION

In the realm of digital logic design, striking the right balance between speed, power
efficiency, and area utilization is a perpetual challenge. One critical avenue in addressing this
challenge is the choice of logic families employed in digital circuitry. This project delves into the
performance analysis of a one-bit full adder designed using domino logic—a dynamic, high-speed
logic family. The primary focus of this study is to assess the advantages and trade-offs of using
domino logic in comparison to traditional static CMOS logic. By evaluating factors such as speed,
power consumption, and area efficiency, this research aims to provide insights into the viability of
domino logic for essential arithmetic circuits, thus contributing to the ongoing optimization of
digital system design.

1.1.1 Background
In the digital logic design landscape, domino logic represents a dynamic approach that
deviates from the traditional static CMOS (Complementary Metal-Oxide-Semiconductor) logic.
Domino logic leverages dynamic precharge and evaluate principles, allowing signal flow
through a sequence of transistors that are dynamically turned on and off. This design philosophy
brings the promise of high-speed operation, making it an attractive option in scenarios where
rapid signal processing is essential.

Static CMOS logic, on the other hand, is revered for its stability and power efficiency. It
serves as the foundation for countless digital circuits, offering consistent performance with
minimal power consumption. However, it often falls short in speed-critical applications,
sparking the need for alternative design methodologies.

One of the pivotal components in digital circuit design is the full adder. Full adders play a
central role in arithmetic operations, serving as the nucleus for binary addition. Their efficient
performance greatly influences the overall functionality of digital systems. In this context, the
choice of logic style used to implement full adders assumes paramount importance, as it can
significantly affect a system's speed, power consumption, and area utilization.

1
 1.2 Importance of Full Adder:

A full adder is a fundamental building block in digital electronics and plays a crucial role in
arithmetic operations, especially in binary addition. Its importance lies in several key aspects:

Binary Addition: Full adders are used to add two binary numbers together. They can handle the
addition of bits and generate a sum and carry output. This operation is essential in various digital circuits,
including microprocessors, memory units, and more.

Arithmetic Functions: Full adders are the basis for performing various arithmetic functions like
subtraction, multiplication, and division when combined with other logic gates and additional circuitry.

Ripple Carry Adder: Multiple full adders can be connected in a ripple carry configuration to
perform multi-bit binary addition. This is the foundation for adding multi-bit numbers in computers and
digital systems.

Carry Propagation: The carry-out generated by one full adder is used as the carry-in for the next
full adder in a multi-bit addition operation. This carry propagation is critical for accurately adding larger
binary numbers.

Logical Functions: Full adders have versatile applications in various logic circuits beyond just
arithmetic. They can be used to implement a wide range of logical functions and create complex digital
circuits.

Data Processing: Full adders are integral to data processing operations in digital systems,
including ALU (Arithmetic Logic Unit) designs in CPUs, memory addressing, and data manipulation.

Hardware Design: Full adders serve as a foundational building block in digital hardware design,
allowing engineers to create complex digital systems for various applications, from simple calculators to
advanced computers.

2
 Error Detection and Correction: Full adders are used in error detection and correction codes in
digital communication systems, ensuring data integrity and reliability.

Real-World Applications: Full adders are used in a wide range of electronic devices and systems,
from computers and smartphones to calculators and embedded systems. They are crucial for any digital
device that involves arithmetic and logical operations.

In summary, the full adder is of utmost importance in the world of digital electronics, providing
the basic functionality for binary addition and serving as a building block for more complex digital
circuits and systems. Its applications span a wide range of industries, from computer engineering to
telecommunications and beyond.

3
1.3 VLSI DESIGN CYCLE
The design process of producing a package VLSI chip physically follows various steps
which is popularly known as VLSI design cycle. This design cycle is normally represented by a
flow chart shown below. The various steps involved in the design cycle are elaboratedbelow.

Fig :1.1 VLSI Design Flow

1.3.1 System Specification:

The specifications of the system to be designed are exactly specified in this step. It
considers performance, functionality, and the physical dimensions of the design. The
choice offabrication technology and design techniques is also considered. The end results
are specifications for the size, speed, power, and functionality of the VLSI system to be
designed.

1.3.2 Functional Design:

In this step, behavioral aspects of the system are considered. The outcome is
usually a timingdiagram or other relationships between sub-units. This information used
to improve the overall design process and to reduce the complexity of the subsequent
phases.

4
1.3.3 Logic Design:
In this step, the functional design is converted into a logical design, using the
Boolean expressions. These expressions are minimized to achieve the smallest logic
design which conforms to the functional design. This logic design of the system is
simulated and tested toverify its correctness.

1.3.4 Circuit Design:

This step involves conversion of Boolean expressions into a circuit representation
by takinginto consideration the speed and power requirements of the original design. The
electrical behavior of the various components is also considered in this phase. The circuit
design is usually expressed in a detailed circuit diagram.

1.3.5 Physical Design:

In this step, the circuit representation of each component is converted into a
geometric representation. This representation is a set of geometric patterns which perform
the intended logic function of the corresponding component. Connections between
different components are also expressed as geometric patterns. (This geometric
representation of a circuit is calleda layout). The exact details of the layout also depend
on design rules, which are guidelines based on the limitations of the fabrication process
and the electrical properties of the fabrication materials. Physical design is a very
complex process; therefore, it is usually broken down into various sub-steps in order to
handle the complexity of the problem.

1.3.6 Design Verification:

In this step, the layout is verified to ensure that the layout meets the system
specifications and the fabrication requirements. Design verification consists of design rule
checking (DRC)and circuit extraction. DRC is a process which verifies that all geometric
patterns meet the design rules imposed by the fabrication process. After checking the
layout for design rule violations and removing them, the functionality of the layout is
verified by circuit extraction.This is a reverse engineering process and generates the circuit
representation from the layout.This reverse engineered circuit representation can then be
compared to the original circuit representation to verify the correctness of the layout.

5
 1.3.7 Fabrication:
This step is followed after the design verification. The fabrication process consists
of severalsteps like, preparation of wafer, deposition, and diffusion of various materials
on the wafer according to the layout description. A typical wafer is 10 cm in diameter
and can be used to produce between 12 and 30 chips. Before the chip is mass produced, a
prototype is made and tested.

1.3.8 Packaging, Testing And Debugging:

In this step, the chip is fabricated and diced in a fabrication facility. Each chip is
then packaged and tested to ensure that it meets all the design specifications and that it
functionsproperly. Chips used in printed circuit boards (PCBs) are packaged in a dual in-
line package (DIP) or pin grid array (PGA). Chips which are to be used in a multichip
module (MCM) are not packaged because MCMs use bare or naked chips.

1.4 PHYSICAL DESIGN CYCLE

The Physical design cycle converts a circuit diagram into a layout. This complex task is
completed in several steps, like partitioning, floor-planning, placement, routing, and lay-out
compaction etc. The details of these steps are given below.

1.4.1 Partitioning:
The chip layout is always a complex task and hence it is divided into several
smaller tasks. A chip may contain several million transistors. Layout of the entire circuit
cannot be handleddue to the limitation of memory space as well as computation power
available. Therefore, it is normally partitioned by grouping the components into blocks.
The actual partitioning process considers many factors such as size of the blocks, number
of blocks, and number ofinterconnections between the blocks. The output of partitioning
is a set of blocks along with the interconnections required between blocks. The set of
interconnections required is referred to as a net list. In large circuits the partitioning
process is hierarchical and at the topmost level a chip may have between 5 and 25 blocks.
Each module is then partitioned recursively into smaller blocks. A disadvantage of the
partitioning process is that it may degrade the performance of the final design. During

6
partitioning, critical components should be assigned to the same partition. If such an
assignment is not possible, then appropriate timing constraints must be generated tokeep
the two critical components close together. Usually, several components, forming a
critical path, determine the chip performance. If each component is assigned to a
different partition, the critical path may be too long. Minimizing the length of critical
paths improvessystem performance.
After a chip has been partitioned, each of the sub-circuits must be placed on a
fixed plane and the nets between all the partitions must be interconnected. The
placement of the sub-circuits is done by the placement algorithms and the nets are routed
by using routing algorithms.

1.4.2 Placement:
It is the process of arranging a set of modules on the layout surface. Eachmodule
has fixed shape and fixed terminal locations. A poor placement uses larger area andhence
results in performance degradation.
The placement process determines the exact positions of the blocks on the chip, so
as to find a minimum area arrangement for the blocks that allows completion of
interconnections between the blocks. Placement is typically done in two phases. In the
first phase an initial placement is created. In the second phase the initial placement is
evaluated and iterative improvements are made until the layout has minimum area and
conforms to design specifications.
It is important to note that some space between the blocks is intentionally left
empty to allow interconnections between blocks. Placement may lead to un-routable
design, i.e., routing may not be possible in the space provided. Thus, another iteration of
placement is necessary. To limit the number of iterations of the placement algorithm, an
estimate of the required routing space is used during the placement phase. A good
routing and circuit performance heavily depend on a good placement algorithm. This is
due to the fact that once the position of each block is fixed, very little can be done to
improve the routing and the overall circuit performance. There are various types of
placements.

7
1.4.3 System Level Placement:
Place all the PCBs together such that Area occupied is minimum and. Heat
dissipation is within limits.

1.4.4 Board Level Placement:

All the chips have to be placed on a PCB. Area is fixed all modules of rectangular
shape. The objective is to, minimize the number of routing layers and Meet system
performance requirements.

1.4.5 Chip Level Placement:

Normally, floor planning / placement carried out along with pin assignment. It
has limited number of routing layers (2 to 4). Bad placements may be unroutable. Can be
detected onlylater (during routing). Costly delays in design cycle. Minimization of area.

1.4.6 Floor planning:

Floor-plan design is an important step in physical design of VLSI circuits to plan
the positions of a set of circuit modules on a chip in order to optimize the circuit
performance. In floor-planning, the information of a set of modules, including their areas
and interconnection is considered and the goal is to plan their positions on a chip to
minimize the total chip area and interconnect cost.

In the floor planning phase, the macro cells are positioned on the layout surface in
such a way that no blocks overlap and that there is enough space left to complete the
interconnections. The input for the floor planning is a set of modules, a list of terminals
(pins for interconnections) for each module and a net list, which describes the terminals
which have to be connected.

8
 Fig:1.2. Physical Design Process

1.4.7 Routing:
The main objective in this step is to complete the interconnections between blocks
accordingto the specified net list. First, the space not occupied by the blocks (called the
routing space)is partitioned into rectangular regions called channels and switchboxes. The
goal of a router is to complete all circuit connections using the shortest possible wire
length and using only the channels and switchboxes. This is usually done in two phases,
referred to as the global routing and detailed routing phases.
In global routing, connections are completed between the proper blocks of the
circuit disregarding the exact geometric details of each wire and pin. For each wire, the
global routerfinds a list of channels which are to be used as a passage way for that wire.
In other words, global routing specifies the ‘‘loose route’’ of a wire through different
regions in the routingspace. Global routing is followed by detailed routing, which
completes point-to-point connections between pins on the blocks. Loose routing is
converted into exact routing by specifying geometric information such as width of wires
and their layer assignments. Detailed routing includes channel routing and switchbox
routing.
As all problems in routing are computationally hard, the researchers have focused
on heuristic algorithms. As a result, experimental evaluation has become an integral part
of allalgorithms and several benchmarks have been standardized. Due to the nature of the

9
 routingalgorithms, complete routing of all the connections cannot be guaranteed in many
cases Compaction: The operation of layout area minimization without violating the
design rules and without altering the original functionality of layout is called as
compaction. The input of compaction is layout and output is also layout but by
minimizing area.
Compaction is done by three ways:
1. By reducing space between blocks without violating design space rule.
2. By reducing size of each block without violating design size rule.
3. By reducing shape of blocks without violating electrical characteristics of blocks.

1.5 VLSI DESIGN STYLES

Though the partitioning of a physical designed composes the physical design into several
conceptually easier steps, still each step is computationally very hard.
So, in order to reduce the complexity of physical design and to get high yield certain
restricted models and design styles are proposed.
They are
1. full-custom design style.
2. standard cell design style.
3. gate array design style.

1.6 SIMULATION
The objective behind any simulation tool is to create a computer based model for the
designverification and analyzing the behavior of circuits under construction also checking the
current level of abstraction.

1.7 TYPES OF SIMULATION

Device level simulation, Circuit level simulation, Timing level & Macro level simulation,
Switch level simulation, Gate level simulation, RTL simulation, System level simulation.

10
1.7.1 Device Level Simulation:
This model involves with a semiconductor device like a MOS transistor used to test
the effectof fabrication parameters. Simulator techniques based on finite-element method
are used forthis purpose.

1.7.2 Circuit Level Simulation:

It deals with small groups of transistors modeled in the analog domain .The
variables computed are currents and voltages and the computations are based on
numerical methods.

1.7.3 Switch Level Simulation:

This simulation method, models the MOS transistors as switches, that pass
signals .The values of signals are discrete, but it also includes certain analog features to
combine certaincomponents like resistance and capacitance.

1.7.4 Gate Level Simulation:

In this model a circuit is composed of several logic gates connected by uni-
directional memory less wires. The logic gates themselves are collections of transistors and
other circuit elements which perform a logic function. A logic gate may be a simple
inverter or NAND gate or NOR gate or more complex functional unit like a flip-flop or
register.

1.7.5 RTL Simulation:

This model is used synchronous circuits where all registers are controlled by a
system clocksignal. The registers store the state of the system, while the combinational
logic computes the next state and the output based on the current state and the input.
Here the important consideration is the state transitions and the precise timing of
intermediate signals in the computation of the next state is not considered.

1.7.6 System Level Simulation:

It deals with the hardware described in terms of primitives that need not
correspond with hardware building blocks. VHDL is the most popular hardware

11
 description language used for system level simulation. When used in the initial stages of
a design, it can describe the behavior of a circuit as a processor as a set of
communicating processes.

1.8 ADDERS
A digital logic circuit called Adder is used to implement binary number addition. An
essential part of an ALU (Arithmetic Logic Unit) is the Adder's circuit. This article gives a
thorough description of Adder, including its types, the design of its circuit, its operating
principle, applications, and benefits and drawbacks.
Binary numbers are added using the adder. A combinational logic circuit is essentially
what an adder circuit is. It is a memory-less circuit that executes the logical operation given to it
by a Boolean expression. The input at any given time determines the outputs.

1.9 ADDERS ARCHITECTURE

In electronics, an adder or summer is a digital circuit that performs addition of numbers.
In many computers and other kinds of processors, adders are used not only in the arithmetic
logic units, but also in other parts of the processor, where they are used to calculate addresses,
table indices, and similar operations.
Although adders can be constructed for many numerical representations, such as binary-
coded decimal or excess-3, the most common adders operate on binary numbers. In cases where
two’s complement or ones complement is being used to represent negative number.

1.10 TYPES OF ADDERS

1.10.1 Half Adder:

The half adder is an example of a simple, functional digital circuit built from
two logic gates. The half adder adds to one-bit binary numbers (AB). The output is the
sum of the two bits (S) and the carry (C). Note how the same two inputs are directed to
two different gates.

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 Fig 1.3: Schemetic diagram of Half adder

Table1.1 : Truth Table of Half Adder

1.10.2 Full Adder:

A full adder adds binary numbers and accounts for values carried in as well as
out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin;
AandB are the operands, and Cin is a bit carried in from the previous less significant
stage. The full adder is usually a component in a cascade of adders, which add 8, 16, 32,
etc. bit binary numbers. The circuit produces a two-bit output, output carry and sum.
Whereas the equation of the sum and carry is
S = A XOR B (1) Eq
Cout = A AND B (2) Eq

13
Fig 1.4: Schematic Diagram of Full Adder

Table 1.2: Truth table Of Full adder (1 Bit)

14
 CHAPTER 2
LITERATURE SURVEY

A full adder is a digital circuit that performs the arithmetic addition of three binary digits: two inputs, A
and B, and a carry input, Cin. In domino logic, the circuit is implemented using dynamic logic, where the
logic gates are connected to a dynamic node that operates as a charge-storage element. The dynamic node
is charged and discharged to perform logic operations.

BY REFERING THE ARTICLES

1."High-Performance Low-Power Domino Full-Adder Circuits" by P. Subbarami Reddy and K. V.

Srinivas, a new design for a domino full adder is presented.

The circuit uses a modified dynamic node to reduce the delay and power consumption. The
proposed circuit is simulated using a 0.18-μm CMOS technology and compared to other existing designs.
The results show that the proposed circuit achieves a 50% reduction in power consumption and a 25%
reduction in delay compared to previous designs.

2. "Design of a High-Speed Low-Power Dynamic Full-Adder Cell" by J. H. Yeh and C. H. Chang, a

new dynamic full adder cell is proposed.

The circuit is designed using a modified domino logic gate to achieve high-speed performance and
low power consumption. The proposed circuit is simulated using a 0.18-μm CMOS technology and
compared to other existing designs. The results show that the proposed circuit has a lower delay and
power consumption than previous designs.

3. "An Ultra-Low Power, Area Efficient Domino Full Adder" by M. T. Nasef and M. I. Elmasry, a
new domino full adder circuit is proposed.

The circuit is designed using a novel dynamic gate structure that reduces power consumption and
delay. The proposed circuit is simulated using a 0.18-μm CMOS technology and compared to other
existing designs. The results show that the proposed circuit has a 55% reduction in power consumption

15
and a 28% reduction in delay compared to previous designs.

4. "A Novel Energy-Efficient Domino Full Adder Cell for High-Speed Arithmetic Circuits" by S. B.
Akers and S. M. Kang, a new energy-efficient domino full adder cell is presented.

The circuit is designed using a modified dynamic logic gate structure to reduce power
consumption and delay. The proposed circuit is simulated using a 0.18-μm CMOS technology and
compared to other existing designs. The results show that the proposed circuit has a 65% reduction in
power consumption and a 30% reduction in delay compared to previous designs.

5. "A High Performance and Low Power 1-Bit Full Adder Cell Using Modified Domino Logic" by
R. Tudi and R. Sharma, a high-performance and low-power 1-bit full adder cell based on modified
domino logic is proposed.

The design uses an XOR-XNOR structure and a modified domino logic circuit to reduce power
consumption and improve performance. The circuit is simulated using 45nm CMOS technology, and the
results show that the proposed design achieves a 56% reduction in power consumption and a 55%
improvement in delay compared to conventional designs.

6."A Novel Low Power 1-Bit Full Adder Design using Domino Logic and Multiple Input Gates" by
N. Garg and R. Rani, a novel low-power 1-bit full adder design using domino logic and multiple
input gates is proposed.

The circuit uses a combination of domino logic and multiple input gates to reduce power
consumption and improve performance. The circuit is simulated using 45nm CMOS technology, and the
results show that the proposed design achieves a 44% reduction in power consumption and a 35%
improvement in delay compared to conventional designs.

7. "Low Power Full Adder Circuit Using Domino Logic" by P. Manjunatha and B. R. Ramesh, a
low-power full adder circuit using domino logic is proposed.

The circuit uses an XOR-XNOR structure and a domino logic circuit to reduce power consumption and

16
improve performance. The circuit is simulated using 45nm CMOS technology, and the results show that
the proposed design achieves a 42% reduction in power consumption and a 20% improvement in delay
compared to conventional designs.

8. "A Novel Energy-Efficient Full Adder Design using Modified Domino Logic" by M. V.
Muthukrishnan and S. S. Sathyalakshmi, a novel energy-efficient full adder design using modified
domino logic is proposed.

The circuit uses a modified domino logic circuit and a transmission gate to reduce power
consumption and improve performance. The circuit is simulated using 45nm CMOS technology, and the
results show that the proposed design achieves a 60% reduction in power consumption and a 45%
improvement in delay compared to conventional designs.

Overall, these studies demonstrate that full adders based on domino logic can achieve high-speed
performance and low power consumption. The proposed circuits in these studies use modified dynamic
gate structures to reduce delay and power consumption. These designs can be implemented using standard
CMOS technology and can be used in a wide range of digital circuits, including arithmetic circuits and
microprocessors .

17
 CHAPTER-3
BLOCK DIAGRAM AND WORKING PRINCIPLE

3.1 CMOS Logic:

CMOS Logic- CMOS is abbreviation of “Complement Metal Oxide Semiconductor”.

CMOS logic uses the P-MOS and N-MOS transistors as shown in Figure, and they work as a pull
up and a pull-down transistor respectively. When input will be low then P-MOS will be on and it will
charge the output node to VDD, and when input will be high N-MOS will turn on and charge stored at the
output node get a conducting path between output node and ground. CMOS logic design has various
numbers of advantages as compare to the others logics which were used before. In this both the transistors
are connected in complementary form i.e. if one transistor will be on, other will be off and vice versa. The
main advantages of the CMOS logic is that high noise margin, low power dissipation and the output are
pretty much rail-to-rail. There are also some disadvantages in CMOS logic like, it required large area and
speed of operation is slow. So for the circuit which uses large number of transistors it require very large
area and speed of operation becomes slow. That’s why there is a need to move on to another technology
which require smaller number of transistors and provide high speed of operation.

Figure.3.1 CMOS LOGIC

18
3.2 Types of CMOS logic gates

3.2.1 CMOS Inverter:

The CMOS inverter is formed by connecting the PMOS and NMOS transistors in cascade, as shown
below:

Figure:3.2 CMOS Inverter

The top of the CMOS inverter is the PMOS transistor, while the bottom transistor is NMOS. The positive
voltage of +VDD at the gate input of the NMOS transistors will turn it ON, while the same positive
voltage at the gate input of the PMOS transistor will keep it OFF. Similarly, the voltage of 0 volts at the
gate input of the NMOS transistors will keep it OFF, while the same 0 at the gate input of the PMOS
transistor will turn it ON.
It means that NMOS transmits logic 1 or VDD, and PMOS transmits logic 0.

Table: 3.1 Inverter Truth Table

19
3.2.2 CMOS NAND :
CMOS NAND is a combination of NMOS NAND and PMOS NOR. It consists of an NMOS NAND gate
with the PMOS NOR as its load. CMOS NAND gate can also include a PMOS NOR with the NMOS NAND as its
load. It means that NMOS and PMOS transistors' combination in the desired manner forms a CMOS logic gate.

Figure:3.3 NAND Gate using CMOS

The input terminal of the transistors is A and B, as shown above. If A = 0 and B = 0, the NMOS transistors will
remain off, and the two PMOS transistors will conduct.

Table:3.2 NAND Gate TruthTable

It clearly shows that the output is 1 when the two inputs are 0. Hence, PMOS NOR will conduct. The output Y will
be:

Y = logic 1 = VDD

Similarly, when both the input is 1, the NMOS NAND will conduct, and PMOS NOR will remain OFF.
But, the output will be 0 because the power will pass to the ground.

20
3.2.3 CMOS NOR :

Figure:3.4 CMOS NOR logic gate

When both the input A and B are 0, NMOS NOR will remain OFF, and PMOS NAND will conduct. It
means that transistors T1 and T2 will be OFF, while T3 and T4 will conduct. Thus, the output will be
logic 1 when the voltage VDD reaches through the conduction of transistors T3 and T4.

CMOS NOR will conduct only when both the inputs are 0 as discussed above. At all the other input
conditions, the output will be 0, as listed below:

Table: 3.3 NOR Gate Truth Table

21
3.3 Domino Logic:

Domino logic- Domino logic family find a wide variety of application, where less transistor count
and high speed of operation such as microprocessor, dynamic memory, digital signal processors etc are
required. Domino logic is an evolution in CMOS based dynamic logic techniques which use either p-MOS
or n-MOS for the pull down or pull up network. The methodology of designing full adder by using
Domino logic employes lesser no. of transistors as if compared to conventional CMOS logic and provides
high performance device.

The Domino logic is an improvement in dynamic logic which has a drawback when one gate is
cascaded to next. In domino logic. A static inverter is used between the two stages for removing the
drawback of dynamic logic. There are various advantages of Domino logic like they have a smaller area
unlike conventional CMOS logic, parasitic capacitance are smaller in domino logic so it provide high
speed of operation and result is glitch free because each gate makes only one transition. Domino logic
consists of two- stages of operation in which first stage is pre-charging, and another stage is evaluation. As
shown in Fig. when clock ‘CLK’ is equal to zero or low PMOS will be on and it pre-charged the output
node to VDD. When the CLK goes to high, p-MOS will be off and the evaluation phase will start. In this
phase output will depend on the input’s configuration. Output node may discharge if inputs have a direct
conducting path to ground otherwise it will remain high. So the output of circuit is obtained by which it
has been intended to design in evaluation phase only. In pre-charge phase, it will provide low output
because we used an inverter in this logic style for cascading the next stage.

Figure: 3.5 DOMINO LOGI

22
3.4 CMOS Full Adder:

Designing of one- bit full adder based on CMOS logic- The one- bit full adder schematic
using CMOS logic is shown in Figure. This circuit uses the 14 p-MOS transistors which are used
for charging the output capacitance and 14 n-MOS transistors for discharging the output node
according to value of inputs.

Figure: 3.6 Schematic structure of one-bit full adder which uses the CMOS logic.

23
 So there is total 28 number of transistors used in designing of one- bit full adder which uses
the CMOS logic style. It is very difficult and complex to design one- bit full adder as it consists
large number of transistors. As we can see in the Figure there are large number of wires used for
providing the connection between the transistors which introduce large delay in the circuit.

24
3.5 Domino Logic Full Adder:
VDD

Figure:3.7 Schematic design of one- bit full adder which uses the Domino logic

Design of one- bit full adder using Domino logic- The one-bit full adder schematic using
Domino logic is shown in Fig. 6. For designing the one-bit full adder by using domino logic we
use the p-MOS transistors for the pre-charge phase and inverter, rest we used the n-MOS
transistors for evaluation phase.

In this logic style we have used 4 P-MOS transistors and 16 N-MOS transistors. So there
are a total 20 transistors being used in designing the adder circuit by using Domino logic.

25
 CHAPTER 4
INTRODUCTION TO TANNER TOOL

4.1 WHAT IS TANNER TOOL

Tanner tool is a Spice Computer Analysis Programmed for Analogue Integrated Circuits.
Tanner tool consists of the following Engine Machines:
1. S-EDIT (Schematic Edit)

2. T-EDIT (Simulation Edit)

3. W-EDIT (Waveforms Edit)

4. L-EDIT (Layout Edit)

Using these engine tools, spice program provides facility to the use to design & simulate
new ideas in Analogue Integrated Circuits before going to the time consuming & costly process
of chip fabrication.

4.2 SCHEMATIC EDIT TOOL (S-EDIT)

S-Edit is hierarchy of files, modules & pages. It introduces symbol & schematic modes.
S-Edit provides the facility of:

1. Beginning a design.
2. Viewing, drawing & editing of objects.
3. Design connectivity.
4. Properties, net lists & simulation.
5. Instance & browse schematic & symbol mode.

4.2.1 Beginning a Design:

It explains the design process in detail in terms of file module operation and
module.

4.2.2 Browser:
Effective schematic design requires a working knowledge of the S-Edit design
hierarchy of files & modules. S-Edit design files consist of modules. A module is a

26
 functional unit of design such as a transistor, a gate and an amplifier.
Modules contain two components:

(1).Primitives: Geometrical objects created with drawing tools.

(2).Instances: References to other modules in file. The instanced module is the

original.

S-Edit has two viewing modes:

(1).Schematic Mode: to create or view a schematic, we operate in schematic mode.

(2).Symbol Mode: it represents symbol of a larger functional unit such as operational

amplifier.

4.3 T-SPICE PRO CIRCUIT ANALYSIS

An introduction to the integrated components of the T- Spice Pro circuit analysis suite:

4.3.1 Schematic Data Files (.sdb):

Describes the circuits to be analyzed in graphical form, for display and editing by
S- Edit" Schematic Editor.

4.3.2 Simulation Input Files (.sp / .spc):

Describes the circuits to be analyzed in textual form, for editing and simulation
by T- Spice" Circuit Simulator.

4.3.3 Simulation Output Files (.out):

Containing the numerical results of the circuit analyses, for manipulation and
display by W- Edit" Waveform Viewer.

4.4 CIRCUIT SIMULATOR (T-SPICE):

T- Spice Pro’s waveform probing feature integrates S- Edit, T- Spice, and W- Edit to
allow individual points in a circuit to be specified and analyzed. A few analysis is described
below:
The heart of T-Spice operation is the input file (also known as the circuit description, the

27
net list & the input deck). This is a plain text file that contains the device statement & simulation
commands, drawn from the SPICE circuit description language with which T-Spice constructs a
model of the circuit to be simulated. Input files can be created and modified with any text editor.
T-Spice is a tool used for simulation of the circuit. It provides the facility of
1. Design Simulation
2. Simulation Commands
3. Device Statements
4. User-Designed External Models
5. Small Signal & Noise Models

T-Spice uses Kirchhoff’s Current Law (KCL) to solve circuit problems. To T-Spice, a
circuit is a set of devices attached to nodes. The voltage at all nodes represents the circuit state.
T-Spice solves for a set of node voltage that satisfied KCL (implying that sum of currents
flowing into each node is zero). In order to evaluate whether a set of node voltages is a solution,
T-Spice computers and sums all the current flowing out of each device into nodes connected to it
(its terminals). The relationship between the voltages at device terminals and the currents
through the terminal is determined by the device model for a resistor of resistance R is

I=∆V/R

Where, ∆V represents the voltage difference across the device. A few analyses are
discussed below:

4.4.1 DC Operating Point Analysis

DC operating point analysis finds a circuit’s steady- state condition, obtained (in
principle) after the input voltages have been applied for an infinite amount of time. The
.include command causes T- Spice to read in the contents of the model file for the
evaluation of NMOS and PMOS transistors.
The technology file assigns values to MOSFET model parameters for both n - and
p -type devices. When read by the input file, these parameters are used to evaluate
MOSFET model equations, and the results are used to construct internal tables of current
and charge values. Values read or interpolated from these tables are used in the
computations called for by the simulation. Following each transistor name are the names

28
of its terminals. The required order of terminal names is: drain -gate -source -bulk. Then
the model name (NMOS or PMOS in this example), and physical characteristics such as
length and width, are specified. The .op command performs a DC operating point
calculation and writes the results to the file specified in the Simulate > Start Simulation
dialog. The output file lists the DC operating point information for the circuit described
by the input file.

4.4.2 DC Transfer Analysis

DC transfer analysis is used to study the voltage or current at one set of points in
a circuit as a function of the voltage or current at another set of points. This is done by
sweeping the source variables over specified ranges, and recording the output. A list of
sources to be swept, and the voltage ranges across which the sweeps are to take place
follow the .dc command, indicating transfer analysis. The transfer analysis will be
performed as follows: vdd will be set at 5 volts and vin will be swept over its specified
range; vdd will then be incremented and vin will be reswept over its range; and so on,
until vdd reaches the upper limit of its range. The .dc command ignores the values
assigned to the voltage sources vdd and vin in the voltage source statements, but they
must still be declared in those statements. The results for nodes in and out are reported by
the .print dc command to the specified destination.

4.4.3 Transient Analysis

Transient analysis provides information on how circuit elements vary with time.
The basic T- Spice command for transient analysis has three modes. In the default mode,
the DC operating point is computed, and T- Spice uses this as the starting point for the
transient simulation. The .tran command specifies the characteristics of the transient
analysis to be performed.

4.4.4 AC Analysis
AC analysis characterizes the circuit’s behavior dependence on small- signal
input frequency. It involves three steps: (1) calculating the DC operating point; (2)
linearizing the circuit; and (3) solving the linearized circuit for each frequency. When ac
voltage source is to be applied, then vdiff sets the DC voltage difference between nodes

29
 the two nodes to -0. 0007 volts; its AC magnitude is 1 volt and its AC phase is 180
degrees. The .ac command performs an AC analysis. Following the .ac keyword is
information concerning the frequencies to be swept during the analysis. In case, the
frequency is to be swept logarithmically, by decades (DEC); 5 data points are to be
included per decade is considered to be the standard The two .print commands write the
voltage magnitude (in decibels) and phase (in degrees), respectively, for the node out to
the specified file. The .acmodel command writes the small- signal model parameters and
operating point voltages and currents for all circuit devices

4.4.5 Noise Analysis

Real circuits, of course, are never immune from small, random fluctuations in
voltage and current levels. In T- Spice, the influence of noise in a circuit can be
simulated and reported in conjunction with AC analysis. The purpose of noise analysis is
to compute the effect of the noise associated with various circuit devices on an output
voltage or voltages as a function of frequency. Noise analysis is performed in
conjunction with AC analysis; if the .ac command is missing, then the .noise command is
ignored. With the .ac command present, the .noise command causes noise analysis to be
performed at the same frequencies. The .noise command takes two arguments: the output
at which the effects of noise are to be computed, and the input at which the .noise can be
considered to be concentrated for the purposes of estimating the equivalent noise spectral
density. The print command is used to print results.

4.5 WAVEFORM EDIT

The ability to visualize the complex numerical data resulting from VLSI circuit
simulation is critical to testing, understanding & improving these circuits. W-Edit is a waveform
viewer that provides ease of use, power & speed in a flexible environment designed for
graphical data representation. The advantages of W-Edit include:
(1). Tight Integration with T-spice, Tanner EDA_s circuit level simulator. W-Edit can
chart data generated by T-spice directly, without modification of the output text
data files. The data can also be charted dynamically as it is produced during the
simulation.

30
 (2). Charts can automatically configure for the type of data being presented.

(3). A data is treated by W-Edit as a unit called a trace. Multiple traces from different
output files can be viewed simultaneously in single or several windows; traces can
be copied and moved between charts & windows. Trace arithmetic can be
performed on existed tracing to create new ones.

(4). Chart views can be panned back & forth and zoomed in & out, including specifying
the exact X-Y co-ordinate range.

(5). Properties of axes, traces, rides, charts, text & colors can be customized.

Numerical data is input to W-Edit in the form of plain or binary text files. Header &
Comment information supplied by T-Spice is used for automatic chart configuration. Runtime
update of results is made possible by linking W-Edit to a running simulation in T-Spice. W-Edit
saves data with chart, trace, axis & environment settings in files with the WDB (W-Edit
Database).

4.6 LAYOUT(L-EDIT)
It is a tool that represents the masks that are used to fabricate an integrated circuit. It
describes a layout design in terms of files, cells & mask primitives. On the layout level, the
component parameters are totally different from schematic level. So it provides the facility to the
user to analyze the response of the circuit before forwarding it to the time consuming & costly
process of fabrication. There are rules for designing layout diagram of a schematic circuit using
which user can compare the output response with the expected one.

4.6.1 L- Edit: An Integrated Circuit Layout Tool

In L- Edit, layers are associated with masks used in the fabrication process.
Different layers can be conveniently represented by different colors and patterns. L- Edit
describes a layout design in terms of files, cells, instances, and mask primitives. You
may load as many files as desired into memory. A file may be composed of any number
of cells. A file may be composed of any number of cells. These cells may be
hierarchically related, as in a typical design, or they may be independent, as in a library
file. Cells may contain any number or combination of mask primitives and instances of

31
other cells.

4.6.2 Cells: The Basic Building Blocks

The basic building block of the integrated circuit design in L- Edit is a cell.
Design layout occurs within cells. A cell can:
(1). Contain part or all of the entire design.
(2). Be referenced in other cells as a sub- cell, or instance.
(3). Be made up entirely of instances of other cells.
(4). Contain original drawn objects, or primitives.
(5). Be made up entirely of primitives or a combination of primitives and
instances of other cells.

4.6.3 Hierarchy
L- Edit supports fully hierarchical mask design. Cells may contain instances of
other cells. An instance is a reference to a cell; should you edit the instanced cell, the
change is reflected in all the instances of that cell. Instances simplify the process of
updating a design, and also reduce data storage requirements, because an instance does
not need to store all the data within the instanced cell instead, only a reference to the
instanced cell is stored, along with information on the position of the instance and on
how the instance may be rotated and mirrored.
L- Edit does not use a “separated” hierarchy: instances and primitives may
coexist in the same cell at any level in the hierarchy. Design files are self- contained. The
pointer to a cell contained in an instance always points to a cell within the same design
file. When cells are copied from one file to another, L- Edit automatically copies across
any cells that are instanced by the copied cell, to maintain the self- contained nature of
the destination file.
Manufacturing constraints can be defined in L- Edit as design rules. Layouts can
be checked against these design rules.

4.6.4 Design Features

L- Edit is a full- custom mask editor. Manual layout can be accomplished more
quickly because of L Edit’s intuitive user interface. In addition, one can construct special

32
structures to utilize a technology without, worrying about problems caused by automatic
transformations. Phototransistors, guard bars, vertical and horizontal bipolar transistors,
static structures, and Schottky diodes, for example, are as easy to design in CMOS- Bulk
technology as are conventional MOS transistors.

4.6.5 Floor Plans

L- Edit is a manual floor planning tool. You have the choice of displaying
instances in outline, identified only by name, or as fully fleshed- out mask geometry.
When you display your design in outline, you can manipulate the arrangement of the
cells in your design quickly and easily to achieve the desired floor plan. One can
manipulate instances at any level in the hierarchy, with insides hidden or displayed, using
the same graphical move/ select operations or rotation/ mirror commands that you use on
primitive mask geometry.

4.6.6 Memory Limits

In L- Edit, one can make your design files as large as one like, given available
RAM and disk space.

4.6.7 Hard Copy

L- Edit provides the capability to print hard copy of the design. A multiage option
allows very large plots to be printed to a specific scale on multiple 8 1/ 2 x 11 inch pages.
An L- Edit macro is available to support large- format, high- resolution, color plotting on
inkjet plotters.

4.6.8 Variable Grid

L- Edit’s grid options support lambda- based design as well as micron- based and
mil- based design.

4.6.9 Error Recovery

L- Edit’s error- trapping mechanism catches system errors and in most cases
provides a means to recover without losing or damaging data.

33
4.6.10 L- Edit Modules
(1).L- Edit TM: a layout editor
TM
(2).L- Edit ¤ Extract : a layout extractor
(3).L- Edit ¤ DRC TM: a design rule checker
L- Edit is a full- featured, high-performance, interactive, graphical mask layout
editor. L- Edit generates layouts quickly and easily, supports fully hierarchical designs,
and allows an unlimited number of layers, cells, and levels of hierarchy. It includes all
major drawing primitives and supports 90°, 45°, and all- angle drawing modes.

4.6.11 L- Edit ¤ Extract Creates SPICE

Compatible circuit netlists from L- Edit layouts. It can recognize active and
passive devices, sub circuits, and the most common device parameters, including
resistance, capacitance, device length, width, and area, and device source and drain area.

4.6.12 L- Edit ¤ DRC Features User

Programmable rules and handles minimum width, exact width, minimum space,
minimum surround, non- exist, overlap, and extension rules. It can handle full chip and
region- only DRC. DRC offers Error Browser and Object Browser functions for quickly
and easily cycling through rule- checking error.

34
 CHAPTER 5
RESULTS AND ANALYSIS

5.1 DESIGN UNIT:

5.1.1 CMOS inverter:

Figure:5.1 CMOS Inverter Design

Figure:5.2 Results of CMOS Inverter

35
5.1.2 CMOS Full Adder:

Figure:5.3 CMOS Full Adder Design

Figure:5.4 Results of CMOS Full Adder

36
5.1.3 Domino Logic Full Adder:

Figure:5.5 Domino Full Adder Design

Figure:5.6 Results of Domino Full Adder

37
 CHAPTER 6
ADVANTAGES AND APPLICATIONS

6.1 Advantages

1. Reduces time delay.

2. Has low energy and power consumption.
3. Smaller area can be achieved.
4. Addition can be made faster.

6.2 Applications

1. A Full Adder’s circuit can be used as a part of many other larger circuits like Ripple Carry
Adder which adds n-bits simultaneously.
2. The dedicated multiplication circuit uses Full Adder’s circuit to perform Carryout
Multiplications.
3. Full Adders are used in ALU - arithematic logic unit.
4. In order to memory address inside a computer and to make the program counter point to next
instruction, the ALU makes the use of Full Adder.
5. Full Adders are a part of Graphics Processing unit for graphic related applications.

38
 CHAPTER 7
CONCLUSION AND FUTURE SCOPE

7.1 Conclusion

In this project designing of full adder circuit using the CMOS logic and Domino logic has been
done. We used Tanner EDA software, 180nm technology for analyzing the full adder circuit. It was
found that Domino logic gives us very accurate results with less number of transistors and minimum
delay as compare to the CMOS design logic. There are almost no glitches in Domino logic transient
analysis. Further there is a decrease in chip area by 28.5% and delay by 47.37% in Domino logic as
compared to CMOS logic. Further, as shown in the power graph of CMOS logic and Domino logic it
was observe that instantaneous power is more in CMOS based logic as compare to the Domino logic so
there are more chances of device failure in CMOS logic as compare to the Domino logic.
7.2 Future scope

To extend this concept we may change the different configurations of Full Adders using PTL,
Transmission gate , GDI by applying Domino logic.

39
 REFERENCE

[1] Gaetano Palumbo, Melita Pennisi, Massimo Alioto, “A simple approach to reduce delay variation in Domino
logic Gates”, IEEE transaction on Circuits and System, Vol. 59, pp. 10-14, October 2012.

[2] Thorp, K. Himabindu and K. Hariharan, "Design of area and power efficient full adder in 180nm," 2017
International Conference on Networks & Advances in Computational Technologies (NetACT), Thiruvanthapuram, ,
pp. 336-340, 2017.

[3] Thakur, R., Dadoria, A. K., & Gupta, T. K, “Comparative analysis of various Domino logic circuits for better
performance”, International Conference on Advancesin Electronics, Computers and Communications (ICAECC),
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[4] K. Bernstein, J. Ellis-Monaghan, E. Nowak, "High-Speed Design Styles Leverage IBM Technology Prowess",
IBM Micro News, vol. 4, no. 3, 1998.

[5] F. Frustaci M. Lanuzza P. Zicari S. Perri and P. Corsonello, "Low-power split-path data-driven dynamic logic,"
IET Circuits Devices Syst., Vol. 3, Iss. 6, pp. 303-312, 2009.

[6] V. Kursun, and E. G. Friedman, "Low swing dual threshold voltage domino logic," in Proc. ACM/SIGDA Great
Lakes Symp. VLSI, pp. 47- 52, 2018.

[7] Zhiyu Liu, Volkan Kursun, "PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm
CMOSTechnologies", IEEE Trans. Very Large-Scale Integration (VLSI) Systems,vol. 15, no. 12, DEC. 2007.

[8] Zhiyu Liu, Volkan Kursun, "Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS
Technologies", IEEE Trans. Circuits and Systems-II, vol. 53, no. 8, 2006.

[9] Sharroush, S. M., Abdalla, Y. S., Dessouki, A. A. El-Badawy, E. S. A., “A novel low-power and high-speed
dynamic CMOS logic circuit technique” IEEE confrenceIn Radio Science Conference, National pp. 1-8, 2009.

[10] L. Ding and P. Mazumder, "On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic
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[11] Karuppusamy, P. " Design and Analysis Of Low-Power, HighSpeed Baugh Wooley Multi-Plier" Journal of
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[12] Kamlesh Kukreti, Rais Ahmad, Anzar Ahmad, “Design and Implementation A Low Power Rail-To-Rail
Preamplifier”, Universal Review ,2018.s

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