Digital VLSI Design

Lecture 9:
Routing
Semester B, 2021-22
Lecturer: Zvika Webb

2nd May 2022

Disclaimer: This course was prepared, in its entirety, by Adam Teman and Zvi Webb. Many materials were copied from sources freely available on the internet. When possible, these sources
have been cited; however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be
cited or removed, please feel free to email webb@tauex.tau.ac.il and I will address this as soon as possible.
 Routing: The Problem
• Scale
• Millions of wires
• MUST connect them all
• Geometric Complexity
• Basic starting point – grid representation.
• But at nanoscale – Geometry rules are complex!
• Also, many routing layers with different “costs”.
• Electrical Complexity
• It’s not enough to just connect all the wires.
• You also have to:
• Ensure that the delays through the wires are small.
• Ensure that wire-to-wire interactions (crosstalk)
doesn’t mess up behavior.
2
 Problem Definition
• Problem:
• Given a placement, and a fixed number of metal layers, find a valid pattern
of horizontal and vertical wires that connect the terminals of the nets.
• Input: • Objective
• Cell locations, netlist • 100% connectivity of a system
• Minimum area, wirelength
• Output:
• Geometric layout of each net • Constraints
connecting various standard cells • Number of routing layers
• Design rules
• Two-step process • Timing (delay)
• Global routing • Crosstalk
• Detailed routing • Process variations
3
 Lecture Contents

• Routing Algorithms
• Routing in practice

4
 2 2
1
Routing Routing in
Intro
Algorithms Practice

Routing Algorithms

This section is heavily based on Rob Rutenbar’s “From Logic to Layout”,

Lecture 11 from 2013. For a better  and more detailed explanation, do
yourself a favor and go see the original!
5
Grid Assumption
• Despite the complexity of nanoscaled routing, we will use a grid assumption
and add the complexity in later.
• Layout is a grid of regular squares Target
• A legal wire is a set of connected grid T
cells through unobstructed cells.
• Obstacles (or blockages) are marked
in the grid. Obstacle
• Wires are strictly horizontal and vertical
(Manhattan Routing) S
• Paths go
Source
• North/South
• East/West.
 Maze Routers
• Also known as “Lee Routers”
• C. Y. Lee, “An algorithm for path connections and its applications” 1961

• Strategy:
• Route one net at a time.
• Find the best wiring path for the current net.
• Problems:
• Early wired nets may block path of later nets.
• Optimal choice for one net may block others.
• Basic Idea:
• Expand  Backtrace  Cleanup
7
 Maze Routing: Expansion
• Start at the source. 3 2 3 4 5 6
• Find all paths 1 cell away.
• Continue until reaching the target. 2 S1 2 3 4 5
• We approach the target with a
“wavefront” 3 2 3 4 5 6
• We found that the shortest path to
the target is 6 unit steps. 4 3 4 5 6

5 4 5 T
6

6 5 6

8
 Maze Routing: Backtrace & Cleanup
• Backtrace: 3 2 3 4 5 6
• Follow the path lengths backwards in
descending order.
• This will mark a shortest-path to the target.
2 S1 2 3 4 5

• However, there may be many shortest 3 2 3 4 5 6

paths, so optimization can be used to
select the best one.
4 3 4 5 6
• Cleanup
• We have now routed the first net.
• To ensure that future nets do not try to use
5 4 5 T
6

the same resources, mark the net path 6 5 6

from S to T as an obstacle.
9
 Maze Routing: Blockages
• How do we deal with blockages?
• Easy. Just “go around” them!
4 5 T6
3
To summarize:
• Expand: 2 S1 2
• Breadth-first-search (BFS) to find all
paths from S to T in path-length order. 3 2 3
• Backtrace:
• Walk shortest path back to source. 4 3 4
• Cleanup:
5 4 5 6
• Mark net as obstacle
and erase distance markers.
10
 Multi-Point Nets
• How do we go about routing a net with 4 3 4
multiple targets?
• Actually, pretty straightforward.
• Start with our regular maze routing
3 2 3 TS4
algorithm to find the path to the nearest
target.
2 S1 S2 S3 4

• Then re-label all cells on found path as

3 2 3 4
sources, and re-run maze router using all
sources simultaneously.
4 3 4

4 T
11
 Multi-Point Nets
• How do we go about routing a net with 4 3 3 2 3
multiple targets?
• Actually, pretty straightforward.
• Start with our regular maze routing
3 2 2 S1 2 3

algorithm to find the path to the nearest

target.
2 S1 S1 S1 2 3

• Then re-label all cells on found path as

3 2 2 2 3 4
sources, and re-run maze router using all
sources simultaneously.
4 3 3 3 4 5
• Repeat until reaching all target points.
Note that this does not guarantee the
shortest path (=“Steiner Tree”)
5 4 4 4 T5
12
 Multi-Layer Routing
• Okay, so what about dealing with several routing layers?
• Same basic idea of grid – one grid for each layer.
• Each grid box can contain one via.
• New expansion direction – up/down.

13
 Multi-Layer Routing
3 2 3 4 5 6

2 S1 2 3 4 5 8

3 2 3 5 6 8 7 6 7 8

4 3 V
4 6 7 7 6 V
5 6 7 8

5 4 5 7 V
8 8 7 6 7 T8 V
6 5 6 7 8 8 7 8

14
Metal 1 Metal 2
 Non-Uniform Grid Costs
• But we know that vias have (relatively) high resistance.
• Shouldn’t we prefer to stay on the same metal layer?
• We also prefer Manhattan Routing
• Each layer is only routed in one direction.
• A “turn” requires going through a via or a “jog” should be penalized.
• Is there a way to prefer routing in a certain layer/direction?

• Yes.
• Let’s introduce non-uniform grid costs.

15
 Multi-Layer Routing
Cost of Via = 10

11 12 13 14 15 16

S1 2 V
3 4 5 6 23 V
13

15 16 24 14

T
26 V
25 26 25 26 25 V
15

35 35 26 16
Cost of wrong
way route = 10 Vertical 27 17 27

16
Horizontal Metal 1 Metal 2
 How do we implement this?
• Grids are huge.
• Assume 1cm X 1cm chip. All of this is hard!
• Assume 100 nm track
• Assume 10 routing layers
• That is 1010 (100 billion) grid cells!
• We need a low cost representation Use many different heuristics:
• Only store the wavefront. • Which net to route first
• Remember which cells have been reached, • Bias towards the right
at what cost, and from which direction. direction
• How to go about fixing
• Use Dijkstra’s algorithm to find the
problems
cheapest cell first.
• Etc., etc., etc.
• Store data in a heap.
17
 Divide and Conquer: Global Routing
• To deal with a big chip, we make our problem smaller
• Divide the chip into big, course regions
• e.g., 200 X 200 tracks each.
• These are called GBOXes.
• Now Maze Route through the GBOXes

18
 Divide and Conquer: Global Routing
• Global routing takes care of basic congestion.
• Balances supply vs. demand of routing resources.
• Generates regions of confinement for the wires.
• Detailed routing decides on the exact path.

GBOXes have a
dynamic cost
according to how
congested they are!

19
 2 2
1
Routing Routing in
Intro
Algorithms Practice

Routing in practice

20
 Layer Stacks
• Metal stacks are changing W2

(and growing)
U2 W1 Intel 45nm 8 metal stack
Representative layer stacks for
130 nm - 32 nm technology
U1
nodes E2

E2 E1 E1
B3
E1 B3
B2
B2 B3 B1 B2
M6 B1 B2 C2 B1
UMC 6 metal stack
M5 M5 B1 C1 M5
M4 M4 M4 M4 M4
M3 M3 M3 M3 M3
M2 M2 M2 M2 M2
M1 M1 M1 M1 M1
130 nm 90 nm 65 nm 45 nm 32 nm
21
 Pre-Routing Checks and Setup
CTS + Check for routing readiness
Clock routing
Control secondary P/G pin routing

Pre-routing Enable redundant via insertion

checks and setup
Increase wire/via optimization level

Routing Enable antenna fixing (layer jumping)

Apply route guide/blockage, if needed

Optimization
and Reroute Control the scope for rerouting
Routing
Enable crosstalk analysis and prevention

Enable via ladder insertion

Signoff
22
 Check for Routing “Readiness”
• Run checks to ensure that you are ready for routing:

icc2_shell> check_design -checks pre_route_stage

Running mega-check 'pre_route_stage':
Running atomic-check 'design_mismatch'
Running atomic-check 'scan_chain'
Running atomic-check 'mv_design'
Running atomic-check 'design_extraction'
Running atomic-check 'timing'
Running atomic-check 'routability‘
…
Info: EMS database is saved to file 'check_design.ems'.
Info: Non-EMS messages are saved to file 'check_design2015Jul07025739.log'.

• Open a Message Browser Window to analyze the violations in the EMS database

23
 Global Route
• Divide floorplan into GCells
• Approximately 10 tracks
per layer each.
Vertical routing

• Perform fast grid routing: capacity = 9

tracks

• Minimize wire-length Y

• Balance Congestion
Horizontal routing
• Timing-driven capacity = 9
tracks
• Noise/SI-driven
• Keep buses together X

• Also used for trial route

• During earlier stages of the flow X
Y

24
 Route Operations: Global Route (GR)
• GR assigns nets to specific metal layers (in the preferred routing
direction) and through specific global routing cells (GRC or Gcells)
• No metal traces are created
• Uses colored zero-width lines to indicate global routes and
assigned metal layers
• GR tries to avoid congested Gcells while minimizing detours:
Global Route
• Congestion exists when more tracks
are needed than available
• Detours increase wire length (delay)
• GR also avoids:
• P/G (rings/straps/rails)
GRC
• Routing blockages Congested area

25
Route Operations: Global Route Summary

• Global routing does not create

metal shapes
• You can select and interact with
global routing in the GUI

Global
route
Preroute

26
Route Operations: Track Assignment

• Track Assignment (TA): Jog reduces

• Assigns each net to a specific track via count

within each global routing cell and

creates the actual metal shapes
• Attempts to:
• Make long, straight traces
• Reduce the number of vias TA metal
shapes
traces
• After Track Assign, there should be no
global routes or GR vias left Preroute

After TA finishes, all nets are routed, but not very carefully. There are many violations, particularly
where the routing connects to pins. Detail routing works to correct those violations.

27
 Congestion map

Congestion Map
• Use congestion map and report to
examine design routability

Congestion Report
#               Routing  #Avail      #Track     #Total     %Gcell
#  Layer      Direction   Track     Blocked      Gcell Blocked
#  ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
#  Metal 1        H        7607        9692     1336335    62.57%
#  Metal 2        H        7507        9792     1336335    55.84%
#  Metal 3        V        7636        9663     1336335    59.51%
#  Metal 4        H        8609        8691     1336335    52.02%
#  Metal 5        V        5747       11551     1336335    56.39%
#  Metal 6        H        5400       11899     1336335    55.09%
#  Metal 7        V        1831        2486     1336335    55.30%
#  Metal 8        H        2415        1903     1336335    43.85%
#  ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
#  Total                  46753      56.99%    10690680    55.07%
#
#  589 nets (0.47%) with 1 preferred extra spacing. 
28
 Detailed Route Detailed Route Boxes Solve
shorts
• Using global route plan,
within each global route cell
Notch
• Assign nets to tracks Spacing
• Lay down wires
• Connect pins to nets Notch
• Solve DRC violations Spacing
• Reduce cross couple cap
• Apply special routing rules
Thin&Fat
• Flow: Spacing

• Track Assignment (TA) Min

• DRC fixing inside a Global Routing Cell (GRC) Spacing

• Iterate to achieve a solution (default ~20 iterations)

29
 Timing-Driven Routing
• Optimize critical paths
• Route some nets first
• Most routing freedom at start
• Use shortest paths possible
• Net weights
• Order of routing (priorities: e.g., Default : Clocks 50, others 2)
• Wire widening
• Reduce resistance
• If you have a congested design you may need to set the timing
driven effort to “low”
• Beware when changing default options
30
 Signal Integrity (SI)
• Signal Integrity during routing is synonymous with Crosstalk.
• A switching signal may affect a neighboring net.
• The switching net is called the Aggressor.
• The affected net is called the Victim.
• Two major effects:
net 1 Aggressor
• Signal slow down
• When the aggressor and victim
switch in opposite directions. net 2 Victim
• Signal speed up
• When the aggressor and victim
switch in the same direction.
Speed Up Delay

31
 SI Multi-Aggressor Timing Analysis
Aggressor
net X
• Infinite Window Analysis Net X
aggressor
Victim
• An infinite noise window Net Y Net B net C

applies the maximum delay aggressor Aggressor

due to crosstalk during timing analysis. net Y

• This model was sufficient for older (pre-90nm)

technologies, but became too severe with the Noise bumps on net C

growing sidewall capacitances at scaled nodes. Crosstalk

noise from
X
• Propagated Noise Analysis Crosstalk
noise from Y
• Min/Max vectors are propagated through the design to
Propagated
create a transition window for all aggressors in relation noise from B
to a certain victim. Worst-case
• Noise is only applied at the overlap of the two combination of noise
bumps on net C
windows to determine the worst case noise bump.
32
 Signal Integrity - Solutions
• Crosstalk Prevention Increasing
wire
• Limit length of parallel nets Upsizing spacing Adding shielding
victim
• Wire spreading driver Inserting buffer
• Shield special nets
Critical Nets
• Upsize driver or buffer
Grounded shields
Extra space

Shielding
Same layer (H)
Spacing Wire Spreading Adjacent layers (V)
33 Net Ordering
 Design For Manufacturing
• During route, apply additional
design for manufacturing (DFM)
and/or design for yield (DFY) rules:
• Via reduction
• Redundant via insertion
Wire straightening (reduce jogs)
• Wire straightening
• Wire spreading

Avoid
asymmetrical
contacts
34
 Via Optimization
• Post-Route Via Optimization, includes:
• Incremental routing for the minimization of vias.
• Replacement of single vias with multi-cut vias.
• These operations are required for:
• Reliability:
• The ability to create reliable vias decreases with each process
node. If a single via fails, it creates an open and the circuit is extra vias
useless. added
• Electromigration:
• Electromigration hazards are even more significant in vias,
which are essentially long, narrow conductors.

35
 Wire Spreading • High-density
critical area
• High probability of
yield-killing defect
• Wire spreading achieves:
• Lower capacitance and better signal integrity.
• Lower susceptibility to shorts or opens due to
random particle defects.
• Density reduced,
yield risk reduced
• No timing impact!
Center of conductive defects within Center of non-conductive defects within
critical area – causing shorts critical area – causing opens
Metal 3
+ +
+ + + +
+ +
Center of conductive defects Critical Areas Center of non-conductive defects
outside critical area – no shorts outside critical area – no opens

36
Reduce Short/Open Critical Area

spread_wires \
-timing_preserve_setup_slack_threshold 0.1 \
-timing_preserve_hold_slack_threshold 0.1
widen_wires \
-timing_preserve_setup_slack_threshold 0.1 \
-timing_preserve_hold_slack_threshold 0.1

Wire Tracks Spreading off-track

by ½ pitch

Widening up to
37 1.5x default width
 Via Ladders or Via Pillars
M5 – actual route
• At finer pitches:
• Resistance: Increases due to thinner width/height
and electron scattering effects
• Regularity: Process becomes highly regular M3 M4
and shapes become one-dimensional
(no jogs, RVI, etc.) M2
• Standard cell design: Pin design for colored Pin
rules becomes more complicated Standard Cell
• A via ladder is a stack of vias starting from the pin
layer, dynamically created by the router with the
purpose of:
• Increasing EM robustness
• Reducing via resistance for critical nets
38
 Multiple Purposes and Types of Via Ladders
• Via Ladders can be of various flavors, primarily for EM and performance
• Each category may have various configurations and possibilities
• e.g. Aggressive and route intensive versus less aggressive and route friendly

39
Performance Via Ladder EM Via Ladder Pattern Must Join Via Ladder
 No via ladder
Net delay Transition Slack
11.3 ps 20.2 ps -0.134

VL type 1
Net delay Transition Slack
7.8 ps 15.6 ps -0.129

VL type 1
VL type 2
Net delay Transition Slack
6.2 ps 14.0 ps -0.126

VL type 2

40
 How Are Via Ladders (VLs) Defined?

The form of the VL is described in A list of VL candidates is provided for

the techfile (using viaRule) or library cell pins
using Tcl (create_via_rule) (Tcl: set_via_ladder_candidate)

A purpose is set on each VL:

• Electro Migration
Required files are provided
• Performance
by the library vendor
41
 Antenna Violations
• As the total area of a wire increases during processing, the voltage
stressing the gate oxide increases
• Antenna rules define acceptable total areas of wires
Oscillating + + + + + + + + + +
charges in
plasma etchant Protective coating
- - Metal 3 - -

- Metal 2 -
Oxide - Metal 1 -
- Poly -

Substrate
Damaged gate oxide

Antenna Ratios:

gate Area of Metal Connected to Gate

Combined Area of Gate
Or
poly Area of Metal Connected to Gate
diffusion Combined Perimeter of Gate

42
 Fixing Antenna Violation by Layer Jumping
Before layer jumping

metal 3 M3 blockage

M1 gate
blockage metal 1
poly
Unacceptable antenna area
driver
diffusion

M1 is split by
jumping to
After layer jumping, to meet Antenna rules M3 and back

metal 3 M3 blockage metal 3

M1 gate
blockage metal 1
poly

driver
Acceptable antenna area
diffusion
43
 Double Patterning
Design

Mask 1 Mask 2

Wafer

44
 Double Patterning Lithography
MASK 2
MASK 1 Pattern Photoresist
Pattern Photoresist with 2nd pattern
with 1st pattern

Open BARC Etch

Etch Pattern in poly & Etch 2nd Oxide HM
(HM) Strip Resist &
BARC
Strip Resist & BARC
Etch HM Pattern Into Poly
Coat 2nd Barc
& Resist Layers
Strip HM

Photoresist Poly LELE Double Patterning (Poly Lines – Dual Hardmask)

BARC (bottom anti-reflection coating) Si Substrate

source: KLA Tencor
URL: http://www.sematech.org/meetings/archives/litho/8376/pres/O-DS-01_Robertson_KLA-T.pdf
Oxide (HM)

45
 Routing and DRC Fixing
CTS +
Clock routing

Pre-routing
checks and setup
Route signal nets

Routing Check DRCs

Optimization Incremental Routing

and Reroute

Routing

Signoff
46
 Route the Signal Nets

route_auto

• Initial routing entails global routing, track assignment and detail

routing – no post-route optimization
• To run the three phases individually:
route_global
route_track
route_detail

• Modify routing or crosstalk options, routing guides, or via

mapping rules and re-route, as needed
47
 Detail Route Iterations

• By default, route_auto performs a maximum of 40 detail route iterations

to fix DRCs
• If your technology requires more iterations, set the value using:

route_auto -max_detail_route_iterations 60

48
 Check Zroute DRC Violations
check_routes
• Checks signal and clock routing for physical DRCs, NDRs, shorts, opens, antenna and voltage area
violations
• Does not check DRCs amongst pre-routed nets only (e.g. P/G grid structure)

49
 Viewing Cell Internal Structures




• By increasing the view level alone, cell internal structures will not be
visible – important for understanding DRC violations
• You need to enable “Expanding cell types” for Standard
and/or Hard Macro cells
50
 Layout versus Schematic Check
• Use check_lvs to check for open, short, and floating nets
• Much quicker as it does not check for DRCs
• Errors can be displayed using the error browser
check_lvs -checks all -open_reporting detailed \
-check_child_cells true

open_reporting=detailed. GUI uses

arrow to shows exact open location.
Short indicator

51
 Detail Routing Loops
• Run additional detail route iterations at any time to fix DRC violations

route_detail \
-incremental true
-max_number_iterations 50
-coordinates {{llx1 lly1} {urx1 ury1} ...}

• With -coordinates, you can specify the routing area –

multiple rectangles are supported

52
 Rerouting Problematic Nets
• Nets that have DRC issues, huge delay due to excessive layer hopping or
crosstalk violations might benefit from being rerouted
• Use remove_routes to remove the net detail routing
• Use route_eco to reroute the net (global, track, detail)

• Remember that you can lock a net’s routing (if you’re satisfied with it) so that it
will not be touched by the router later:

set_attribute \
-objects [get_nets <dont_reroute_nets>] \
-name physical_status \
-value locked

53
 Optimization and Reroute
CTS +
Clock routing

Pre-routing
checks and setup

Routing
Optimize the design for
timing, crosstalk and power
Optimization
and Reroute Incremental Routing
Routing

Signoff
54
 Post Route Full Optimization
• Perform post-route optimization, which includes:
• Post route setup/hold timing optimization
• Logical DRC and Area optimization
• ECO placement and routing

route_opt

• Optionally enable Power, CTO and CCD optimization, as needed

• Application options that affect route_opt start with route_opt.*

55
 Post Route Optimizations: Power and CTO
• To enable power optimization:
set_app_options –name route_opt.flow.enable_power \ Default: false
-value true

• Power optimization, once enabled, is based on the scenario configuration

• Active scenario with leakage+dynamic: total power optimization
• Active scenario with leakage only: leakage power optimization

• If you are using the classic CTS flow, you can use the following to optimize
clock tree skew/latency:
after route_opt:
synthesize_clock_trees –postroute \
• Do not use if CCD is enabled detail_with_signal_routes
-routed_clock_stage

56
 Post Route Optimizations: CCD
• Enable concurrent clock and data optimization:
set_app_options –name route_opt.flow.enable_ccd \ Default:
-value true false

• Post-route CCD can be used even if classic CTS was used during clock_opt
• To enable CCD power recovery during route_opt:
set_app_options –name route_opt.flow.enable_clock_power_recovery \
-value none | auto | area | power

• CCD power recovery works on the clock cells and registers only
• By default (auto), if CCD is enabled, performs power recovery, otherwise none

57
 Using PrimeTime Delay Calculation
• Use the integrated PrimeTime delay calculator in ICC II when performing post-
route timing analysis and optimization with route_opt
• Improves accuracy and correlation with PrimeTime SI,
leading to overall faster timing closure

• PT delaycalc is enabled by default if using 2018.06 CLIBs 2018.06

• CLIBs must have been generated using Library Manager 2018.06 or later
• In earlier releases, or older CLIBs, the .db files of the reference libraries must
be available in addition to the NDM cell libraries (see notes)
• In this case, you have to enable PT delaycalc explicitly

58
 Using the PrimeTime Delay Calculator during
route_opt
• All route_opt optimizations are supported with PT delay calculation
# Align ICCII and PT timing analysis
set_app_options –name time.enable_ccs_rcv_cap -value true
set_app_options –name time.delay_calc_waveform_analysis_mode –value full_design
set_app_options -name time.si_enable_analysis -value true
set_app_options -name time.enable_si_timing_windows -value true

# PT delay calculation is enabled by default if using 2018.06+ CLIBs. Otherwise, enable explicitly (use
dbs)
# set_app_options –list {time.use_pt_delay true}

# Enable optional route_opt optimizations

set_app_options –name route_opt.flow.enable_ccd -value true
set_app_options –name route_opt.flow.enable_power -value true

route_opt
...
59
 StarRC InDesign
• In addition to using Primetime delay calculation, configure StarRC
advanced fusion extraction from within ICC II
• Transparently extracts the current block using the same CLIBs
• Recommendation: Use in combination with PrimeTime delaycalc
# set_app_options -name extract.starrc_mode -value fusion_adv
set_starrc_in_design -config ./scripts/starrc_config.txt

SIGNOFF_IMAGE: /apps/starrc_2019.12-SP4/bin/StarXtract
MAPPING_FILE: /…/tech/saed32nm_tf_itf_tluplus.map
CORNER_GRD_FILE: ./scripts/starrc_corner_grd.txt

ss_125c /remote/…/saed32nm_1p9m_Cmax.nxtgrd
ff_125c /remote/…/saed32nm_1p9m_Cmin.nxtgrd
ff_m40c /remote/…/saed32nm_1p9m_Cmin.nxtgrd
60
 Main References
• Rob Rutenbar “From Logic to Layout” 2013
• Synopsys University Courseware
• IDESA
• Kahng, et al. “VLSI Physical Design: From Graph Partitioning to Timing
Closure” – Chapter 6

61
 Routing in Innovus/Encounter
• The detailed routing engine used by Innovus/Encounter is called “NanoRoute”
• NanoRoute provides concurrent timing-driven and SI-driven routing.
• In addition, it can perform multi-cut via insertion, wire widening and spacing.
• The commands for running a route with NanoRoute are:
set_db route_design_with_timing_driven true 
set_db route_design_with_si_driven true 
route_design

• Following detailed route wire optimization and timing optimization:

set_db route_design_with_timing_driven false 
set_db route_design_detail_post_route_spread_wire true
set_db route_design_detail_use_multi_cut_via_effort high
route_design –wire_opt
set_db route_design_with_timing_driven true 
opt_design –post_route –setup ‐hold
62
Routing in Innovus/Encounter
• To achieve a high percentage of multi-cut vias:
set_db route_design_concurrent_minimize_via_count_effort high 
set_db route_design_detail_use_multi_cut_via_effort high 

• To check your design after routing:

report_route; # provide routing statistics
report_wires; # provides wire statistics including wirelength
time_design –post_route; # check timing after routing
check_drc; # Run a DRC check – in new techs: “verify_drc”
check_connectivity; # Run an LVS check

• To perform incremental routing (ECO routing):

set_db route_design_with_eco true 
route_global_detail