6.

012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-1

Lecture 9 - MOSFET (I)
MOSFET I-V Characteristics
March 6, 2003
Contents:
1. MOSFET: cross-section, layout, symbols
2. Qualitative operation
3. I-V characteristics
Reading assignment:
Howe and Sodini, Ch. 4, 4.1-4.3
Announcements: Quiz #1, March 12, 7:30-9:30 PM,
Walker Memorial; covers Lectures #1-9; open book; must
have calculator.
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-2
Key questions
How can carrier inversion be exploited to make a tran-
sistor?
How does a MOSFET work?
How does one construct a simple rst-order model for
the current-voltage characteristics of a MOSFET?
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-3
1. MOSFET: layout, cross-section, symbols
source
gate
drain body
gate oxide
inversion layer
channel
polysilicon gate
p
p
n
n
p
+
n
+
n
+
n
+
p
+
n
+
n
+
n
+
n
+
Key elements:
inversion layer under gate (depending on gate voltage)
heavily-doped regions reach underneath gate in-
version layer electrically connects source and drain
4-terminal device: body voltage important
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-4
2 Circuit symbols
Two complementary devices:
n-channel device (n-MOSFET) on p-Si substrate
(uses electron inversion layer)
p-channel device (p-MOSFET) on n-Si substrate
(uses hole inversion layer)
n
+
n
+
p
Bulk or
Body
Drain
Source
Gate
(a) n-channel MOSFET
D

G
I
Dp
B
p
+
p
+
n
Bulk or
Body
Drain
Gate
(b) p-channel MOSFET
Source
+
_
V
SG
D
S

G
+
+
_
V
GS
I
Dn
I
Dn
B
V
SD
> 0
V
DS
> 0
+
_
V
BS
+
_
V
SB
D
G
B
S
S S
B
D
G
I
Dp
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-5
2. Qualitative operation
Water analogy of MOSFET:
Source: water reservoir
Drain: water reservoir
Gate: gate between source and drain reservoirs
source drain gate
depletion region
inversion layer
n
+
p
n
+
V
GS
V
GS
D
G
S
B
V
DS
V
DS
I
D
water
Want to understand MOSFET operation as a function of:
gate-to-source voltage (gate height over source water
level)
drain-to-source voltage (water level dierence between
reservoirs)
Initially consider source tied up to body (substrate or
back).
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-6
Three regimes of operation:
2 Cut-o regime:
MOSFET: V
GS
< V
T
, V
GD
< V
T
with V
DS
> 0.
Water analogy: gate closed; no water can owregardless
of relative height of source and drain reservoirs.
depletion region
n
+ n
+
D
G
S
p
no inversion layer
anywhere
no water flow
V
GD
<V
T
V
GS
<V
T
I
D
= 0
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-7
2 Linear or Triode regime:
MOSFET: V
GS
> V
T
, V
GD
> V
T
, with V
DS
> 0.
Water analogy: gate open but small dierence in height
between source and drain; water ows.
depletion region
n
+ n
+
D
G
S
p
inversion layer
everywhere
V
GD
>V
T
V
GS
>V
T
Electrons drift from source to drain electrical current!
V
GS
|Q
n
| I
D

V
DS
E
y
I
D

V
DS
small V
DS
I
D
V
GS
>V
T
0
0
V
GS
V
T
small V
DS
I
D
V
DS
0
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-8
2 Saturation regime:
MOSFET: V
GS
> V
T
, V
GD
< V
T
(V
DS
> 0).
Water analogy: gate open; water ows from source to
drain, but free-drop on drain side total ow indepen-
dent of relative reservoir height!
depletion region
n
+ n
+
D
G
S
p
inversion layer
"pinched-off" at drain side
V
GD
<V
T
V
GS
>V
T
I
D
independent of V
DS
: I
D
= I
Dsat
V
DS
I
D
V
DSsat
=V
GS
-V
T
V
GDsat
=V
T
0
0
saturation
linear
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-9
3. I-V characteristics
Geometry of problem:
depletion region
inversion layer
n
+
p
n
+
V
BS
=0
V
GS
>V
T
D
G
S
B
0
L
y
V
DS
I
D
2 General expression of channel current
Current can only ow in y-direction:
J
y
= Q
n
(y)v
y
(y)
Total channel current:
I
y
= WQ
n
(y)v
y
(y)
Drain terminal current is equal to minus channel current:
I
D
= WQ
n
(y)v
y
(y)
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-10
I
D
= WQ
n
(y)v
y
(y)
Rewrite in terms of voltage at channel location y, V
c
(y):
If electric eld is not too big:
v
y
(y)
n
E
y
(y) =
n
dV
c
(y)
dy
For Q
n
(y) use charge-control relation at location y:
Q
n
(y) = C
ox
[V
GS
V
c
(y) V
T
]
for V
GS
V
c
(y) V
T
.
All together:
I
D
= W
n
C
ox
(V
GS
V
c
(y) V
T
)
dV
c
(y)
dy
Simple linear rst-order dierential equation with one un-
known, the channel voltage V
c
(y).
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-11
Solve by separating variables:
I
D
dy = W
n
C
ox
(V
GS
V
c
V
T
)dV
c
Integrate along the channel in the linear regime:
-for y = 0, V
c
(0) = 0
-for y = L, V
c
(L) = V
DS
(linear regime)
Then:
I
D

L
0
dy = W
n
C
ox

V
DS
0
(V
GS
V
c
V
T
)dV
c
or:
I
D
=
W
L

n
C
ox
(V
GS

V
DS
2
V
T
)V
DS
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-12
For small V
DS
:
I
D

W
L

n
C
ox
(V
GS
V
T
)V
DS
Key dependencies:
V
DS
I
D
(higher lateral electric eld)
V
GS
I
D
(higher electron concentration)
L I
D
(lower lateral electric eld)
W I
D
(wider conduction channel)
V
DS
small V
DS
I
D
V
GS
>V
T
0
0
V
GS
V
T
small V
DS
I
D
V
DS
0
This is the linear or triode regime.
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-13
In general,
I
D
=
W
L

n
C
ox
(V
GS

V
DS
2
V
T
)V
DS
Equation valid if V
GS
V
c
(y) V
T
at every y.
Worst point is y = L, where V
c
(y) = V
DS
, hence, equa-
tion valid if V
GS
V
DS
V
T
, or:
V
DS
V
GS
V
T
V
DS
I
D
V
GS
V
GS
=V
T
V
DS
=V
GS
-V
T
0
0
term responsible for bend over of I
D
:
V
DS
2
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-14
To understand why I
D
bends over, must understand rst
channel debiasing:
V
DS
0
0
0
y
L
L
L
y
y
|Q
n
|
|E
y
|
V
c
0
0
0
V
GS
V
T
V
DS
0 L
y
V
GS
-V
c
(y)
C
ox
(V
GS
-V
T
)
local gate
overdrive
Along channel from source to drain:
y V
c
(y) |Q
n
(y)| |E
y
(y)|
Local channel overdrive reduced closer to drain.
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-15
Impact of V
DS
:
0
0
y
L
L
L
y
y
|Q
n
|
V
c
0
0
0
0
V
DS
V
DS
V
DS
V
DS
=0
V
DS
=0
V
DS
=0
|E
y
|
As V
DS
, channel debiasing more prominent
I
D
rises more slowly with V
DS
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-16
1.5 46.5 NMOSFET
Output characteristics (V
GS
= 0 3 V, V
GS
= 0.5 V ):
Zoom close to origin:
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-17
Transfer characteristics (V
DS
= 0.1 V ):
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 9-18
Key conclusions
The MOSFET is a eld-eect transistor:
the amount of charge in the inversion layer is con-
trolled by the eld-eect action of the gate
the charge in the inversion layer is mobile con-
duction possible between source and drain
In the linear regime:
V
GS
I
D
: more electrons in the channel
V
DS
I
D
: stronger eld pulling electrons out
of the source
Channel debiasing: inversion layer thins down from
source to drain current saturation as V
DS
approaches:
V
DSsat
= V
GS
V
T