ADC1

ADC2
CH12data A A A A A A
1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3
Legend
Idle Time (due to delay : 6cycles must separate sampling ADC1 and Sampling ADC2)
Sampling time : 3 cycles
Delay between sampling of 2 ADC : 6 cycles
Convertion phase : 8 cycles (resolution=8bit ==> Conversion time = 8 cycles)
A Converted data availble
A A A
4 5 6 1 2 3 4 5 6 1 2 3 4 5 6
Idle Time (due to delay : 6cycles must separate sampling ADC1 and Sampling ADC2)